JPH04140812A - Information processing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a means for supplying a clock to each circuit in an information processing system having a plurality of semiconductor integrated circuits operated by a clock, and The present invention relates to a method of controlling an operating clock of a computer.

[Prior Art] An information processing system constructed from a plurality of semiconductor integrated circuits according to the prior art is as shown in FIG.

The method for supplying clocks to each semiconductor integrated circuit 16, 36, 46 is as follows: 1. A clock of a frequency required within each semiconductor integrated circuit 16, 36, 46 is supplied by clock generation circuits 61 to 63 outside the semiconductor integrated circuit. The semiconductor integrated circuit 16, 36, 46 was created and supplied via the clock lines 110 to 112 on the printed circuit board on which the semiconductor integrated circuit 16, 36, and 46 was mounted. , C.P.
U (Central Processing Un)
JP-A-64-6
As described in Japanese Patent No. 2023, there is a semiconductor integrated circuit 76 that includes a phase-locked loop circuit 66 (hereinafter also referred to as PLL) to generate a stable clock within the semiconductor integrated circuit.

[Problems to be Solved by the Invention] The above-mentioned conventional technology shown in FIG. In order to use the clock as it is as an internal operating clock, one or more clock generation circuits 61, 62, 63 corresponding to the speed performance of the semiconductor integrated circuit 16, 36, 46 are required, which reduces system cost. The problem was that it was expensive.

In addition, since the CPU 16 and the I10 controller 36.46 have different tarock sources, when the CPU 16 accesses the 1.10 controller 36.46, it becomes an asynchronous access for the I10 controller 36.46, causing a timing loss for synchronization, and the system There was a problem that the performance of the system deteriorated.

In addition, the clock input to each I10 controller 36.46 is transmitted from an external clock generation circuit 62.63 to the wiring pattern on the printed circuit board (clock lines 111 to 114).
Therefore, if the clock has a high frequency, there is a problem in that a large amount of radio interference noise is generated from the wiring pattern through which the clock is transmitted.

Furthermore, in the prior art shown in FIG. 7, each functional block (C
P, U17. Memory 27. I10 controller 37.4
Since the same clock is sent to 7), the above-mentioned problem does not occur, but if there are a plurality of such semiconductor integrated circuits, the above-mentioned problem occurs. However, no consideration has been given to this issue.

An object of the present invention is to provide an information processing system having a plurality of semiconductor integrated circuits in which timing loss due to synchronization is reduced and system performance is improved.

Means for Solving the Problems] In order to achieve the above object, the present invention provides an information processing system including a semiconductor integrated circuit having a plurality of PLLs (phase locked loops) and supplying a clock signal to the PLLs. Each of the -1- semiconductor integrated circuits has a clock generation circuit, and each of the semiconductor integrated circuits described in -1- is operated by a clock signal output from the PLL that each has, and each of the semiconductor integrated circuits operates by a clock signal output from the PLL, and each of the semiconductor integrated circuits operates by a clock signal output from the PLL. It is equipped with a synchronization circuit for synchronizing with signals.

[Operation] The clock signal from the clock generation circuit is input to the PLL provided in each semiconductor integrated circuit, and based on this, the PLL operates as described above according to the division ratio of the frequency divider inside the PLL. A clock signal with a frequency multiplied by the input clock signal is output.

Therefore, since they are synchronized with the tarock signals of other circuits, each circuit can set optimal timing for access control signals from other circuits, and at the same time, the circuit scale of the synchronization circuit can be reduced.

In addition, the built-in phase-locked loop circuit described above allows
Since a clock signal with a multiplied frequency can be generated, a multiplied clock signal can be selected as the clock signal in each semiconductor integrated circuit.

In addition, even if the frequency of the external clock signal is set to a low frequency to the extent that a large amount of electromagnetic noise is not generated from the wiring pattern existing on the printed circuit board, each semiconductor integrated circuit internally maintains its own required frequency. clock signal can be generated.

[Example code] Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a configuration diagram of an information processing system described in the present invention. In this system, a CP'UI, a memory 2, and I10 devices each target are
The controllers 3 and 4 are mounted on independent semiconductor integrated circuits 7 to 1o, respectively.

Each of the semiconductor integrated circuits 7 to 10 is connected to a clock line 11 for transmitting a clock signal generated by an external clock generation circuit 6 and a control bus 12 for transmitting control information etc. between each semiconductor integrated circuit. be done.

The control bus 12 is a means for the CPU 1 to select a circuit whose frequency is to be changed and output a control signal to the selected circuit to control its output frequency.

Each of the semiconductor integrated circuits 7 to 10 includes, for example.

In addition to functional block circuits such as a CPU, a phase locked loop circuit (PLL) 5 is incorporated.

A tarock signal input to this circuit 5 from an external clock line 11 is transmitted to the CPU 1 via a control bus 12.
The phase-locked loop circuit 5 converts the frequency into a predetermined frequency according to control information from the phase-locked loop circuit 5.

The obtained clock signal is then supplied via internal clock lines 131 to 134 to functional block circuits that require a clock signal within each semiconductor integrated circuit.

In addition, if it includes a circuit that does not require a clock signal,
There is no need to supply a clock signal to that circuit. For example, with respect to the memory 2, there are some types of memory that do not require a clock signal, and there is no particular need for a clock signal to be supplied by a phase-locked loop circuit.

FIG. 2 is a configuration diagram of a phase-locked loop circuit mounted in each semiconductor integrated circuit 6 This figure shows the case of a PLL 5 mounted in a semiconductor integrated circuit 7, but other semiconductor integrated circuits 8 to PLL5 installed in 10 has a similar configuration.

The clock signal supplied via the clock line 11 is input to the 1-phase comparator 16, which compares the input signal with the output of the frequency divider circuit 15, and inputs the output signal to the low-pass filter 17. The output signal of 17 is input to a voltage controlled oscillator (VC○) 18.

A clock signal 131 outputted from the VCO 18 is input to the frequency divider circuit 15, frequency-divided to a frequency division ratio set by control information from the CPUI, and input to the phase comparator 16.

As mentioned above, the phase-locked loop circuit installed in each semiconductor integrated circuit has an internal frequency divider circuit, and the frequency division ratio can be freely controlled. It is possible to set the frequency to be a multiple of the clock signal generated by the circuit 6.

Next, the frequency dividing circuit will be explained.

FIG. 5 is a block diagram of a programmable frequency divider capable of dividing the frequency by 1/2, 1/3°, .

Here, 20.21.22 is for 1/2 frequency division.

23 is used for latching signals.

The control bus input terminal 26 becomes a high level only for the circuit selected by the CPU as the target for changing the frequency, and at that time, a signal corresponding to the high frequency set to the control bus input terminal 205, 215, 225 is input. .

The control bus input terminal 26 is a signal obtained by decoding an address signal issued by the CPU by a decoder, and in this way, a circuit whose frequency is to be changed is arbitrarily selected.

The input clock signal to this circuit is input as a clock signal to the first stage flip-flop 20, and the subsequent flip-flops 21 and 22 receive the inverted output Q of the previous stage as a clock input. The D input terminals of the flip-flops 2o to 22 have their own inverted outputs or the control bus input terminal 205.
, 215° and 225 are selected depending on the level of the signal from the control bus input terminal 26.

The outputs of the frequency dividing flip-flops 20 to 22 are as follows:
After the logical product (AND) is taken.

It becomes the output of this frequency dividing circuit and is outputted from the clock output terminal j25.

In this circuit, normal branch operation is performed when the signal from the control bus human power conductor 26 is at the 'L level' level, but by setting this signal to 'H', it becomes possible to write to set the branch station level. , control input terminals 205, 215.22
The frequency division ranges from 1/2 to 1/8 depending on the signal level from 5 to 1/8.

If the number of cycles is changed by the control signal from the CPU in this way, for example, if there are multiple CPUs in one information processing system and the frequency of the clock signal of the CPUs differs depending on the CPU, the CPU will By doing so, the frequency of the clock signal of each circuit other than the CPU can be changed.

Next, we will discuss timing loss.

FIG. 3(A) shows a conventional synchronization circuit for control signals for accessing between blocks operating asynchronously, and FIG. 3(B) shows its timing chart.

In the mask slave type flip-flops 19a and 19b shown in FIG. and enters the master flip-flop 19a. The slave flip-flop 19b receives the output from the master flip-flop 19a (flows through the signal line 121) at the rising edge of the clock signal flowing through the clock line 111, and outputs a synchronized control signal (flows through the signal line 122).

The slave flip-flop 19b is intended to avoid the metastable state of the output of the master flip-flop 19a, but in the synchronous circuit used in the conventional system, as shown in FIG. 3(B), the clock signal 110
Since there is a phase difference Δφ between the control signal flowing through the signal line 120 and the control signal flowing through the signal line 120, the control signal flowing through the synchronized signal line 122 is at most 1.5 times larger than the original signal flowing through the signal line 120.
There is a possibility that there will be a clock delay.

On the other hand, FIG. 4(A) shows a control signal synchronization circuit according to the present invention, and FIG. 4(B) shows its timing chart.

FIG. 4 shows a synchronous circuit provided inside the I10 controller A3, and the memory 2, I10 controller B4
The same applies to the synchronous circuit provided inside.

As shown in FIG. 4(B), the control signal flowing through the signal l1A120 is synchronized with the clock signal inputted through the clock line 133, so there is almost no one phase difference. It is best to import the data using an edge with a delayed clock.

The synchronized control signal flowing through the signal line 123 obtained in this way is
- Since the delay is only 0.5 clock, the timing loss is smaller than when using the master-slave flip-flop.

Furthermore, since the synchronous circuit itself does not need to be a master/slave flip-flop as shown in FIG. 3(A), the circuit can be simplified.

The present invention is configured as described above.

It has the following effects.

A phase-locked loop circuit is built into a plurality of semiconductor integrated circuits such as I10 controllers, and the low-speed clock from the only clock generation circuit in the system or the low-speed clock signal from the CPU is connected to a PL provided in each semiconductor integrated circuit.
Based on this, the PLL changes the division ratio of the frequency divider inside the PLL to output a clock signal of not only the same frequency but also any frequency for the input clock signal. do.

Therefore, even if the frequency of the external clock signal is set to a low frequency to the extent that a large amount of electromagnetic noise is not generated from the wiring pattern existing on the printed circuit board, each semiconductor integrated circuit internally receives a clock signal at the required frequency. can be generated.

Therefore, it is possible to prevent radio interference noise caused by this clock signal.

Furthermore, since the built-in phase-locked loop circuit can generate a tarock signal with a multiplied frequency, a multiplied clock signal can be selected as the clock signal in each semiconductor integrated circuit.

In addition, since it is synchronized with the clock signal of other circuits, each circuit can perform optimal timing settings for access control signals from other circuits.

At the same time, the circuit scale of the synchronous circuit can be reduced.

Furthermore, since tarock signals synchronized with each functional block are used, timing loss during access between circuits can be reduced, and the circuit for synchronization can be simplified.

In addition, since a clock signal corresponding to the speed performance can be supplied to each semiconductor integrated circuit based on the reference clock signal from a single clock generation circuit, only one clock generation circuit is required, reducing system costs. According to the present invention, it is possible to provide an information processing system having a plurality of semiconductor integrated circuits in which timing loss for synchronization is reduced and system performance is improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an information processing system showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a phase-locked loop shown in FIG. 1, and FIG. 3 is a conventional control signal synchronization circuit and its configuration. 4 is an explanatory diagram of the timing chart of the present invention, and FIG. 4 is an explanatory diagram of the synchronous circuit of the present invention and its timing chart.
The figure is a block diagram of the two frequency divider circuits shown in Figure 2,
FIG. 7 is a configuration diagram of a conventional information processing system. 1...CPU, 2...Memory, 3.4...I10
Controller, 5... Phase locked loop circuit, 7 to 10
...Semiconductor integrated circuit, 15...Frequency divider circuit, 16...
- Phase comparator, 17 low-pass filter, 18...voltage controlled oscillator.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit having a plurality of PLLs (phase-locked loops) and a clock generation circuit that supplies a clock signal to the PLL, each of the semiconductor integrated circuits having a What is claimed is: 1. An information processing system comprising a synchronizing circuit that operates according to a clock signal output from a PLL and synchronizes signals from other circuits with the clock signal output from the PLL. 2. At least one of the semiconductor integrated circuits has a CPU (
2. The information processing system according to claim 1, wherein the information processing system is a central processing unit. 3. The CPU arbitrarily selects a semiconductor integrated circuit from among the semiconductor integrated circuits and outputs a control signal for controlling the output frequency of the PLL included in the selected semiconductor integrated circuit. 3. The information processing system according to claim 1, wherein the PLL has means for setting the frequency of the clock signal output based on a control signal from a CPU.