JPH04142823A - Data transmission system - Google Patents

Abstract

PURPOSE:To establish synchronization in a short time by confirming super-frame synchronization at every frame when the data of a super-frame form is received. CONSTITUTION:A receiver receiving the data of a super frame form composed of plural frames having a respective frame synchronization pattern is provided and a frame synchronization pattern 14 included in an incoming data is detected and a frame pattern detection circuit 1 outputs a frame pattern detection signal 15. Then the super frame synchronization state is confirmed at every frame based on a frame number included in the incoming data. Thus, even when the super frame is considerably long, the super-frame synchronization is implemented in a short time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a super frame synchronization method for digital communication. This allows synchronization to be established in a short period of time by using three steps.

[Prior Art] In the conventional super-frame synchronization method, a super-frame pattern is inserted into the data string every super-frame period as shown in Fig. 3, so backward protection is required to establish super-frame synchronization. If the number of times is N, the superflare l, and the period is TS, then the time T
Requires sxN.

[Problem to be solved by the invention]

In the conventional example, the super frame pattern is inserted into the data string every super frame period, so if the backward protection is N' times and the super frame period is T, the time required to establish super frame synchronization is T, In general, if Ts is the frame period Tr and the number of frames is k, then TS=k・
The disadvantage is that it takes a long time to establish super frame synchronization.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission system that eliminates such drawbacks and has a means for shortening the time required to establish super-frame synchronization.

[Means to solve the problem]

The present invention provides a data transmission system that includes a receiving device that receives data in a superframe format consisting of a plurality of frames each having a frame synchronization pattern, in which each of the frames constituting the superframe has a respective A frame number is assigned to a time slot following a frame synchronization pattern, and the receiving device includes synchronization confirmation means for confirming a super frame synchronization state for each frame based on a frame number included in incoming data. It is characterized by

Here, the synchronization confirmation means includes a pattern detection means that detects a frame synchronization pattern included in incoming data and outputs a pattern detection signal, and a first pattern detection means that delays the pattern detection signal and outputs a frame number latch signal. a delay means; a frame number signal generation means for extracting a frame number included in incoming data and outputting a received frame number signal corresponding to the frame number; a latch means for outputting a number signal; a frame number counting circuit for outputting a frame count value signal in which a latched frame number signal is loaded in response to a load signal and incremented by a pattern detection signal; and a frame number counting circuit for receiving the frame count value signal. a comparison circuit that compares the frame number signals and outputs a match signal when they match, and outputs a mismatch signal when they do not match; a backward protection means that outputs a synchronization pulse signal when the match signal occurs N times in a row; forward protection means that outputs an asynchronous pulse signal when the number mismatch signal continues M times; a state signal that is set by the synchronous pulse signal by the initial setting signal and reset by the mismatch signal and indicates a super frame synchronization state; a first flip-flop means whose status signal is initialized to false by an initialization signal; a first gate means which allows a mismatch signal to pass when the status signal is false; A second flip-flop means is reset by the signal output from the first gate means and outputs a backward synchronization protection process signal, and this backward synchronization protection process signal is initialized to false by the initialization signal; It is preferable to include a second delay means for outputting a timing signal based on a backward synchronization protection process signal, and a second gate means for controlling a timing signal using a backward synchronization protection process signal and outputting a load signal.

[Effect]

Each of the frames constituting the superframe has a frame number assigned to the time slot following its frame synchronization pattern.

This frame synchronization pattern is detected and a pattern detection signal is output, and a frame number latch signal is output by adding a delay to this pattern detection signal. On the other hand, a frame number is extracted, a received frame number signal corresponding to this frame number is output, this received frame number signal is latched by a frame number latch signal, and a latched frame number signal is output. A latched frame number signal is loaded in accordance with the load signal, and a frame count value signal incremented by the pattern detection signal is output. This frame count value signal and the received frame number signal are compared, and if they match, a match signal is output, and if they do not match, a mismatch signal is output. A synchronous pulse signal is output when the match signal occurs N times in a row, and an asynchronous pulse signal is output when the frame number mismatch signal occurs M times in a row.

It is set by the sync pulse signal by the initial setting signal and IJ-1z is set by the mismatch signal, outputs a state signal indicating the super frame synchronization state, and this state signal is initialized to false by the initial setting signal, and the state signal is set to false by the initial setting signal. Allow the mismatch signal to pass when . It is set by a match signal, reset by a signal indicating this permission, and outputs a backward synchronization protection process signal, which is initialized to false by an initialization signal. Further, a timing signal is output by giving a delay to the pattern detection signal. The timing signal is controlled by the backward synchronization protection process signal and the load signal is output.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the frame format of this embodiment.

At the beginning of each frame is a frame pattern that determines the beginning position of the frame, followed by a frame number. If the super frame is composed of a number of frames,
This frame number increases by one from "0" to rk-IJ, returns to "0", and continues counting up again.

FIG. 1 shows the configuration of this embodiment.

In this embodiment, as shown in FIG.
A frame pattern detection circuit 1 detects a frame pattern indicating the start position of each frame of 4 and generates a frame pattern detection signal 15, a serial parallel circuit 2 converts the received data signal 14 into parallel data, and a frame pattern detection signal The frame pattern detection signal 15 is sent to the frame number counting circuit 6 having a count value from "O" to rk-IJ by delaying the frame number latch signal 15, and the frame pattern detection signal 15 is serial-parallel converted by the frame number latch signal 17 delayed by the delay circuit 4. A delay circuit 3 generates a timing signal 16 to load a latched frame number signal 19 obtained by latching the number signal 18 to the data latch circuit 5, and a load signal 21 gates the timing signal 16 by a backward synchronization protection process signal 22.
The frame count value signal 20 of the frame number counting circuit 6 and the received frame number signal 18 after serial/parallel conversion are compared with the frame count value signal 20 of the frame number counting circuit 6 and the frame count value signal 20 of the frame number counting circuit 6 is serially/parallel converted. When the received frame number signal 18 matches the frame number match signal 2,
3, and outputs a frame number mismatch signal 24 when the frame count value signal 20 of the frame number counting circuit 6 and the received frame number signal 18 after serial/parallel conversion do not match, and a frame number match signal. A backward N times synchronization protection circuit 9 outputs a synchronization pulse signal 25 when 23 is true for N frames consecutively, and an asynchronous pulse signal is output when the frame number mismatch signal 24 is true for consecutive M frames. Forward M times synchronization protection circuit 1 outputting signal 26
0, an R-S flip-flop circuit 12 that is set by a synchronization pulse 25, reset by an asynchronous pulse signal 26, and outputs a super frame synchronization state signal 28, and a frame number when the super frame synchronization state signal 28 is false. The AND circuit 11 which does not inhibit the mismatch signal 24 and the super frame synchronization state signal 28 which is set in a false state by the frame number match signal 23 causes the frame number mismatch signal 24 to be set.
and an R-S flip-flop circuit 13 that is reset by and outputs a backward synchronization protection process signal 22.

That is, as shown in FIG. 1, this embodiment includes a receiving device that receives data in a superframe format consisting of a plurality of frames each having a frame synchronization pattern, and the frames constituting the superframe. Each of these has a configuration in which a frame number is assigned to the time slot following the frame synchronization pattern of each, and the receiving device performs synchronization that checks the super frame synchronization state for each frame based on the frame number included in the incoming data. The synchronization confirmation means includes a frame pattern detection circuit 1 which is a pattern detection means for detecting a frame synchronization pattern 14 included in incoming data and outputting a frame pattern detection signal 15, and a frame pattern detection circuit 1 which detects a frame synchronization pattern 14 included in incoming data and outputs a frame pattern detection signal 15. a delay circuit 4 having a second delay means for outputting a frame number latch signal 17 by applying a delay to the frame number latch signal 17;
A serial-to-parallel conversion circuit 2 which is a frame number signal generating means that extracts a frame number included in incoming data and outputs a received frame number signal 18 corresponding to this frame number.
and a data latch circuit 5 which is a latch means for latching the received frame number signal 18 with a frame number latch signal 17 and outputting a latched frame number signal 19; A frame number counting circuit 6 that outputs a frame count value signal 2o incremented by the frame pattern detection signal 15 compares the frame count value signal 20 and the received frame number signal 18, and when they match, outputs a frame number matching signal. 23
a comparison circuit 7 that outputs a frame number mismatch signal 24 when the frame number match signal 23 does not match, and a backward M times synchronization protection circuit that is a backward protection means that outputs a synchronization pulse signal 25 when the frame number match signal 23 occurs N times in a row. 9 and the asynchronous pulse signal 2 when the frame number mismatch signal 24 continues M times.
The forward M-time synchronization protection circuit 10 is a forward protection means that outputs 6, and the super frame synchronization state is set by the synchronization pulse signal 25 according to the initial setting signal 27 and reset by the frame number mismatch signal 24, indicating a super frame synchronization state. The RS flip-flop circuit 12, which is a first flip-flop means, outputs a signal 28, and this super frame synchronization state signal 28 is initialized to false by the initialization signal 27, and when the super frame synchronization state signal 28 is false. The AND circuit 11 is a first gate means for allowing the frame number mismatch signal 24 to pass through, and the frame number match signal 23 is set, and the backward synchronization protection process signal 22 is reset by the signal output from the first gate means. This backward synchronization protection process signal 22 is output to the R-S flip-flop circuit 13, which is a second flip-flop means, which is initialized to false by the initial setting signal 27, and the frame pattern detection signal 15 is delayed to determine the timing. It includes a delay circuit 3 as a second delay means for outputting the signal 16, and an AND circuit 8 as a second gate means for controlling the timing signal 16 by the backward synchronization protection process signal 22 and outputting the load signal 21.

Next, the operation of this embodiment will be explained based on FIG.

The R-S flip-flops 13 and 12 are initialized by the initialization signal 27 so that the super frame synchronization state signal 28 and the backward synchronization protection process signal 22 are both false.

Next, when the frame pattern detection circuit 1 outputs the frame pattern detection signal 15, this frame pattern detection signal 15 is delayed by the delay circuit 4, and the received frame number signal 18 is converted from serial to parallel by the serial to parallel conversion circuit 2. The frame number latch signal 17 is latched by the data latch circuit 5.

Let the frame number latched at this time be "I".

The latched frame number signal 19 latched by the data latch circuit 5 delays the frame pattern detection signal 15 by the delay circuit 3, and is loaded into the frame number counting circuit 6 by the load signal 21 that passes through the AND circuit 8. That is, the frame number counting circuit 6 is set to "1". The load signal 21 is output through the AND circuit 8 because
This is because the R-S flip-flop circuit 13 initializes the backward synchronization protection process signal 22 to false using the initialization signal 27. The frame number counting circuit 6 is counted up by the frame pattern detection signal 15 of the next frame, that is, the frame with frame number r i +14, and the count value signal 20 of the frame number counting circuit becomes r1+IJ. Also,
Since the received frame number signal 18 subjected to serial/parallel conversion in the ri+IJ frame should become r i + l J, the frame number-match signal 23 is output from the comparison circuit 7 . At this time, the backward synchronization protection process signal 22 of the R-S flip-flop circuit 13 becomes true. In the next ri+2J frame, the load signal 21 is not output from the AND circuit 8, so the frame number counting circuit 6 uses the frame pattern detection signal 15 to change the frame number "1+1" of the previous frame stored in the frame number counting circuit 6 to "1"
is added, and ri+2J is output as the frame count value signal 20. Therefore, the frame number match signal 23 becomes true in this frame as well. When the coincidence signal 23 becomes true for N consecutive frames, the frame number counting circuit 6 assumes that it is completely synchronized with the frame number and sends a synchronization pulse signal from the backward N times synchronization protection circuit 9. 25 is output, the R-S flip-flop is set, and the super frame synchronization status signal 28 becomes true. If an incorrect frame number is latched in the frame number counting circuit 6 due to a transmission path error, or if there are frames whose frame numbers do not match N times in a row before matching, the R-S flip-flop circuit 13 is reset. Then, the frame number of the next frame is again loaded into the frame number counting circuit 6 in the above-described procedure, and from the next frame, the frame count value signal 20 of the frame counting circuit 6 and the received frame number signal 18 are again compared. .

Once the super frame synchronization status signal 28 becomes true,
Unless the frame count value signal 20 of the frame number counting circuit 6 and the received frame number signal 18 do not match M times in succession, the R-S flip-flop circuit 12 is not reset and the super frame synchronization state signal 28 remains true. It does not change. However, if the frame count value signal 20 and frame number signal 18 do not match M times in a row, an asynchronous pulse signal 26 is output from the forward M times synchronization protection circuit 10, and the super frame synchronization state signal 28 becomes false. . If the mismatch signal 24 is output even once during the next N frames, R
-S flip-flop circuit 13 is also reset, and the whole becomes the initial state. If the mismatch signal 24 is not output even once during N frames and all the signals are match signals, the super frame synchronization state signal 28 becomes true again.

〔Effect of the invention〕

As explained above, the present invention verifies super frame synchronization frame by frame, so it has the advantage of being able to establish super frame synchronization in a short time even if the super frame is extremely long. Furthermore, even if the received frame number slips, it is possible to return to the asynchronous state in a short time and proceed to the resynchronization procedure.

4,

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a frame format diagram showing the structure of a data signal used in the embodiment of the present invention. FIG. 3 is a frame format diagram showing the structure of a data signal used in a conventional example. DESCRIPTION OF SYMBOLS 1... Frame pattern detection circuit, 2... Serial-to-parallel conversion circuit, 3.4... Delay circuit, 5... Data latch circuit, 6... Frame number counting circuit, 7... Comparison circuit , 8.11...AND circuit, 9...Backward N times synchronization protection circuit, 10...Forward M times synchronization protection circuit, 12.1
3...R-S flip-flop circuit. Patent applicant: IEI Hondenki Co., Ltd. Agent: Naotaka Ide, patent attorney

Claims (1)

[Scope of Claims] 1. In a data transmission system including a receiving device that receives data in a super frame format consisting of a plurality of frames each having a frame synchronization pattern, each of the frames constituting the super frame has a structure in which a frame number is assigned to the time slot following each frame synchronization pattern, and the receiving device has synchronization confirmation means for confirming the super frame synchronization state for each frame based on the frame number included in the incoming data. A data transmission method characterized by: 2. The synchronization confirmation means includes a pattern detection means that detects a frame synchronization pattern included in incoming data and outputs a pattern detection signal, and a first delay that delays the pattern detection signal and outputs a frame number latch signal. means for extracting a frame number included in incoming data and outputting a received frame number signal corresponding to the frame number; latching the received frame number signal with a frame number latch signal; a latch means for outputting a frame number signal; a frame number counting circuit for outputting a frame count value signal loaded with a latched frame number signal in response to a load signal and incremented by a pattern detection signal; Compares the received frame number signal and outputs a matching signal when they match.
A comparison circuit that outputs a mismatch signal when there is a mismatch, a backward protection means that outputs a synchronous pulse signal when a match signal occurs N times in a row, and a forward protection circuit that outputs an asynchronous pulse signal when a frame number mismatch signal occurs M times in a row. protection means and a first flip-flop which is set by the sync pulse signal by the initialization signal and reset by the mismatch signal to output a state signal indicative of a super-frame synchronization condition, which state signal is initialized to false by the initialization signal; first gating means for allowing the mismatch signal to pass when the status signal is false; a second flip-flop means which outputs a backward synchronization protection process signal and whose backward synchronization protection process signal is initialized to false by an initialization signal; a second delay means which delays the pattern detection signal and outputs a timing signal; and a backward synchronization protection process signal. 2. The data transmission system according to claim 1, further comprising second gate means for controlling the timing signal and outputting the load signal.