JPH04169961A - Parallel processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention generally relates to parallel processors in which microprocessors are interconnected.

More specifically, the present invention relates to a method for testing parallel processors and the configuration of element processors (microprocessors) for testing.

[Conventional technology]

A common method for testing parallel processors is failure analysis using a tester. but.

Testers have problems such as the presence of ICs that are difficult to mount test probes on, such as expensive surface-mounted components. As a countermeasure to this problem, boundary scan may be applied. Boundary scan is JTAG (Jo, i
, nt Te5t Action Group) proposed a method for facilitating testability of printed circuit boards. ! It is a standard. For example, Nikkei Electronics, 1989゜1
2, il (no, 488), page 316, Figure A-1 is shown in Figure 14. In FIG. 14, 700 is a board, 110-1 to 110-4 are LSIs,
410-1 to 410-5 are wirings between LSIs. 11
5 is a shift register added for testing, 211 is a scan in for inputting test data, 213
-1 to 213-3 are scan paths for passing test data, and 212 is a scan out for outputting test data. In boundary scan, LSL
A test circuit (shift register 115) is added to all input/output cells of llo-1 to 110-4. These L
Sllo-1 to 110-4 are connected in series, and the test data path (scan path 213-1 to 213-3) is connected in series.
)make.

Edge connectors (Scan-in 211, Scan-in
LSIIIO-1 to 110-4 are accessed from the output 212). Both the input of test data from scan-in 211 and the output of test data from scan-out 212 are performed serially.

[Problem to be solved by the invention]

- In the above prior art, test data input (from scan-in) is serial. Therefore, when the above-mentioned conventional technique is applied to a parallel processor (in which a plurality of microprocessors are interconnected), there is a problem that the number of element processors (microprocessors) increases and the time required to input test data increases. In addition, in the above conventional technology, redundant circuits (shift register, scan-in,
(scan path, scan out) is required.

An object of the present invention is to provide a method for testing parallel processors and a method for configuring element processors for this purpose, in which the time for inputting test data does not depend on the number of element processors, and increase in unnecessary circuits is suppressed. That's true.

[11! Means for Solving the Problem] In order to achieve the above objective, the data transmission buffer and data reception buffer in all element processors are
The configuration is such that it is connected in parallel to a test data input/output path from outside the LSI without going through other parts within the element processor.

[Operation] In the present invention, the data transmission buffer and data reception buffer in each element processor are used for test data input and
Connected in parallel to the output bus.

Therefore, input of test data to each element processor can be executed in parallel. The test procedure is shown below.

The following example shows the test data manual/output node number,
This is an example using a data bus. Therefore, addition of scan-in and scan-out is unnecessary.

In the present invention, each element processor is tested simultaneously using the same data. Therefore, it is not necessary to add scan /<.

1 (or 0) of the wiring that interconnects the element processors.
) if you want to test for stuck-at faults.

■ All '0's are sent from outside the LSI to the data transmission nodes in all element processors via the data bus.
(all '1') is written.

(1'4) Data is transmitted from each processor to a data receiving buffer in another processor to which it can be transferred.

■ The data transferred to the IB in each PE is sequentially read out to the outside of the LSI via the data bus.

If it is other than all 10' (all '1'), this means that a 1 (or 0) stuck-at fault exists in the wiring used for data transfer from the data transmission buffer to the data reception buffer.

Here, the data transmission buffers and data reception buffers in all the element processors are connected to the data bus without going through other parts in the element processor. Therefore, 0 or 1 of the wiring interconnecting the element processors is not affected by the failure of element processors other than buffers.
Can test for stuck-at faults.

The arithmetic processing functions of the element processors are, for example, the following a) ~
C) can be tested.

a) Write test data from outside the LSI to the data reception buffers in all element processors via the data bus.

b) Perform arithmetic processing using the test data in the data reception buffer as input data of the ALU, and output the calculation result to the data transmission buffer in the same element processor.

C) Read and check the calculation results stored in the data transmission buffers in each element processor to the outside of the LSI via the data bus.

Here, in the test of the arithmetic processing functions of the element processors, wiring interconnecting the element processors is not used.

〔Example〕

Hereinafter, five embodiments of the present invention will be explained with reference to FIGS. 1 to 13.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 600 is a parallel processor, 100-1
- 100-4 are element processors (hereinafter referred to as PEs) constituting the parallel processor 60°, 400-1 to 400-4
is a wiring connecting PEs. 150-1 to 150-4 are input cover IBs that temporarily store data sent from other PEs, and 160-1 to 160-4 are other PEs.
Output buffer OB that temporarily stores data to be sent to.

210 is a test data input/output bus. In FIG. 1, IBs 150-1 to 150-4 and OBs 160-1 to 160-4 in all PEs are connected in parallel to a test data input/output bus 210. Furthermore, the configuration is such that data can be read and written to and from the test data input/output bus 210. FIG. 2 shows an example of a control circuit for reading and writing data.

In FIG. 2, a data bus is used as the input/output bus 210 for test data. In addition, only PE100-1
It shows the input/output circuit to B or OB. LO5-1
is the other part of PE excluding the input/output circuits to IB and OB. PE100-2 to PE100-4 have the same configuration as PELOO-1. In FIG. 2, 220 is the test mode/
'signal TEST for switching non-test mode;
230 is a signal l0BSEL that specifies whether to access IB or OB, 240 is a test strobe signal TSTRB, and 250 is a signal R/ that specifies reading and writing of data between PE and data bus 210.
It is W. An example of a truth table is shown in FIG.

When TEST220 is O, it is a non-test mode,
Data input/output between IB, QB and the data bus is prohibited. When TEST220 is 1, the test mode is entered. In test mode.

When TSTRB140 is 1, data is input/output between the PE and the data bus. If R/W 250 is 1, data is written from the data bus to IB or OB.

If R/W250 is 0.

Data is read from IB or OB onto the data bus. Whether to access IB or OB,
This is done with l0BSEL230.

When l0BSEL230 is O, OB becomes the access target. When l0BSEL230 is 1, IB becomes the access target.

FIG. 3 is a block diagram showing an example of the PE 105-1 shown in FIG. 2, excluding the input/output circuits to the IB and OB.

In Figure 3, 111 is an arithmetic logic unit (ALU)
, 120 is a shifter (SFT), 130 is a general-purpose register (
REG), 140 is a working register (REG (W)) for storing intermediate results of calculations, 150 is an input buffer (IB) for temporarily storing input data from other PEs, 16
0 is an output buffer (OB) that temporarily stores output data to other PEs. 151 is a wiring for transmitting input data from other PEs, and 161 is a wiring for transmitting output data to other PEs, both of which are connected to the connection network 400 that interconnects the PEs.

170 and 180 are REG130. REG(W)1
A bus 190 is a bus for transmitting input data from 40 or IB150 to ALUIIO, and is a bus for transmitting the operation result of AL'UilO to REG(W) 140 or ○B1601\. 210 is a data bus for exchanging data between the element processor 100 and the host computer 200. Other control signals for controlling the PE 105 are omitted.

Each component of the PE 105 will be explained below.

ALUI l l performs, for example, arithmetic and logical operations using data on bus 170 or 180 and data on bus 170 or data bus 210 as input. The output is also the working register 140.

is output to shifter 120. Shifter 120 is ALUI
11 or the input data from the bus 180 is outputted to the bus 190 in a right-shifted, left-shifted, or unchanged form.

Data stored in general purpose register 130 can be read onto bus 170 or 180. General purpose register 13
Writing data to 0 is performed from bus 190. Also,
General-purpose register 130 can read data from and write data to data bus 210 . The input cover sofa IB 150 stores data sent from other PEs. Further, data can be exchanged with the data bus 210. In the case of a number of n-bit wires for inputting data from the OB of another PE to the IB 150, the IB 150 has n-bit buffers corresponding to the number of wires. l
The data stored in B150 is sent to AL through bus 170.
You can input to Ull. Alternatively, the data can be directly output to other PEs without going through an arithmetic processing unit such as the ALU 11. The output buffer 160 stores output data to other PEs. Furthermore, data can be exchanged with the data bus 210. If there are L number of n-bit wires for data output from 0B160 to rB of other PE, ○B160
has L number of n-bit buffers arranged on L lines, and data can also be stored in the ○B160 from the bus 190.

FIG. 4 is a diagram for explaining the procedure for testing PEs in the parallel processors shown in FIGS. 1 to 3. However, in FIG. 4, switching elements 300 are used to connect PEs. A function for switching connection/disconnection between the wiring 400 and each PE is added to the parallel processor 400. Therefore, by having spare PEs in the system and replacing failed PEs with spare PEs according to test results, it is possible to improve yield.

In FIG. 4, 300-1 and 300-2 are switching elements 31 for switching the connection/non-connection between the wiring 400 coupling between the PEs and the PEs 100-1 and 100-2.
5-1, 325-1゜335-1 is switching element 3
Signal for controlling 00-1, 315-2, 325-
2,335-2 is a signal for controlling the switching element 300-2, and 50-1 to 50-6 are fuse cells that generate control signals for the switching elements.

The arithmetic processing function of the PE can be tested, for example, by the following ① to ②.

(2) Write test data simultaneously from the host computer 200 to the IBs 150 in all PEs via the data bus 210.

■ The test data in 1B150 is processed as ALU input data, and the result is sent to 0B160 in the same PE.
Output to. Shifter if necessary.

Use a working register.

(2) Read and check the calculation results stored in 0B160 in each PE to the outside of the LSI via the data bus.

Here, in the above-described test of the arithmetic processing function of the PEs, wiring interconnecting the PEs is not used. However, the above P
In the test of E's arithmetic processing function.

General-purpose registers can also be used in place of 1B150 and 0B160.

FIG. 5 shows a switching element 300-l shown in FIG.
(This is an h-example. The switching element 300-2 also has the same configuration.

In FIG. 5, 310, 320, and 330 are transmission gates. transmission gate 31
0, 311 is composed of NMOS, and 312 is composed of P to IO8. Transmission gate 310 is controlled by control signal 315. That is, NMOS3
When a signal is applied to 315 so that the control signal on the 11 side becomes high level and the control signal on the PMOS 312 side becomes low level, the transmission gate 310 is turned on. Conversely, the control signal on the 8MOs311 side is the low lever\
When a signal is applied to the transmission gate 315 so that the control signal on the PMOS 312 side becomes a high level, the transmission gate 310 is turned off.

Similarly, transmission gates 320 and 330 are controlled by control signals 325 and 335, respectively.

FIG. 16 shows an example of the relationship between the control signals 315, 325° 335 and the states of the switching elements.

FIG. 5 shows an example in which a switching element is configured using a transmission gate. The switching element can also be configured with a logic circuit.

FIG. 6 is an example of a fuse cell 50-1 for generating control signals for switching elements 300-4 and 300-2. Fuse cells 50-2 to 50-6 also have the same configuration.

FIG. 6 shows a laser cuttable fuse 500° transistor 501. Resistance 502. It is composed of a transistor 503. Fuse 500 is in a connected state during manufacturing. A pulse is applied in an analog manner when the power is turned on so that the gate of the transistor 503 is at a high level in the initial state.

Transistor 503 is turned on. by this,
The potential of the node 504 becomes low level, and the output 505 becomes low level.

On the other hand, consider a case where the fuse 500 is cut by a laser. At this time, the transistor 501 is turned on, and the source of the transistor 501 becomes low level.

As a result, transistor 503 is turned off. Output 5
05 is at a high level. Therefore, by connecting the 5 output 505 to, for example, 315 shown in FIG. S, it is possible to control on/off of the transmission gate 310. Similarly.

By using the fuse cell, it is possible to control whether the transmission gates 320, 330 are turned on or off.

The on/off state of each transmission gate, that is, the logical connection relationship of each switching element, is determined by the test results of each PE after manufacturing. FIG. 4 shows an example in which a transmission gate is controlled by including the fuse cell as a part of an LSI.

An example of using a fuse cell to control a transmission gate has been described above. The control signal for the transmission gate can also be given from an external part of the LSI constituting the parallel processor, such as a host computer.

FIG. 7 shows wiring lines 400-1 to 400- interconnecting PEs in the parallel processors shown in FIGS. 1 to 3.
FIG. 4 is a diagram for explaining the procedure for testing a stuck-at fault of 0 or 1. FIG. 7 shows a case where each PE is connected in a ring shape. Here, the stuck-at-at-0 (or 1) fault is a fault in which the signal value does not depend on the input and is fixed at 0 (or 1) due to a disconnection, short circuit, or the like. However, in the parallel processor 600 shown in FIG.
It has spare wiring 401-1 to 401-4.

Furthermore, the switching elements 301-1 to 301-4 have a function of switching a faulty wiring to a spare wiring.6 Therefore, it is possible to improve the yield.

For example, when testing for a 1(o) stuck-at fault in wiring that interconnects PEs, the test can be performed using the following steps (1) to (2).

■ Via the data bus 210, all '0' (all '1') is sent from the host computer 2oo to the OBs in all PEs.
Write. Test data is written to OBs in all PEs in parallel.

, 2 Test data written to OB in each PE.

It is transmitted to the IB in the PE located on the right side on the ring connection network.

Test data is output from each PE OB in parallel.

I2- The data transferred to the IB in each PE is read out sequentially to the outside of the LSI via the data bus.

If it is other than all 'O' (all '1').

1 (0) in the wiring used for data transfer from OB to IB
A stuck-at fault will exist.

Here, in the above-mentioned test for a stuck-at-0 or 1 fault in the wiring interconnecting the PEs, the PE sections (eg, ALU, internal buses 170, 180, 190, etc.) other than IB and OB are not used.

As described above, for the case where PEs are connected in a ring shape, P
We have shown a method to test for failures in the wiring that connects E.

The above wiring testing method is also effective when the wiring connecting PEs is in a shape other than a ring.

For example, it can be applied to torus, two-dimensional lattice coupling, hypercube, etc.

FIG. 8 illustrates a torus network of the type adopted in ILLIAC-IV in the case where the number of PEs is 4 rows x 4 columns. In a torus network of the type used in I LL I AC-IV.

The wiring 400 that connects all the PEs in the horizontal direction is a ring-shaped wiring. PEs belonging to the same column (4 in this case)
The wirings 401, 402, 403, and 404 that connect the two are also ring-shaped wirings. Therefore, after writing test data to all PEs in parallel, the ring-shaped wiring 4
The above test method can be applied by considering 00 to 404 separately. The ring-shaped wirings 401 to 404 can be tested in parallel.

FIG. 9 illustrates a two-dimensional lattice coupling network employed in the DAP in a case where the number of PEs is 4 rows by 4 columns.

Wirings 401, 402, 403° 404 that connect PEs (four in this case) belonging to the same column, and wirings 405, 4 that connect PEs (four in this case) belonging to the same row.
06, 407° and 408 are part of the ring-shaped wiring, respectively.

Therefore, after writing test data to all PEs in parallel, the test method 5 above can be applied by considering the PEs separately. Wiring lines 4.01-404 can be tested in parallel.

Wiring lines 405-408 can be tested in parallel.

Figure 10 shows CM (Connection Mach)
The hypercube connection network adopted in
The diagram shows a case where the number of PEs is 8.

An N-dimensional hypercube has = 2N nodes (PEs), and each PE has a number (address) from O to -1.
is given as an N-bit binary number. PEC with Hamming distance 1
In Fig. 12, there is a route that sequentially selects all PEs (PEs whose address numbers differ by 1 bit) and enriches all PEs, that is, a ring-shaped route.5 In Fig. 12, for example (OOO)-
>(001)->(011)-> (OL O)-
>(110)->(111)->(101)->
There is a ring-shaped path from (100) to (000). The untraversed wiring may be selected from another ring-shaped route. Therefore.

After writing test data to all PEs in parallel.

The above test method can be applied.

FIG. 11 shows the switching element 301-1 shown in FIG.
This is an example. Switching elements 301-2 to 301-
4 also has the same configuration.

In Figure 11, 310-1, 320-4゜330-
1, 310-2, 320-2, 330-2 are transmission gates. In the transmission gate 310-1.

311-1 is composed of NMOS, and 312-1 is composed of PMO3. Transmission gate 310-1 is controlled by control signal 315-1. That is, NMO5
311-1 side control signal is high level and PMOS31
315- so that the control signal on the 2-1 side becomes low level.
1, transmission gate 310
-1 is in the on state. Conversely, when a signal is given to 315-1 so that the control signal on the NMO 5311-1 side is at a low level and the control signal on the PMO 5312-1 side is at a high level, the transmission gate 310-1 is turned off. Similarly, transmission game h320-1
,330-1,310-2゜320 2.33Q 2
are the control signals 32E)-1, 335-1, 31, respectively.
5-2, 325-2, 335-2.

Control signal 315-1, 325-1, 335-1゜315
-2, 325-2, 335-2 can be generated by using the fuse cell shown in FIG. 6 on an LSI, as in the case of the switching element shown in FIG. Further, it can also be provided from an external part of the LSI constituting the parallel processor, such as a host computer.

FIG. 11 shows an example in which a switching element is configured using a transmission gate. The switching element can also be configured with a logic circuit.

In the parallel processor shown in FIG.
and P E 100-1 when 401-2 is in failure. P.E.
100-2'' and PE100-3 are shown in FIG. 12. The thick solid line indicates the electrically connected part.
By using the switching elements 301-1 to 301-3 shown in the figure, it is possible to connect between PEs while avoiding the faulty wirings 400-1 and 400-2. However, in FIG. 12, the description of the control signals for the switching elements 301-1 to 301-3 is omitted.

FIG. 13 is a block diagram showing the connection relationship between the data bus 210 and each PE in a parallel machine having spare PEs.

In Figure 13, 100-1 to 100-5 are PE, 2
00 is a host computer, 210 is a data bus D[0-31 for exchanging data between the PE and the host computer.
]. In FIG. 13, PE 100-5 is assumed to be a spare PE. In FIG. 13, data is sent and received to and from each PE in units of 8 bits. That is, among the 32 bits D[0-31], D[0-7] are PE100-1. D
[8-151 is PE100-2.0 [16-23]
is PE 100-3, D [24-31 is PE 100
Connect to -4. However, the spare PE100-5 has D.
[All 32 bits from 0 to 31 can be connected.

This is to enable PE 100-5 to be used as a backup for all PEs 100-1 to 100-4.

This embodiment differs from boundary scan.

For test 1-, there is no need to add a shift register or a scan path. FIG. 17 shows a comparison between the test method according to this embodiment and boundary scan.

〔Effect of the invention〕

As described above, according to one aspect of the present invention, test data input can be executed in parallel to all element processors. Therefore, the time for inputting test data does not depend on the number of element processors, and the invention is also applicable to testing parallel processors with spare PEs or wiring.

[Brief explanation of the drawing]

FIG. 1 shows one embodiment of a parallel processor according to the present invention;
The figure shows an example of a circuit that controls data input/output between the parallel processor shown in FIG. 1 and a data bus. Fig. 3 is an example of an element processor, Fig. 4 is an example showing a test method for an element processor, Figs. 5 and 11 are examples of switching elements, and Fig. 6 is an example of a fuse cell that generates a control signal for the switching element. , Figures 7 to 10 are an example of a wiring test method, Figure 12 is an example of replacing a faulty wiring, Figure 13 is a diagram showing the connection relationship between element processors and data buses, and Figure 14 is a conventional example. It is. FIG. 15 is a diagram showing truth values regarding data input/output control in the second (!l). FIG. 16 is a diagram showing the relationship between various states of the switching elements in FIG. 5 and control signals. 17 is a diagram showing a comparison between an embodiment of the present invention and a conventional boundary scan. 100... Element processor, 150... Input buffer, 160... Output buffer, 210... ... Data bus, 300... Switching element, 400... Element process to) Fig. 6gρ Fuji 7 Fig. 6 Do Fig'￥ q Fig. 10 Heron 11 Fig. VJlz Fig. % t3 Fig. % /4 11] % t5 Fig. 76

Claims (1)

[Claims] 1. Writing the same test data from outside the parallel processor to data reception buffers in all element processors constituting the parallel processor simultaneously, and calculating the test data written in the data reception buffers. Arithmetic processing is performed on the input data of the processing unit, processing for outputting the result of the calculation to the data transmission buffer in the same element processor is performed in parallel to all element processors, and the processing is performed in parallel to the data transmission buffer in the element processor. A method of reading stored calculation results outside of a parallel processor and testing the element processors. 2. From outside the parallel processor, all '0's (or all '1's) are simultaneously written to the data transmission buffers in all element processors that make up the parallel processor, and the test data written to the data transmission buffers is simultaneously to the data reception buffers of other processors, read the test data transferred to the data reception buffers in each element processor to the outside of the parallel processor, and test the wiring connecting the element processors. Method. 3. A parallel processor in which a plurality of processors each having an arithmetic means and a storage means for storing input data and arithmetic results of the arithmetic means are interconnected, and the arithmetic operations are controlled based on signals given from outside the parallel processor. In the parallel processor, each processor has a buffer for transmitting or receiving data with all other mutually coupled processors, and each of the buffers for transmitting or receiving data is connected to the parallel processor. A parallel processor characterized by having means for writing and reading data from outside the processor. 4. The parallel processor according to claim 3, wherein said storage means for storing input data or calculation results of said calculation means has means for writing and reading data from outside said parallel processor. 5. The parallel processor has a spare processor or a spare wiring, and has means for determining connection/disconnection between each processor and the wiring interconnecting the processors according to test results after manufacturing. 5. The parallel processor according to claim 3 or 4. 6. Claim 5, wherein in the parallel processor having a spare processor, a part or all bits of the data bus can be connected to the spare processor.
Parallel processors as described in section.