JPH04162161A - storage controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a storage unit comprising an error correction code bit and a data pin, an n-bit error detection mechanism, and an m-bit error correction mechanism (n>m). The present invention relates to a storage control device comprised of a control unit, and particularly relates to processing of soft error failures in memory.

[Prior art] When a correctable error of m bits or less is detected, it is possible to continue processing by correcting the data, but it is not possible to correct the data in memory that has caused an error of m or less bits. If left as is, further errors will occur, increasing the probability of errors exceeding the correctable m bits, and reducing reliability. Therefore, when a correctable error of m bits or less is detected, the error is corrected and corrected data is rewritten.

Conventionally, at this time, the corrected data was rewritten immediately after waiting for an access request to the storage section. for example,
As described in Japanese Patent Laid-Open No. 57-162186, when a correctable 1-bit error occurs, rewriting the corrected data is given priority over a request to access the storage unit, and the corrected data is immediately written to the address from which it was read. there was.

[Problem to be solved by the invention] In the conventional method, when a correctable error of m bits or less occurs, the access request to the storage unit is forced to wait and the access processing to the storage unit is temporarily interrupted. Since the corrected data is then rewritten, there is a problem in that access processing to the storage section is awaited, resulting in overhead.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage control device that eliminates the overhead caused by interruption of access processing to a storage unit as described above.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, when it is detected that the data read from the storage unit has an error of m bits or less, the detected error is retained. an address register for holding a read address, a data register for holding error-corrected data, and an access detection means for detecting that there is no access to the storage section, and when the holding means is set, When the access detection means detects that there is no access request to the storage section, the corrected data held in the data register is rewritten into the storage section.

Furthermore, by providing two detection means, two address registers, and two data registers, two detection means, two address registers, and two data registers are provided, so that two detection means, two address registers, and two data registers are provided.
When a correctable error of m bits or less occurs, at least one piece of corrected data is rewritten in priority to normal access, and the corrected data is also rewritten in such a case. I made sure that I wouldn't be disappointed.

[Operation] In the present invention, when a correctable error of 1m bits or less is detected when reading data from the storage unit, the occurrence of an error is stored in the storage means, and the error is corrected when there is no request to access the storage unit. Since the data is rewritten, no overhead is generated by rewriting the corrected data.

In addition, by having two addresses each for storing the corrected data, a register for holding the corrected data, and a storage means for holding the fact that a correctable error has occurred, the data can be rewritten before the first rewriting of the corrected data is completed. When a second correctable error occurs, at least one piece of corrected data is immediately rewritten, so that no correction data is omitted.

[Example 1 The present invention will be explained in detail below.

FIG. 1 shows a first embodiment of the invention.

In FIG. 1, 12 is a storage unit in which data and error correction codes are stored; 5 is a rewrite address register that holds a memory address 1 to which correction data is written;
A correction data register 6 holds read data 17 corrected by the ECC correction circuit 16. 7.8
are selectors, and selector 7 normally selects address 1, and selects the output of rewrite address register 5 when rewrite request signal 10 is generated. The selector 8 normally selects the write data 2, and selects the output of the rewrite data register 6 when the rewrite request signal 10 is generated. 16 is F
This is a CC correction circuit that checks the read data and detects 1-bit error or 2-bit error.
When a bit error is detected, the error-corrected data is output. Reference numeral 19 denotes an error flip-flop, which stores the ECCl bit error detection signal 18 to hold that a 1-bit error has occurred. 15 is an access detection circuit, which receives access request 4 and correction request 2.
Generates 10 rewrite requests from 0 and outputs them.

FIG. 2 shows one of the specific circuit configurations of the access detection circuit 15.
This is an example. 23 is an inverter which inputs the fact that there is no access request 4 to the AND gate 24 by inverting it. 24 is an AND gate, which outputs the rewrite request 10 when the correction request 20 is issued and the access request 4 is not issued.

This embodiment is characterized in that an access detection circuit 15 is provided to rewrite data corrected by the ECC correction circuit 16 into the memory 12 when there is no access request.

When writing data to memory 12, access request 4
Input address 1, memory write 3, and write data 2. Write data 2 is output by selector 8 to memory 12 as memory write data 9, and address 1 is output by selector 7 to memory 12 as memory address 11.

An AND gate 21 detects that there is an access request 4 and a memory write 3, outputs a write enable 14 to the memory 12 through an OR gate 22, and writes memory write data to the address indicated by the memory address 11.

When reading data from the memory 12, access request 4 and address 1 are input. The rewriting address register 5 holds address 1 in case of rewriting. Selector 7 sets address 1 to memory address 1
It is output to the memory 12 as 1. Memory read data 13 read by outputting memory address 11 is checked by ECC correction circuit 16, and if no ECCl bit error 18 occurs, the access process ends. On the other hand, when an ECCl bit error 18 occurs, the corrected data is output as read data 17, the correction data register 6 holds the read data 17, and the error flip-flop 19 is set.

The rewrite address register 5 and the correction data register 6 are held while the error flip-flop 19 is set. The access detection circuit 15 uses the inverter 23 and the AND gate 24 to detect that the error flip-flop 19 is set and there is no access request 4, and switches the selector 7 and the selector 8 to transfer the contents of the rewrite address register to the memory. The contents of the correction data register are output to the memory write data 9, the rewrite request 10 is output as the write enable 14 through the OR 22, and the corrected data is written to the memory 12. Further, after the rewriting is completed, the error flip-flop 19 is reset. Furthermore, 33-2
The human comparator and the AND gate 34 indicate that if a memory write is performed by access request 4, memory write 3, and address 1 to the address to be rewritten before the rewriting is completed, a correction that matches address 1 is made. Data is not rewritten and is used to reset error flip-flops.

In the first embodiment described above, since the rewriting of the corrected data is performed after detecting that there is no memory access request, the overhead due to rewriting can be completely eliminated. However, before the writing of the corrected data is completed, the next 1-bit error occurs, and when writing of the corrected data occurs, it becomes impossible to rewrite one of the two corrected data. Although this situation occurs infrequently, it can be a problem when extremely high reliability is required. In order to avoid this, it is necessary to have two holding means for holding the detected data, two address registers for holding the read address, and two data registers for holding the corrected data. When a rewrite occurs due to a 1-bit error, a holding means is provided to hold the detection of a second rewrite due to a 1-bit error that occurred later, an address register to hold the read address, and a corrected data. It is sufficient to save the data to the data register and force the first rewrite process.

FIG. 3 shows a second embodiment of the present invention, which realizes the above functions. 5-a is a first rewrite address register that holds a memory address 11 to which corrected data is to be written.

5-b is memory address 11 where correction data is written.
This is a second rewrite address register that holds . 6-a is a first correction data register that holds read data 17 corrected by the FCC correction circuit 16;
A second correction data register 6-b holds read data 17 corrected by the FCC correction circuit 16. 27 is a selector for selecting address 1 in normal times and the first rewriting address register 5-a or second rewriting address register 5-b in rewriting according to the selection signal 25; It is a selector that sometimes switches the write data 2 to the first rewrite data register 6-a or the second rewrite data register 6-b when there is a switching address 25. 19-a is a first error flip-flop which stores the occurrence of a 1-bit error by storing the 1-bit error detection signal 18; 19-b indicates the occurrence of a 1-bit error by storing the 1-bit error detection signal 18; This is a second error flip-flop that holds by storing . 32 is a second access detection circuit that outputs a rewrite request 10, a switching address 25, and an access wait instruction 27 from the access request 4, the first correction request 20-a, and the second correction request 20-b; FIG. 4 shows an example of a circuit configuration of the second access detection circuit 32. An inverter 23 inputs the fact that there is no access request 4 to the AND gate 24 by inverting it.
4 is the first correction request 20-a or the second correction request 2
AND gate that outputs rewrite request 10 when 0-b is issued and access request 4 is not issued, 28 is first correction request 2-0-a2 or second correction request 20
This is an OR gate that outputs -b to the AND gate 24.

29, when there is no access request and there is a first surface correction request 20-a, the first rewrite address register 5-a and the first
The AND gate 3o outputs the switching address 25 so that the correction data register 6-a is selected, and the AND gate 3o outputs the switching address 25 so that the correction data register 6-a is selected. This is an AND gate that outputs an address and data selection signal 25 so that the second correction data register 6-b is selected. 31 is the first correction request 20-a, the second correction request 2o-b and 1
This is a Nant gate that outputs an access wait instruction 27 when a bit error detection signal 18 is present.

The second embodiment will be explained below with reference to FIGS. 3 and 4.

When reading data from memory 12, access request 4 and address l are input. The rewriting address register 5-a holds address 1 in case of rewriting. Selector 27 outputs address 1 to memory 12 as memory address 11. The memory read data 13 read by outputting the memory address 11 is checked by the ECC correction circuit 16, and if no error is detected, the access process ends.

On the other hand, when the 1-bit error detection signal 18 is detected, E
The CC correction circuit 16 corrects the error and corrects the read data 17.
The first correction data register 6-a holds the corrected data 17, and the first error flip-flop 19-a is set.

In the second access detection circuit 32, the first error flip-flop 19-a is set and the inverter 23 and the AND gate 24 detect that there is no access request 4.
, the selector 27 and the selector 28 are switched to output the contents of the first rewrite address register 5-a to the memory address 11, and the contents of the first correction data register 6-a are output to the memory write data 9. The corrected data is written to the memory 12 by outputting the rewrite request 10 as a write enable 14 through the OR gate 22. Furthermore, after the rewriting is completed, the first error flip-flop 19 is reset. On the other hand, when reading data from the memory 12 before the corrected data is rewritten, access request 4 and address 1 are input. At this time, if the correction data held in the first correction data register 6-a has not been rewritten yet, address 1 is retained in case there is rewriting in the rewriting address register 5-b. Then, the selector 27 outputs address 1 to the memory 12 as memory address 11. The memory read data 13 read by outputting the memory address 11 is checked by the ECC correction circuit 16, and if the 1-bit error detection signal 18 is not detected, the access process ends.

On the other hand, if the 1-bit factory detection signal 18 is detected,
The corrected data is output to the read data 17, and the second rewrite data register 6-already read data 17 is output.
is held, and the second error flip-flop 19-b is set.

In the second access detection circuit 32, the AND gate 31 detects the first correction request 20-a and the second correction request 20-b.
It detects that both are output, outputs an access wait instruction 27, and temporarily interrupts the access request 4. Next, the inverter 23 and the ant gate 24 detect that the first error flip-flop 19-a is set and there is no access request 4, and the selector 27 and the selector 2
8 to output the contents of the first rewrite address register to memory address 11, output the contents of the first correction data register to memory write data 9, and write rewrite request 10 through OR gate 22. 14, and write the corrected data into the memory 12.

Furthermore, after the rewriting is completed, the first error flip-flop 19-a is reset. This allows and gate 3
1 is no longer output from the access weight 27, and the input of the access request 4 is resumed.

In addition, the second access detection circuit 32 detects that the second error flip-flop 19-b is set and that there is no access request 4 through the inverter 23 and the AND gate 2.
4, the selector 27 and the selector 28 are switched to output the contents of the second rewrite address register 5-a to the memory address 11, and the contents of the second correction data register 6-a are converted into memory write data. 9, rewrite request 10 is output as write enable 14 through OR gate 22, and the corrected data is sent to memory 12.
write to. Further, after the rewriting is completed, the first error flip-flop 19-b is set.

Note that the three-person comparator 35 and the AND gate 36 indicate that if memory writing is performed by access request 4, memory write 3, and address 1 to the address to be rewritten before rewriting is completed, the address The corrected data that matches 1 is not rewritten,
Used to reset error flip-flops.

[Effect of the invention 1] In the present invention, a rewrite request for corrected data is held in an error flip-flop, and rewriting is performed by detecting when there is no access request, so there is no need to wait for an access request as in the conventional case. This eliminates the overhead of rewriting.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a storage control device according to a first embodiment of the present invention, FIG. 2 is a circuit block diagram showing an example of the access detection circuit 15 in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing an example of the second access detection circuit 32 in FIG. 3. FIG. Explanation of symbols 5... Address register for rewriting, 6... Data register for rewriting, 7... Access request, 10
... Rewrite request, 15... First access detection circuit, 19... Error flip-flop, 32... Second access detection circuit, 12... Memory, 16...
ECC correction circuit

Claims (1)

[Claims] 1. An error detection and correction mechanism (n
> m), when it is detected that the data read from the storage section includes a correctable error of m bits or less, a holding means for holding the detection, and a read address of the data. an address register that holds an error in the data, a data register that holds corrected data that corrects an error in the data, and an access detection means that detects that there is no request for access to the storage unit, and the holding means is set, And when the access detection means detects that there is no access request to the storage unit, after rewriting the correction data held in the data register to the address indicated by the address register of the storage unit,
A storage control device characterized in that the holding means is cleared. 2. An error detection and correction mechanism that controls the storage unit in which information consisting of error correction code bits and data bits is stored, and can detect n-bit errors and correct m-bit errors.
n>m), when it is detected that the data read from the storage unit has a correctable error of m bits or less, the detection is held.
two address registers that hold read addresses, two data registers that correspond to each of the address registers and hold correction data that corrects errors in the data, and an access request to the storage unit. If only one of the two holding means is set, when the access detection means detects that there is no request to access the storage unit. , after rewriting the corrected data held in the data register to the storage unit, clears the corresponding holding means, and if both holding means are set, takes priority over the access request. A storage control device characterized in that, after writing the correction data held in at least one of the data registers into the storage section, the corresponding holding means is cleared.