JPH04171550A - Cache memory - Google Patents

Abstract

PURPOSE:To avoid the degrading of a cache memory due to an intermittent trouble by deciding no trouble of the cache memory unless two parity errors occur within a fixed time at the time of index of the cache memory and then rewriting the erroneous data into the normal data. CONSTITUTION:When a trouble occurs in an address array 20 or a data array 30 and the output of a parity check circuit 50 is set at logic '1', a trouble deciding circuit 60 outputs logic '1' and '2' to the signal lines 601 and 602 respectively and store the parity errors at one time. A detector circuit 40 outputs logic '0' to a signal line 401 regardless of the result of address comparison. A timer 70 starts counting for a fixed time when the logic value of a signal line 501 changes to '1'. If the parity errors are not continuously produced within a fixed time, the parity error stored in the circuit 60 is reset. Thus it is possible to prevent the deterioration of the processor performance caused by an intermittent trouble.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a cache memory.

[Conventional technology]

When conventional cache memory detects a parity error in the read data during reading, it interrupts processor processing, clears the contents of the cache memory, retries the instruction, and degrades the cache when a parity error is detected again. .

[Problem to be solved by the invention]

The conventional cache memory described above is resistant to intermittent failures.
Since the contents of the cache memory are cleared and the second intermittent failure causes the cache memory to be degraded, there is a problem in that the performance of the processor deteriorates.

[Means to solve the problem]

The cache memory of the present invention includes a data array that stores a copy of data in the main memory, an address array that associates the contents of the data array with the contents of the main memory, and checks read data of the data array and the address array. a parity check circuit that determines a failure of the address array or the data array from the output of the parity check circuit and internally stores that a parity error has occurred; a timer that counts a certain period of time and resets the memory that a parity error has occurred stored in the failure determination circuit; and a timer that checks the contents of the address array when accessing the data array to determine if there is a hit in the read data. and a detection circuit for making a determination.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Address register 10 holds memory access addresses.

The address array 20 manages correspondence with the address register 10 by storing part of the memory access address indicated by the signal line 102 in the address center.

Data array 30 is indexed at the same time that the address value of address array 20 is determined by address register 10, and the read data is sent out on signal line 301. The read data on the signal l1301 is sent to the detection circuit 4.
Signal from 0! ! It is valid when the output on 401 is logic "1". Note that when the logic value on the signal line 401 is [1], a signal hit occurs. The parity check circuit 50 performs a parity check on the read data of the address array 20 and the data array 30, and if there is a parity error, the ζf logic is detected. A value “1” is output onto the signal line 501.

The failure determination circuit 60 internally stores that a parity error has occurred when the output of the parity check circuit 50 is "1", that is, when the output of the address array 20 or data array 30 is an R error. Keep it at this time,
If the parity error has already been memorized, signal line 6
02, and if it has not been stored yet, outputs a logic "1" onto signal line 601.

The detection circuit 40 compares the contents of the address section of the address array 20 with the contents of the address register 10, and when the two match and the logical value on the signal line 601 is “0”, a logical “1” is generated.
is output as signal 11401h.

The timer 70 changes the logical value on the signal line 501 from "0" to "
When the signal changes to "1", it starts counting for a certain period of time, and outputs a logic "1" onto the signal line 701 when the certain period of time has elapsed. In response to this, the failure determination circuit 60 resets the memory that a parity error occurred in the past.

Next, the operation related to the present invention will be explained. A memory access address is set in address register 10 and sent to address array 20 . data array 3
The contents of 0 are simultaneously indexed, and the detection circuit 40 performs address match detection. Here, when the output of the parity check circuit 50 is a logic "0" (that is, when the read data of the address array 20 and data array 30 is normal), the failure determination circuit 60 outputs a logic "0" on the signal lines 601 and 602. " is output. The detection circuit 40 compares the contents of the address part of the address array 20 and the contents of the address register 10, and if they match, the logical value on the signal line 601 is "0", and therefore outputs a match output on the signal line 401. Set to "1", that is, the signal line 201 is set to "1".
The above read data becomes valid.

Next, consider the case where a failure occurs in the address array 20 or the data array 30 and the output of the parity check circuit 50 is logic "1".
A logic "1" is output on signal line 602 and a logic "0" is output on signal line 602, and a parity error is stored at the same time. The detection circuit 40 outputs a logic signal on the signal line 401 regardless of the result of address comparison.
0" is output. In other words, it becomes Kiya Soshmis, loads the data corresponding to the memory access address from the main memory, and loads the address array 20. Register in data array 30. The timer 70 starts running I~ for a certain period of time in response to the change in the logic value on the signal line 501 to rl.

Here, if a parity error does not continue to occur within a certain period of time, the parity error stored in the failure determination circuit 60 is reset. If a parity error continues to occur before the parity error is reset, the failure determination circuit 60 outputs a logic "1" on the signal line 602 to notify that the cache memory has been decried.

〔Effect of the invention〕

As explained above, the present invention does not determine that the cache memory is malfunctioning unless two parity errors occur within a certain period of time when indexing the cache memory, and instead rewrites the error data with normal data. This has the effect of avoiding cache memory deterioration due to intermittent accidents.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 10...Address register, 20...
Address array, 30...Data array, 4o
...Detection circuit, 101, 102, 301.40
1,501゜601.602,701...Signal line, 5o...Parity check circuit, 60...
...Failure judgment circuit, 70...Timer. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a data array that stores a copy of data in a main memory, an address array that associates the contents of the data array with the contents of the main memory, and a parity check circuit that checks read data of the data array and the address array; a failure determination circuit that determines a failure of the address array or the data array from the output of the parity check circuit and internally stores that a parity error has occurred; and a failure determination circuit that counts a certain period of time after the parity error occurs. a timer that resets the memory that a parity error has occurred stored in the failure determination circuit; and a detection circuit that examines the contents of the address array when accessing the data array and determines whether there is a hit in the read data. A cache memory characterized by having.