JPH04184953A - Connection method of semiconductor device - Google Patents
Connection method of semiconductor deviceInfo
- Publication number
- JPH04184953A JPH04184953A JP31514590A JP31514590A JPH04184953A JP H04184953 A JPH04184953 A JP H04184953A JP 31514590 A JP31514590 A JP 31514590A JP 31514590 A JP31514590 A JP 31514590A JP H04184953 A JPH04184953 A JP H04184953A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resin
- substrate
- electrode
- paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000011347 resin Substances 0.000 claims abstract description 29
- 229920005989 resin Polymers 0.000 claims abstract description 29
- 230000001681 protective effect Effects 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 6
- 239000011521 glass Substances 0.000 abstract description 6
- 238000007789 sealing Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000011231 conductive filler Substances 0.000 abstract description 2
- 229920001187 thermosetting polymer Polymers 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 11
- 238000007796 conventional method Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 potassium ferricyanide Chemical compound 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の回路基板への電気的、機械的接
続方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for electrically and mechanically connecting a semiconductor device to a circuit board.
従来、半導体装置の回路基板への接続方法は以下のごと
きのものである。従来の方法を第2図を用いて説明する
。第2図はすべて断面図である。Conventionally, methods for connecting a semiconductor device to a circuit board are as follows. The conventional method will be explained using FIG. All of FIG. 2 are cross-sectional views.
まず、第2図(a)に示すように、所定の素子を形成し
た半導体基板1のアルミ電極2が露出するよ゛うに保護
膜乙に開口を形成した後、メツキの共通電極膜として半
導体基板1全面に、AJ、Cr、Cuを積層し、金属膜
4を形成する。First, as shown in FIG. 2(a), an opening is formed in the protective film B so that the aluminum electrode 2 of the semiconductor substrate 1 on which a predetermined element is formed is exposed, and then the semiconductor substrate is opened as a plating common electrode film. 1. A metal film 4 is formed by laminating AJ, Cr, and Cu on the entire surface.
次に第2図(b)に示すように、金属膜4上にフォトレ
ジストをスピンコード法により塗布し、所定のマスクを
用いて露光、および現像処理をおこないアルミ電極2上
に開口部を有するレジスト5を形成する。次に第2図(
C)に示すように、銅メツキ6、金メツキ7をおこない
バンプ21を形成スる。Next, as shown in FIG. 2(b), a photoresist is coated on the metal film 4 by a spin code method, exposed using a predetermined mask, and developed to form an opening on the aluminum electrode 2. A resist 5 is formed. Next, Figure 2 (
As shown in C), copper plating 6 and gold plating 7 are performed to form bumps 21.
最後にレジスト5及び金属膜4の不用部分を除去し、第
2図(d)に示すバンプ21の構造を得る。Finally, unnecessary portions of the resist 5 and metal film 4 are removed to obtain the bump 21 structure shown in FIG. 2(d).
バンプ形成終了後のウェハーは、ダイシングをおこない
、チップ単体にした後、第2図(e)に示すようにバン
プ21表面に導電ペースト8を転写し、ガラス基板9上
の電極パターン10と接続し、加熱することにより導電
ペースト8を硬化させる。After the bump formation has been completed, the wafer is diced into single chips, and then a conductive paste 8 is transferred onto the surface of the bumps 21 and connected to the electrode pattern 10 on the glass substrate 9 as shown in FIG. , the conductive paste 8 is cured by heating.
ここで電極パターン10は酸化インジウムスズである。Here, the electrode pattern 10 is indium tin oxide.
さらに第2図(f)に示すように、半導体基板1とガラ
ス基板9どの間にモールド樹脂11を注入し加熱、硬化
させるという接続方法である。Furthermore, as shown in FIG. 2(f), the connection method involves injecting a molding resin 11 between the semiconductor substrate 1 and the glass substrate 9 and heating and hardening it.
しかしながら、上述した従来の方法では、バンプ形成工
程及びボンディング工程が長く煩雑である。またメツキ
用のレジスト5をスピンコード法により形成する場合、
このレジスト5は一度に数μm程度の厚みしか形成でき
ない。こうしたレジスト5をマスクとして、湿式メツキ
法によりバンプ21を形成する場合、メツキは等方的に
成長するため横方向への広がり□が問題となる。すなわ
ちメツキの不要な横方向への広がりのため、所望の大き
さのバンプを得るためには、バンプ間距離が規制されて
しまい、高密度バンプの形成には不適当である。However, in the conventional method described above, the bump forming process and the bonding process are long and complicated. In addition, when forming the resist 5 for plating by the spin code method,
This resist 5 can only be formed to a thickness of about several μm at a time. When the bumps 21 are formed by a wet plating method using the resist 5 as a mask, the plating grows isotropically, so that lateral spread □ becomes a problem. In other words, due to the unnecessary spread of the plating in the lateral direction, the distance between the bumps is restricted in order to obtain bumps of a desired size, making it unsuitable for forming high-density bumps.
そこでメツキ用のレジスト5をバンプに必要な高さまで
厚く形成することにより、メツキの横方向への広がりを
抑えることができる。しかし、スピンコード法により繰
り返し重ねて塗布する場合、品質の安定性、生産性にお
いて問題がある。Therefore, by forming the resist 5 for plating as thick as the height required for the bump, it is possible to suppress the spread of the plating in the lateral direction. However, when repeatedly applying the coating in layers using the spin code method, there are problems in quality stability and productivity.
この課題を解決するため、本発明の目的は半導体基板と
回路基板上の電極パターン間の簡易で、かつ高密度化が
可能な接続方法を提供することにある。In order to solve this problem, an object of the present invention is to provide a simple method for connecting electrode patterns on a semiconductor substrate and a circuit board, and which can increase the density.
上記目的を達成するため罠、本発明は半導体装置の回路
基板への電気的、機械的接続方法において、半導体基板
上の全面に保護膜を形成し、さらにこの保護膜をエツチ
ングしてアルミ電極上に開口を形成し、さらに全面に金
属膜を形成する工程と、この金属膜をエツチングし、ア
ルミ電極上に金属膜を形成する工程と、全面に樹脂膜を
形成しさらにこの樹脂膜の金属膜上に開口を形成する工
程と、樹脂膜の開口内に導電ペーストを埋め込む工程と
、基板の電極パターンと導電ペーストとをボンディング
する工程とよりなることを特徴とする。In order to achieve the above object, the present invention provides a method for electrically and mechanically connecting a semiconductor device to a circuit board, in which a protective film is formed on the entire surface of the semiconductor substrate, and the protective film is further etched onto an aluminum electrode. A process of forming an opening on the surface and forming a metal film on the entire surface, a process of etching this metal film and forming a metal film on the aluminum electrode, and a process of forming a resin film on the entire surface and then forming a metal film on the resin film. It is characterized by comprising the steps of forming an opening on the resin film, embedding a conductive paste in the opening of the resin film, and bonding the electrode pattern of the substrate and the conductive paste.
以下、本発明による一実施例を第1図(a)〜←)を用
いて工程順に説明する。第1図はすべて断面図である。Hereinafter, one embodiment of the present invention will be explained in order of steps using FIGS. 1(a) to ←). All of FIG. 1 are cross-sectional views.
−
まず、第1図(a)に示すように、所定の素子を形成し
た半導体基板1上のアルミ電極2が露出するように保護
膜3を形成する。保護膜3はSiNをCVD法により厚
さ800nm形成し、さらにポリイミドを厚さ2μm形
成した二層膜である。- First, as shown in FIG. 1(a), a protective film 3 is formed so that the aluminum electrode 2 on the semiconductor substrate 1 on which predetermined elements are formed is exposed. The protective film 3 is a two-layer film formed by forming SiN to a thickness of 800 nm by CVD and further forming polyimide to a thickness of 2 μm.
SiN膜の他に、SiO,、PSGなども保護膜3とし
て可能である。In addition to the SiN film, SiO, PSG, etc. can also be used as the protective film 3.
次に半導体基板1の全面に蒸着法により金属膜4を形成
する。金属膜4の形成はスパッタリング法も可能である
。金属膜4は、Al1μm、Cr3nm、Cu800n
mの積層構造をとる。金属膜4は、上下に形成する導電
材料に対して接着性が良く、なおかつ金属膜材料と導電
材料同志が相互拡散しない上記組合せが望ましい。Next, a metal film 4 is formed on the entire surface of the semiconductor substrate 1 by a vapor deposition method. The metal film 4 can also be formed by sputtering. The metal film 4 is made of Al1μm, Cr3nm, Cu800n
It has a laminated structure of m. It is desirable that the metal film 4 have good adhesion to the conductive materials formed above and below, and the above-mentioned combination is such that the metal film material and the conductive material do not interdiffuse with each other.
次に半導体基板1の全面に7オトレジスト膜(図示せず
)を形成し、露光、現鐵した後、第1図(b)に示すよ
うに不要部分の金属膜4をエツチング液により除去し、
アルミ電極2上に金属膜4を形成する。Cuのエツチン
グ液にはアンモニア系の溶液を用い、Alにはフェリシ
アン化カリウムと水酸化ナトリウムの混合水溶液を用い
る。Crはklをエツチングする際にリフトオフにより
゛除去する。Next, a photoresist film (not shown) is formed on the entire surface of the semiconductor substrate 1, exposed and developed, and unnecessary portions of the metal film 4 are removed using an etching solution as shown in FIG. 1(b).
A metal film 4 is formed on the aluminum electrode 2. An ammonia-based solution is used as the etching solution for Cu, and a mixed aqueous solution of potassium ferricyanide and sodium hydroxide is used for Al. Cr is removed by lift-off when etching kl.
次に第1図(C)に示すように、感光性樹脂であるドラ
イフィルムをラミネート法により25〜40μmの厚さ
で形成し、フォトリソグラフィーによりアルミ電極2上
に開口部を有する樹脂膜12を形成する。樹脂膜12の
開口径は、応力緩和の点などから、金属膜4と一致させ
るか、または金属膜4よりやや小さくすることが望まし
い。また樹脂膜12は、ボンディング後のICチップの
保護を兼ねるため、半導体基板1上の保護膜6との密着
性が良く、耐熱性を有することが必要である。Next, as shown in FIG. 1(C), a dry film of photosensitive resin is formed with a thickness of 25 to 40 μm by a laminating method, and a resin film 12 having openings is formed on the aluminum electrode 2 by photolithography. Form. The opening diameter of the resin film 12 is desirably made to match that of the metal film 4 or to be slightly smaller than the metal film 4 from the viewpoint of stress relaxation. Furthermore, since the resin film 12 also serves to protect the IC chip after bonding, it needs to have good adhesion to the protective film 6 on the semiconductor substrate 1 and have heat resistance.
次に半導体基板1上の開口部に、第1図(d)に示すよ
5に樹脂中に導電フィラーを分散させた、導電ペースト
8をスキージ−法、デイツプ法などによって埋め込む。Next, as shown in FIG. 1(d), a conductive paste 8 in which a conductive filler is dispersed in a resin is embedded in the opening on the semiconductor substrate 1 by a squeegee method, dip method, or the like.
次にウェハー表面に厚さ数μmの保護膜(図示せず)を
形成し、ウェハー状となっている半導体基板1をダイシ
ングにより、所定の大きさのチップ単体に分割した後、
この保護膜を除去する。ここで、ダイシングは樹脂膜1
2の形成後におこない、チップ単体とした後に、導電ペ
ースト8を樹脂膜12の開口内に埋め込んでもよい。Next, a protective film (not shown) with a thickness of several μm is formed on the wafer surface, and the wafer-shaped semiconductor substrate 1 is divided into individual chips of a predetermined size by dicing.
This protective film is removed. Here, dicing is performed using resin film 1.
The conductive paste 8 may be buried in the opening of the resin film 12 after forming the chip 2 and forming a single chip.
次に第1図(e)に示すように、半導体基板1とガラス
基板9どの接続をおこなう。導電ペースト8が埋め込ま
れた部分と、ガラス基板9の電極パターン10の位置合
わせをおこない、熱または光によって導電ペースト8を
硬化させる。従来の方法ではICチップ保護のため、半
導体基板1とガラス基板9との間に第2図+f)に示す
モールド樹脂11を注入し、加熱硬化させていたが、本
発明による接続方法では、樹脂膜12が同様の役割を果
たすため、モールド樹脂の樹脂封止工程を廃止すること
が可能となる。Next, as shown in FIG. 1(e), the semiconductor substrate 1 and the glass substrate 9 are connected. The portion where the conductive paste 8 is embedded is aligned with the electrode pattern 10 of the glass substrate 9, and the conductive paste 8 is cured by heat or light. In the conventional method, in order to protect the IC chip, a molding resin 11 as shown in FIG. Since the film 12 plays a similar role, it becomes possible to eliminate the resin sealing process of the mold resin.
また、従来の方法では、アルミ電極2上にコアとして銅
などの金属を用いていたため、外部応力が直接下地に影
響を与え、さらにメツキ時に生ずる堆積応力の信頼性へ
の影響が問題であった。しかし本発明による接続方法で
は、アルミ電極2上に導電ペースト8を埋め込むことに
より、樹脂による応力の緩和が可能となり、メツキによ
る堆積応力も発生しない。In addition, in the conventional method, since a metal such as copper was used as the core on the aluminum electrode 2, external stress directly affected the underlying layer, and the reliability of the deposited stress generated during plating was a problem. . However, in the connection method according to the present invention, by embedding the conductive paste 8 on the aluminum electrode 2, the stress can be relaxed by the resin, and no deposit stress is generated due to plating.
以上の説明で明らかなように本発明によれば、半導体装
置の回路基板への接続方法において、半導体基板上にド
ライフィルムによる樹脂膜を形成することによって、半
導体基板とガラス基板との間の樹脂封止工程な省略する
ことが可能となる。As is clear from the above description, according to the present invention, in the method of connecting a semiconductor device to a circuit board, by forming a resin film using a dry film on the semiconductor substrate, the resin film between the semiconductor substrate and the glass substrate is bonded. It becomes possible to omit the sealing process.
さらにアルミ電極間距離を任意に変化させ、このアルミ
電極上に導電ペーストを埋め込むことができるため、高
密度実装が可能となる。Furthermore, since the distance between the aluminum electrodes can be changed arbitrarily and the conductive paste can be embedded on the aluminum electrodes, high-density packaging is possible.
第1図(a)〜(e)は本発明の半導体装置の基板への
接続方法を工程順に示す断面図、第2図(a)〜(f)
は従来例における半導体装置の基板への接続方法を工程
順に示す断面図である。
1・・・・・・半導体基板、
2・・・・・・アルミ電極、
3・・・・・・保護膜、
4・・・・・・金属膜、
8・・・・・・導電ペースト、
10・・・・・・電極パターン、
12・・・・・・樹脂膜。
第1図
(C)
第1図
第2図
(b)FIGS. 1(a) to (e) are cross-sectional views showing the method of connecting a semiconductor device to a substrate according to the present invention in order of steps, and FIGS. 2(a) to (f)
1A and 1B are cross-sectional views illustrating a method of connecting a semiconductor device to a substrate in the order of steps in a conventional example. 1... Semiconductor substrate, 2... Aluminum electrode, 3... Protective film, 4... Metal film, 8... Conductive paste, 10... Electrode pattern, 12... Resin film. Figure 1 (C) Figure 1 Figure 2 (b)
Claims (1)
をエッチングしてアルミ電極上に開口を形成し、さらに
全面に金属膜を形成する工程と、該金属膜をエッチング
し、該アルミ電極上に前記金属膜を形成する工程と、全
面に樹脂膜を形成しさらに該樹脂膜の前記金属膜上に開
口を形成する工程と、前記樹脂膜の開口内に導電ペース
トを埋め込む工程と、基板の電極パターンと該導電ペー
ストとをボンディングする工程とを有することを特徴と
する半導体装置の接続方法。A process of forming a protective film on the entire surface of the semiconductor substrate, etching the protective film to form an opening on the aluminum electrode, and further forming a metal film on the entire surface, and etching the metal film and forming an opening on the aluminum electrode. forming the metal film on the substrate; forming a resin film on the entire surface and further forming an opening on the metal film of the resin film; embedding a conductive paste in the opening of the resin film; 1. A method for connecting a semiconductor device, comprising the step of bonding the electrode pattern and the conductive paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31514590A JPH04184953A (en) | 1990-11-20 | 1990-11-20 | Connection method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31514590A JPH04184953A (en) | 1990-11-20 | 1990-11-20 | Connection method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04184953A true JPH04184953A (en) | 1992-07-01 |
Family
ID=18061956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31514590A Pending JPH04184953A (en) | 1990-11-20 | 1990-11-20 | Connection method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04184953A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8174093B2 (en) | 1996-12-02 | 2012-05-08 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
-
1990
- 1990-11-20 JP JP31514590A patent/JPH04184953A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8174093B2 (en) | 1996-12-02 | 2012-05-08 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
| US8283755B2 (en) | 1996-12-02 | 2012-10-09 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
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