JPH0418897A - Selective control output circuit - Google Patents

Abstract

PURPOSE:To ensure connected control output operation by providing an interruption control part which outputs an interrupt signal to a master controller when the operation of a position selection contact based on a one second pulse becomes insignificant. CONSTITUTION:The interruption control part 20 which outputs the interrupt signal In to the master controller 1 when the operation of the position selection contact 15 based on the one second pulse P1 becomes insignificant is provided. Then, in response to the insignificant sides state of the position selection contact 15 based on the one second pulse, the interrupt signal In is outputted to the master controller 1 so that time control in the connected control at a master controller 1 side is abbreviated. Thus, the connected control output operation is ensured, and simultaneously, the processing load of the master controller 1 can be lightened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selection control output circuit used in a remote monitoring and control device, and particularly to a selection control output circuit that can reliably perform a connected control output operation. It is something.

[Prior Art] Generally, switchgear, etc. used in power transmission systems and substation systems are located in multiple remote locations and in dangerous environments, so it is difficult to receive control data from a remote control device, that is, a central control room. centrally managed based on

For this reason, each switchgear in the above system is equipped with a master controller and a selection control output circuit (constant mark decoding output section), and the constant marks encoded in the central control room are taken in via the master controller. After being decoded by the constant mark decoding output unit, the signal is input to the switchgear as a control signal. As a result, the opening/closing device, which is an external device to be controlled, is controlled to open/close in accordance with the sequence specified by the central control room.

FIG. 8 is a block diagram showing a conventional selection control output circuit, as described in, for example, Japanese Utility Model Application Publication No. 1-116801, together with a master controller and a monitored control device.

In the figure, (1) is a master controller into which control data etc. are input from a central control room (not shown), (2) is controlled based on the write pulse WR, address AD and data DT from master controller (1). A constant mark decoding output section that generates signal C, (3) is a constant mark decoding output section (
2) A monitored control bag whose drive is controlled by the control signal C of the shell! It is.

In this case, only one set is shown, but in reality, the master controller (1) and constant mark decoding output unit (2)
A plurality of sets are prepared corresponding to each monitored control device (3). Further, the monitored control device (3) is assumed to be, for example, a switching device such as a power transmission system.

Further, the data DT consists of, for example, 13 bits, and is
, 3-bit control data representing control contents such as ``off,''``stop,'' and ``normal,'' and 5 selected positions (points).
It consists of 5-bit point data representing the selected monitored control device (3) and 5-bit group data representing the group of monitored control devices (3) to be selected. A specific example of the circuit and specifications for receiving and passing the control signal C from the remote control device (central control room) to the monitored control device (3) can be found, for example, in the Japan Incorporated Association published on September 20, 1976. It is specifically described on page 13 of ``Japan Electrical Manufacturers Association Standard JEM 1352 (1976) Interface J of Remote Monitoring and Control Devices'' published by the Electrical Manufacturers Association.

Further, in FIG. 8, the constant mark decoding output section (2) is composed of the following elements (7) to (16).

(7) is a data memory control unit that outputs a write trigger WT based on the write pulse WR. (8) is an address decoder that decomposes the address AD and outputs a significant signal A, and the significant signal A specifies the constant mark decoding output section (2). (9) is a data memory in which data DT is stored in response to a trigger signal T based on a write trigger WT;
0) is an output relay that processes the data in the data memory (9), (11) is a constant mark verification and point decomposition unit that verifies the data via the output relay (10), and (12) is a constant mark verification and point decomposition unit. This is a one second timer driven by the verification signal E from the decomposition unit (11).

(13) is an inverter that inverts the 1-second pulse P1 from the 1-second timer (12) and outputs a prohibition signal K. When the 1-second pulse P1 is significant due to the prohibition signal K, data DT is written (rewritten). prohibited. <14) is 1 second pulse P1
This is a Z relay that outputs a signal B1 for a time limit of 1 second in response to.

(15) is a position selection contact that generates a control signal C, and a contact 2 driven by a one-second signal B1 from a Z relay (14) and a constant mark verification and point resolution unit (1
1) contacts selectively driven by, e.g.
"off" and "stop" are included.

(16) is an AND gate that performs a logical product of the write trigger WT and the inhibit signal and outputs a trigger signal T to the data memory (9).

Next, while referring to the timing chart diagram in Fig. 9,
The operation of the conventional selection control output circuit shown in FIG. 8 will be explained.

First, the master controller (1), in response to data transmitted from the central control room, sends a constant mark decoding output unit (2) to the constant mark decoding output unit (2).
, a write pulse WR, an address AD, and data DT having a predetermined data format are output.

That is, the content of data DT is output as "0 (normal)" to address AD content "OJ", and then address AD is output as "0 (normal)".
For the content "1", data DT is set as "first time", and the first content of the concatenation control output is output.

The constant mark decoding output section (2) is an address decoder (8).
The address AD is decomposed by 0.1.
In either case 2.3, the significant signal A is output to the data memory control section (7).

When the significant signal A is input, the data memory control unit (7) outputs a write trigger WT having a pulse width equivalent to the write pulse WR. At this time, since the 1 second pulse P1 is not significant, it is not output as the prohibition signal and the AND gate (16
) is open, and the write trigger WT is directly input as a trigger signal T to the data memory (9).

That is, the contents of address AD are changed to rQ by trigger signal T.
, write O clear to the data memory (9), set the output relay (10) to "normal", and then,
When address AD is "1", 1 is stored in data memory (9).
Write the control data for the second time.

On the other hand, the data memory (9) is connected via the output relay (10).
) is input to the constant mark verification and point decomposition unit (11), the constant mark verification and point decomposition unit (11) inputs “Group J
, the constant mark verification is performed according to the constant mark code representing "point" and "control content". Then, the control data corresponding to the connection control is decomposed into points from the constant mark code, and if the constant mark test result is "Good J", the test signal E is changed to "
"Good" is output, and the 1-second timer (12) is driven.

As a result, the 1-second timer (12) outputs a 1-second pulse P1 to drive the Z relay 14), and the Z relay (14) outputs a signal B1 for a time limit of 1 second to close the contact Z.

At this time, the timing of the 1-second time limit signal B1 is slightly delayed from the 1-second pulse P1, and the actual operation of contact Z is as follows.
The timing is further delayed than the signal B1 by one second.

In addition, the constant mark verification and point resolution section (11) selectively closes each contact r, "on", "off", "stop", etc., and a predetermined control signal C is generated from the position selection contact (15). be done. In this way, the control signal C generated from each contact in the position selection contact (15) is transmitted to the monitored control device (3).
and controls contacts (not shown) in the monitored control device (3).

On the other hand, the inverter (13) outputs the 1 second pulse P1 (
AND gate (16) due to prohibition signal K indicating “significant)”
Disable. As a result, the write trigger T is no longer input to the data memory (9) as the trigger signal T, and data writing and data rewriting are prohibited.

Therefore, after the first data write, the master controller (1) waits for the timing when the 1-second pulse P1 changes from the significant side to the non-significant side and the prohibition signal K is released, and writes the control data for the second time. Prepare for action.

When writing data for the second time, similarly to the first time, data DT is set to rQ (normal) for address AD "0".
” and then the second address AD of the concatenated control output.
is "2", and the content of the data DT is "second time".

Therefore, the data memory control unit (7) in the constant mark decoding output unit (2) once writes r□clear (normal) to the data memory (9), and then writes the second control data. , based on this data, position selection contact (15
) and outputs a control signal C to the monitored control device (3).

In this case as well, the master controller (1) prepares for the third data write operation by determining the timing when the one-second pulse P1 becomes involuntary after the second data write.

Thereafter, in the same way as the first and second data writes, O clear and control data are written, the position selection contact 15) is driven, and the control signal C is output to the monitored control device (3). do.

In this way, every time the master controller (1) writes data DT regarding connection control to the data memory (9),
Time management is performed so that the next data write operation does not start while the 1-second pulse PI (actually, the 1-second time limit signal Bl) is being output (significant). This is because if the next data is written while the borrowed symbol B1 is being output for one second without time management, the control output operation for the next data will not be performed, resulting in an inactive state.

[Problems to be Solved by the Invention] As described above, the conventional selection control output circuit outputs the next data one second during each data write operation while outputting the signal B1 for one second.
Since the master controller (1) needs to manage the time of the on/off control output so as not to overload, there is a problem that the processing load on the master controller (1) 1 cannot be reduced.

This invention was made to solve the above-mentioned problems, and it not only ensures the connected control output operation, but also simplifies (or eliminates) time management on the master taco/trawler side.
The purpose of this invention is to provide a selection control output circuit that reduces the processing load on the master controller.

[Means for Solving the Problems] A selection control output circuit according to a first aspect of the present invention sends an interrupt signal to a master controller when the operation of a position selection contact based on a one-second pulse becomes involuntary. This is provided with an interrupt control section for outputting.

Further, the selection control output circuit according to the second invention of the present invention includes:
An interrupt control section is provided that outputs an interrupt signal to the master controller when data is illegally written from the master controller during operation of the position selection contact based on a one-second pulse.

Further, the selection control output circuit according to the third aspect of the present invention includes:
A storage means for storing a plurality of data corresponding to the connection control output, an address counter in which the number of times of connection control from the master controller is set, and a storage means for storing a plurality of data corresponding to the connection control output in response to the operation of the position selection contact based on the 1 second pulse. A storage means control section is provided for controlling the address counter, incrementing the address counter, and outputting an interrupt signal to the master controller when the contents of the address counter reach the number of times of connection control.

[Function] In the first aspect of the present invention, an interrupt signal is output to the master controller in response to the involuntary side state of the position selection contact based on a 1-second pulse, and time management in connection control on the master controller side is performed. Simplify.

Further, in the second aspect of the present invention, it is shown that the concatenated control output operation of the latest input data cannot be executed during the concatenated control output operation of the previous data, thereby simplifying time management on the master controller side. At the same time, the write operation of the connection control data is ensured.

Further, in the third aspect of the present invention, the selection control output circuit side stores a plurality of data and continuously executes the connected control output operation, and sends the connected control to the master controller by an interrupt signal. By notifying the end of the output operation and outputting the next data after the end of the connected control output operation, time management on the master controller side is completely unnecessary.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of the first invention of the present invention, in which (1) to (16), WR, AD, DT, A, W
T, T, = P 1. B1 and C are the same as described above.

(20) is an interrupt control unit that generates an interrupt signal IN in response to the prohibition signal C, and when the position selection contact (15) based on the 1-second pulse P1 becomes inactive, the interrupt control unit An interrupt signal IN is output to the terminal. In this case, since the 1-second pulse P1 corresponds to the operation of the position selection contact (15), the inverted signal of the 1-second pulse P1, that is, the inhibit signal K, is input to the interrupt control section (20).

Next, with reference to FIG. 2, the operation of the embodiment of the first invention shown in FIG. 1 will be described. still,
The output operation of the control signal C is the same as described above, so it will not be described here.

While the connected control output operation is being performed based on the data DT, the inverter (13) outputs the prohibition signal K to prohibit data writing, and when the 1-second timer (12) times out, the 1-second pulse P1 becomes unconscious, and gate (1
6) will be opened.

At this time, the interrupt control unit (20) raises the interrupt signal N in response to the state of the prohibition signal indicating the time-up (involuntary side state) of the one-second pulse P1, and the interrupt signal IN. Input to master controller (1).

Therefore, each time the master controller (1) writes each data from the first to third times, it confirms that the signal B1 has become inactive for one second using the interrupt signal IN, and then writes the next control data. It is possible to prepare for an intrusion operation. That is, time management in connection control of the master controller (1) is simplified, and the processing load on the master controller (1> side) is reduced.

In the above embodiment, the interrupt control unit (20) detects the involuntary state of the signal B1 for one second based on the prohibition signal K, but as shown in FIG. Z may be used as a pair of interlocking contacts to directly detect the state of contact Z in the position selection contact (15), where the contact end of one interlocking contact Z is connected to the positive pole of a power source (not shown) or It is sufficient if it is connected to the negative electrode.

In FIG. 3, when the one-second timer (12) times up and the signal B1 turns off for one second, and the contact Z switches from the closed state to the open state, the interrupt control section (20)
It detects a change in the signal state from contact Z connected to the power supply and outputs an interrupt signal IN. In this case, since the interrupt signal IN is generated in response to the actual operation of contact Z, the interrupt signal I
The reliability of N becomes extremely high.

Next, with reference to FIGS. 4 and 5, a description will be given of an embodiment of the second aspect of the present invention in which the write operation of data DT is ensured.

In FIG. 4, the interrupt control unit (20A>) illegally writes data DT from the master controller (1) while the position selection contact (15) is operating, that is, while the 1-second pulse P1 is output (significant). When installed, the master controller (1)
An interrupt signal ■NA is output for the

(21) is an AND gate that takes the logical product of the write trigger WT and the 1-second pulse P1, detects illegal writing by the write trigger WT, and sends the illegal signal Q to the interrupt control unit (20A). Output.

Next, to explain the specific operation, first, if the master controller (1) makes a normal access,
As described above, the unauthorized signal Q and the interrupt signal INA are not output.

On the other hand, if the master controller (1) makes an unauthorized access, an interrupt signal INA is generated based on the unauthorized signal Q, as shown in FIG.

That is, while the 1-second pulse PL (time-limited 1-second signal Bl) is in a significant state and prohibits the data DT write operation, the master controller (1) makes a mistake in time management, etc.
When the next data DT write operation is performed, an AND gate (2
1) outputs a fraudulent signal Q having a pulse width equivalent to the write pulse WR to the interrupt control section (20^). As a result, the interrupt control unit (20^)
) to notify that the current data write operation was an unauthorized access. When the master controller (1) receives the interrupt signal ■NA, it performs the writing operation of the control data DT again.

For example, as shown in FIG. 5, when the second data write access is performed by the write pulse WR during the first data-based connected control output operation and when the one-second pulse P1 is significant, Since it is known from the interrupt signal INA that the current access was invalid, the 5th master controller <1) performs a retry operation to write the second data DT.

At this time, since the output sushi-(10) does not output the data due to the previous unauthorized access, the one-second pulse P1 is not output as shown by the broken line, and the unauthorized signal Q is not output. Therefore, the interrupt signal INA is not output, the second data DT write operation by the retry operation becomes valid, and the concatenation control output operation is performed normally.

In this way, the interrupt signal INA indicates that the concatenated control output operation of the latest data cannot be executed during the concatenated control output operation based on the previous data, thereby ensuring the write operation of control data on the master controller (1) side. . As a result, the master controller (1) can perform a retry operation when it detects unauthorized access, and can reliably execute a desired connection control output operation without particularly strict time management.

In the above embodiment, only the interrupt signal INA indicating unauthorized write access is generated from the interrupt control unit (20A), but as in the embodiment shown in FIG. ) may also be used in combination with an interrupt control unit (20) that generates an interrupt signal IN indicating the end of the connected control output operation based on the above. In this case, the possibility of unauthorized write access is reduced and reliability is improved.

Next, referring to FIGS. 6 and 7, a description will be given of an embodiment of the third aspect of the present invention that completely eliminates the need for time management on the master controller side.

In FIG. 6, (27) is a RAMIIIj section corresponding to the aforementioned data memory control section (7>), and (29) is a RAM corresponding to the data memory (9).

(22) is an address counter for reading RAM (29) during internal access processing, and the number of times of connection control is set based on data DT from the master controller (1). When the number of inputs of the count-up signal reaches the number of times of connection control, a carry signal M is outputted to the RAM III w section (27N:1m).

(23) is the count up signal and the address counter (
There is an output gate which takes a logical product with the contents of the counter (22), and when the count up signal is at rH level, it is activated and outputs the contents of the counter (22).

(24) is a RAM address selector that accesses RAM (29), and the address AD from the master controller (1) and the contents of the AT counter (22) via the output game 1-(23). and the RAM control unit (27
) is switched in response to the RAM switching signal RC from R.
Write pulse w as address for A M (29)
Output along with p.

The RAM switching signal RC indicates whether the access to the RAM (29) is an external access based on the address AD from the master controller (1) side or an address counter (29).
2) is switched between internal accesses based on addresses from 2). Further, the write pulse WP is generated based on the write trigger WT, and is output under control by the RAM switching signal RC.

RAM (29) stores a plurality of data DT corresponding to the number of times of connection control, and the contents of the address are [OJ
6RAM II outputs data as rQ when .
The Iw section (27) has a significant signal A, a write pulse WR, 1
In response to the second pulse P1 and the carry signal M, the RAM
(29) and also controls the atto counter (22).
) is incremented, and when all connected control output operations related to the data DT stored in the RAM (29) are completed, an interrupt signal I is sent to the master controller (1).
Outputs N.

Next, to explain the specific operation, the data DT for the connected control output operation is input to the interrupt signal IN as shown in FIG.
, is output continuously when it is significant.

That is, when the address AD is "1", the data DT is the "first time" of the concatenation control output, and when the address AD is "2", the data DT is the concatenation control output [2nd time J, address AD
When the address AD is "3", the data DT is output as the "third time" of the concatenation control output, and when the address AD is [4], the data DT is output so as to indicate the number of concatenation control outputs (the concatenation control number).

At this time, the address decoder (8) in the constant mark decoding output section (2) decomposes the address AD and converts the significant signal A into R.
By inputting to the AM control section (27), the address A
When the content of D is "1", "2" or "3", the RAM switching signal RC is
) side, and in other cases, it is set to the address counter (22) side, that is, the "internal side."

Also, based on the write pulse WR, the RAM control unit (27)
The write trigger WT generated by is gated by the RAMgJ conversion signal RC in the RAM address selector (24), becomes a write pulse WP, and is converted to RAM (2).
9). As a result, the RAM (29) has
The first to third connection control output data are stored.

Although not shown, at the time of initialization, the RAM (29)
RAM (29) with address AD as “0”.
“0 (normal)” is stored in .

When the address AD is "4", the address counter (22) is preset with the number of times of concatenation control by the pulse WR, and the RAM control section (27) outputs a count-up signal.

The count-up signal is r
Close the output game) and set the address from (23) to "0"
, "0 (normal)" is output from RAM <29).

When the count-up signal changes from the rl level to the "H" level, the address counter (22) is incremented at this change point (rising), and the RA
The first data is output from M (29). As a result, the output relay (10) inputs the contents of RAM (29) to the constant mark verification and point decomposition section (11), and the constant mark verification and point decomposition section (11) inputs the contents of the RAM (29) into the group and point decomposition section (11) as described above. Constant mark verification is performed according to the constant mark code of the point and the constant mark code for control.

Further, the 1 second timer (12) drives the Z relay (14) with the 1 second pulse P1 and outputs the control signal C.
The 1-second pulse P1 is also input to the RAM III control section (27).

When the 1-second pulse P1 becomes involuntary, the RAM control unit (27) sets the count amplifier signal to the "yes" level. In order to match the actual operating timing of contact Z, the fall timing of the count-up signal is slightly delayed from the fall of the one-second pulse P1, as shown.

In this way, the address counter (22
) is incremented, and at the fourth rise of the count-up signal, the address counter (
The contents of 22) are r4. is going to be incremented.

At this time, the contents of the address counter (22) exceed the preset number of times of connection control (3 in this example), so the address counter (22) resets the contents to "0" and A carry signal M is output to the RAM control section (27). The RAM control unit (27) outputs the carry signal M as is to the master controller (1) as an interrupt signal IN.

When the interrupt signal IN is input, the master controller (1) determines that a series of connected control output operations based on the previously input data DT has been completed, and sends the constant mark decoding output unit (2) to the next The data DT is output to perform the same connection control output operation as described above.

In this way, a plurality of data DT are stored in RAM <29), and the concatenated control output operation is performed by the constant mark decoding output unit (2
), and the end of the connected control output operation can be indicated to the master controller (1) by the interrupt signal IN. Therefore, the data DT can be output without any need for time management on the master controller (1) side.

In the above embodiment, the number of times of connection control is three times, but the number of times of connection 11 control may be four or more times.

In addition, R is used as a storage means for storing connection control data.
Although A M (29) is used, the same effect can be achieved by using FIFO or scratch pad memory.

In this case, it goes without saying that a storage means control section corresponding to any storage means is used in place of the RAM ilJ control section (27).

[Effects of the Invention] As described above, according to the invention of the present invention, an interrupt signal is output to the master controller 1-roller when the operation of the position selection contact based on the 1-second pulse becomes involuntary. Since the interrupt control section is provided, it is possible to obtain a selective control output circuit that ensures the connected control output operation and reduces the processing load on the master controller.

Further, according to the second aspect of the present invention, when data is illegally received from the master controller during the operation of the position selection contact based on a one-second pulse, an interrupt signal is issued to the master controller. An interrupt control unit is provided to indicate that the connected control output operation of the latest input data cannot be executed while the connected control output operation is being performed based on the previous data, so that the connected control output operation is ensured and the master controller This has the effect of providing a selection control output circuit with a reduced processing load.

Further, according to the third aspect of the present invention, there is provided a storage means for storing a plurality of data corresponding to the connection control data, an address counter in which the number of times of connection control from the master controller is set, and a position counter based on the one second pulse. a storage means control unit that controls the storage means and increments an address counter in response to the operation of the selection contact, and outputs an interrupt signal to the master controller when the contents of the address counter reach the number of times of connection control; The selective control output circuit side stores a plurality of pieces of data, continuously executes the connected control output operation, and uses an interrupt signal to notify the master controller of the end of the connected control output operation. This has the effect of providing a selection control output circuit that reliably performs the connected flijm output operation and eliminates the need for time management on the master controller side.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the first invention of the present invention, Fig. 2 is a timing chart diagram for explaining the operation of Fig. 1, and Fig. 3 is a circuit diagram showing an embodiment of the first invention of the present invention. 4 is a circuit diagram showing another embodiment of the present invention, FIG. 5 is a timing chart for explaining the operation of FIG. 4, and FIG. 6 is a circuit diagram showing another embodiment of the present invention. is a circuit diagram showing an embodiment of the third aspect of the present invention, FIG. 7 is a timing chart diagram for explaining the operation of FIG. 6, and FIG. 8 is a circuit diagram showing a conventional selection control output circuit. FIG. 9 is a timing chart for explaining the operation of No. 8171. (1) Master controller (2) Constant mark decoding output section (selection control output circuit) 3)
Monitored control device 1)... Constant mark verification and point resolution unit 12) - 1 second timer 15 - Position selection contact 20), (20^) - Interrupt control unit 22) - Address counter (27) - RAM control unit (storage means control unit) (29.
・RAM (storage means) DT...Data C・Control signal E Verification signal Pl...1 second pulse Q・Illegal signal L...Count up signal M・Carry signal IN, ■NA, IN, l・Interrupt Signal. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] (1) A constant mark verification and point decomposition unit that performs constant mark verification and point decomposition of the data based on data from a master controller connected to a remote control device; a 1-second timer that outputs a 1-second pulse when the result is good; and a position selection contact that is selectively driven based on the constant mark verification and point resolution section and the 1-second timer; In a selection control output circuit that outputs a control signal to a monitored control device via a selection contact, an interrupt is sent to the master controller when the operation of the position selection contact based on the 1-second pulse becomes involuntary. A selection control output circuit comprising an interrupt control section that outputs a signal. 2) a constant mark verification and point decomposition unit that performs constant mark verification and point decomposition of the data based on data from a master controller connected to a remote control device; a 1-second timer that outputs a second pulse; and a position selection contact that is selectively driven based on the constant mark verification and point resolution section and the 1-second timer, and is monitored via the position selection contact. In a selection control output circuit that outputs a control signal to a control device, when the data is illegally written from the master controller while the position selection contact is operating based on the 1-second pulse, the selection control output circuit outputs a control signal to the master controller. 1. A selection control output circuit comprising an interrupt control section that outputs an interrupt signal. (3) a constant mark verification and point decomposition unit that performs constant mark verification and point decomposition of the data based on data from a master controller connected to a remote control device; and when the constant mark verification result is good; a 1-second timer that outputs a 1-second pulse; and a position selection contact that is selectively driven based on the constant mark verification and point resolution section and the 1-second timer, and a position selection contact that outputs a 1-second pulse. In a selection control output circuit that outputs a control signal to a supervisory control device, a storage means for storing a plurality of pieces of data corresponding to the number of times of connection control for the monitored control device; an address counter that is incremented every time a connected control output operation is performed; and in response to the operation of the position selection contact based on the one-second pulse, the storage means is controlled and the address counter is incremented, and the contents of the address counter are A selection control output circuit comprising: a storage means control unit that outputs an interrupt signal to the master controller when the number of times of connection control is reached.