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JPH04199608A - Manufacture of soi wafer - Google Patents

Manufacture of soi wafer

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Publication number
JPH04199608A
JPH04199608A JP32597390A JP32597390A JPH04199608A JP H04199608 A JPH04199608 A JP H04199608A JP 32597390 A JP32597390 A JP 32597390A JP 32597390 A JP32597390 A JP 32597390A JP H04199608 A JPH04199608 A JP H04199608A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor substrate
oxygen
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32597390A
Other languages
Japanese (ja)
Inventor
Toru Miyayasu
宮保 徹
Fumitoshi Sugimoto
文利 杉本
Yoshihiro Arimoto
由弘 有本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP32597390A priority Critical patent/JPH04199608A/en
Publication of JPH04199608A publication Critical patent/JPH04199608A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To prevent the instable state of a laminated interface by a method wherein the Si semiconductor supporting substrate, which is covered by an insulating film having an excess-oxygen layer on the surface, and another Si semiconductor substrate are opposingly positioned and they are closely fixed. CONSTITUTION:An Si semiconductor supporting substrate 13 and an Si semiconductor substrate 11, which is covered by an insulating film 14 and having an excess-oxygen layer 14A, whereon excessive oxygen is introduced on the surface, are closely fixed in an opposing manner. An oxide film 11A is grown by diffusing oxygen on the semiconductor substrate by conducting a heat treatment, and the Si semiconductor substrate and the Si semiconductor substrate are laminated. Then, an Si semiconductor active layer is formed by thinning off the Si semiconductor substrate 11. Accordingly, the interface which works as the interface of the semiconductor active layer and the base oxide film is the oxide layer, which is grown by diffusing excessive oxygen generated in the oxide film when the heat treatment for lamination is conducted, and the remaining semiconductor active layer. As a result, the instable state of the interface can be substantially removed completely.

Description

【発明の詳細な説明】 〔概要] 絶縁層上に半導体層が在る半導体ウェハ、即ち、SOI
ウェハを製造する方法の改良に関し、簡単な手段を採る
ことに依り、Si半導体基板と下地の酸化膜との界面を
実際の貼り合わせ界面とは異なった位置、即ち、Si半
導体基板内に生成させ、貼り合わせ界面に於ける状態の
不安定や重金属などの不純物が半導体装置に悪影響を与
えるのを回避することを目的とし、 過剰な酸素が導入された酸素過剰層を表面にもつ絶縁膜
で覆われたSi半導体支持基板とSi半導体基板を対向
して密着させ且つ熱処理を行って該酸素を該Si半導体
基板に拡散させて酸化物膜を生成させると共にSi半導
体支持基板とSi半導体基板とを貼り合わせ、次いで、
前記Si半導体基板の薄膜化を行ってSi半導体活性層
とする工程が含まれてなるよう構成する。
[Detailed Description of the Invention] [Summary] A semiconductor wafer having a semiconductor layer on an insulating layer, that is, an SOI
Regarding the improvement of the method of manufacturing wafers, by adopting a simple method, the interface between the Si semiconductor substrate and the underlying oxide film is created at a different position from the actual bonding interface, that is, within the Si semiconductor substrate. In order to avoid the instability of the state at the bonding interface and the adverse effects of impurities such as heavy metals on semiconductor devices, the semiconductor device is covered with an insulating film with an oxygen-rich layer on the surface into which excess oxygen is introduced. The Si semiconductor support substrate and the Si semiconductor substrate are placed in close contact with each other facing each other, and heat treatment is performed to diffuse the oxygen into the Si semiconductor substrate to generate an oxide film, and the Si semiconductor support substrate and the Si semiconductor substrate are bonded together. Combine, then
The method is configured to include a step of thinning the Si semiconductor substrate to form a Si semiconductor active layer.

〔産業上の利用分野] 本発明は、絶縁層上に半導体層が在る半導体つ1/’t
、即ち、SOI  (silicon  on  1n
sulator)ウェハを製造する方法の改良に関する
[Industrial Application Field] The present invention relates to a semiconductor device in which a semiconductor layer is on an insulating layer.
, that is, SOI (silicon on 1n
The present invention relates to an improvement in a method of manufacturing a sulator wafer.

SOI構造を利用した半導体装置は、接合容量及び配線
容量が低減されるので、素子特性を向上させることがで
き、また、表面から絶縁層に達する絶縁分離領域を形成
することで雑音に対する耐性を高めることができる。
Semiconductor devices using an SOI structure can improve device characteristics because the junction capacitance and wiring capacitance are reduced, and also improve noise resistance by forming an isolation region that reaches from the surface to the insulating layer. be able to.

このようなSOI構造のなかでも、素子が作り込まれる
活性層の結晶性、或いは、従来からの半導体装置の製造
プロセスとの整合性などの面から貼り合わせSOIウェ
ハが注目されているのであるが、未だ、解決しなければ
ならない問題を抱えている。
Among these SOI structures, bonded SOI wafers are attracting attention because of the crystallinity of the active layer in which elements are built, and their compatibility with conventional semiconductor device manufacturing processes. , there are still problems that need to be solved.

〔従来の技術〕[Conventional technology]

第5図乃至第8図は高速バイポーラ半導体装置を製造す
る場合に用いて好適なSOIウエノ\を作成する従来の
技術を説明する為の工程要所に於けるSOIウェハの要
部切断側面図を表し、以下、これ等の図を参照しつつ解
説する。尚、SO■ウェハの場合、基本的には、Si半
導体基板とSi半導体支持基板とを貼り合わせるのであ
るが、その貼り合わせを行う前の段階でSi半導体基板
及びSi半導体支持基板にそれぞれ別個に施す処理や加
工は、どちらの基板について先に行うかは任意であり、
また、同時であっても良いことは勿論である。
Figures 5 to 8 are cross-sectional side views of essential parts of an SOI wafer at important points in the process to explain a conventional technique for creating an SOI wafer suitable for manufacturing high-speed bipolar semiconductor devices. This will be explained below with reference to these figures. In the case of SO wafers, basically the Si semiconductor substrate and the Si semiconductor support substrate are bonded together, but before the bonding, the Si semiconductor substrate and the Si semiconductor support substrate are separately bonded. It is up to you which substrate to perform the processing or processing on first.
Moreover, it goes without saying that they may be performed at the same time.

第5図参照 イオン注入法を通用することに依り、Asなどのドーパ
ント・イオンをSi半導体基板1に打ち込んで、不純物
導入層2を形成する。
Referring to FIG. 5, by applying the ion implantation method, dopant ions such as As are implanted into the Si semiconductor substrate 1 to form an impurity-introduced layer 2.

第6図参照 熱酸化法を適用することに依り、Si半導体支持基板3
にSin、からなる絶縁膜4を形成する。
By applying the thermal oxidation method (see FIG. 6), the Si semiconductor support substrate 3
An insulating film 4 made of Sin is then formed.

第7図参照 不純物導入層2をもつSi半導体基板1と絶縁wA4を
もつSi半導体支持基板3とを不純物導入層2と絶縁膜
4とが対向するようにして貼り合わせる。
Refer to FIG. 7. A Si semiconductor substrate 1 having an impurity-introduced layer 2 and a Si semiconductor support substrate 3 having an insulating wA4 are bonded together so that the impurity-introduced layer 2 and the insulating film 4 face each other.

第8図参照 Si半導体基板1を研削及び研磨することで薄膜化され
たSi半導体活性層1′を得る。
Referring to FIG. 8, by grinding and polishing the Si semiconductor substrate 1, a thin Si semiconductor active layer 1' is obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

一般に、絶縁膜4はSi半導体活性層1′の母体である
Si軍導体基板1側に形成するか、或いは、Si半導体
基板1とSi半導体支持基板3との両方に形成すること
が多い。
Generally, the insulating film 4 is often formed on the Si conductor substrate 1 side which is the base of the Si semiconductor active layer 1', or on both the Si semiconductor substrate 1 and the Si semiconductor supporting substrate 3.

若し、Si半導体支持基板3例のみに形成したとすると
、貼り合わせ界面は、前記従来の技術の説明に見られる
ように、Si半導体活性層1′と絶縁wA4との界面そ
のものとなり、Si半導体活性Ill’に半導体装置を
作り込んだ場合、その半導体装置の中に貼り合わせ界面
が入り込んだ状態となる。
If it is formed on only three Si semiconductor supporting substrates, the bonding interface will be the interface itself between the Si semiconductor active layer 1' and the insulating wA4, as seen in the explanation of the conventional technology, and the Si semiconductor When a semiconductor device is fabricated in the active Ill', the bonding interface enters into the semiconductor device.

本来、貼り合わせ界面は、文字通り、別体のものを貼り
合わせた面なのであるから、その界面には重金属などの
不純物が存在するなど、汚染される虞が極めて高いこと
は云うまでもない。
Since the bonded interface is literally a surface where two separate objects are bonded together, it goes without saying that there is an extremely high risk of contamination, such as the presence of impurities such as heavy metals, at the interface.

従って、一般には、少なくとも半導体装置を作り込むべ
きSi半導体活性層1′側を熱酸化して絶縁膜4を形成
するようにしている。そのようにした場合には、Si半
導体活性層1′と絶縁膜4と界面は清浄であって、汚染
物などは全て絶縁膜4の表面に出てしまう。
Therefore, generally, the insulating film 4 is formed by thermally oxidizing at least the side of the Si semiconductor active layer 1' in which a semiconductor device is to be fabricated. In this case, the interface between the Si semiconductor active layer 1' and the insulating film 4 is clean, and all contaminants and the like come out to the surface of the insulating film 4.

然しながら、SOIウェハに作り込むべき半導体装置の
種類に依っては、Si半導体活性層1′の母体であるS
i半導体基板1側を熱酸化することが常に可能であると
は限らない。
However, depending on the type of semiconductor device to be fabricated on the SOI wafer, S, which is the base material of the Si semiconductor active layer 1', may be
i It is not always possible to thermally oxidize the semiconductor substrate 1 side.

前記例示した従来の技術の場合もSi半導体基板1側に
絶縁膜4を形成することができないものの一つである。
The conventional technique exemplified above is also one in which the insulating film 4 cannot be formed on the Si semiconductor substrate 1 side.

即ち、そこで必要としているS0Iウェハは、バイポー
ラ半導体装置を組み込む為のものであるから、コレクタ
を引き出す為の埋め込み層を必要とするのであるが、こ
の埋め込み層を形成する為のイオン注入を行ってから、
即ち、不純物導入層2を形成してから熱酸化を行ったの
では、それが熱拡散されてしまって、その制御は容易で
はない、と言うよりも、むしろ、困難と言うべきである
。尚、Si半導体基板1側に絶縁膜4を形成することが
できないケースは、前記事例のみでなく、他にも多くが
存在する。
In other words, since the S0I wafer needed there is for incorporating a bipolar semiconductor device, it requires a buried layer to draw out the collector, but ion implantation is performed to form this buried layer. from,
That is, if thermal oxidation is performed after forming the impurity-introduced layer 2, the impurity will be thermally diffused, and its control is not easy, but rather difficult. Note that there are many other cases, not only the above case, in which the insulating film 4 cannot be formed on the Si semiconductor substrate 1 side.

前記したようなことから、第5図乃至第8図Gこついて
説明した従来の技術では、Si半導体支持基板3側に絶
縁膜4を形成してpsるのである力く、このようにした
場合、Si半導体活性層1′と絶縁膜4との界面が貼り
合わせ界面そのものになることから、その界面の状態は
不安定であり、重金属などの不純物も溜まり易く、しか
も、そのようなことが半導体装置の特性に直接的に悪影
響を及ぼす虞がある。
For the reasons mentioned above, in the conventional technique explained in FIGS. 5 to 8G, the insulating film 4 is formed on the Si semiconductor support substrate 3 side. Since the interface between the Si semiconductor active layer 1' and the insulating film 4 is the bonding interface itself, the state of the interface is unstable and impurities such as heavy metals are likely to accumulate. There is a possibility that the characteristics of the device will be directly affected.

本発明は、簡単な手段を採ることに依り、Si半導体活
性層と下地の酸化膜との界面を実際の貼り合わせ界面と
は異なった位置、即ち、Si半導体活性層内に生成させ
、貼り合わせ界面に於ける状態の不安定や重金属などの
不純物が半導体装置に悪影響を与えるのを回避しようと
する。
The present invention employs simple means to create an interface between the Si semiconductor active layer and the underlying oxide film at a position different from the actual bonding interface, that is, within the Si semiconductor active layer, and bond the Si semiconductor active layer to the underlying oxide film. An attempt is made to avoid unstable conditions at the interface and impurities such as heavy metals from adversely affecting semiconductor devices.

(課題を解決するための手段〕 本発明に依る301ウエハの製造方法に於し)では、 (1)過剰な酸素が導入された酸素過剰層(11えci
14A)を表面にもった絶縁膜(例えば絶縁膜14)で
覆われたSi半導体支持基板(例えばSi半導体支持基
板13)並びにSi半導体基板(例えばSi半導体基板
11)を対向して密着させ且つ熱処理を行って該酸素を
該Si半導体基板に拡散させて酸化物膜(例えば酸化物
膜11A)を生成させると共にSi半導体支持基板とS
i半導体基板とを貼り合わせ、次1.zで、前記Si半
導体基板の薄膜化を行ってSi半導体活性層(例えばS
i半導体活性層11′)とする工程 が含まれてなるか、或いは、 (2)前記(1)に於いて、Si半導体支持基板を覆う
絶縁膜の表面に酸素イオンを注入して酸素過剰層を生成
させること を特徴とするか、或いは、 (3)前記(1)に於いて、Si半導体支持基板と貼り
合わせる側に於けるSi半導体基板の表面に導電性を付
与する不純物層(例えばn型不純物層12)を形成する
こと を特徴とする。
(Means for Solving the Problems) In the method for manufacturing a 301 wafer according to the present invention, (1) an oxygen-excess layer into which excess oxygen is introduced (11 wafers);
A Si semiconductor support substrate (e.g., Si semiconductor support substrate 13) and a Si semiconductor substrate (e.g., Si semiconductor substrate 11) covered with an insulating film (e.g., insulating film 14) having 14A) on the surface thereof are placed in close contact with each other facing each other, and heat-treated. The oxygen is diffused into the Si semiconductor substrate to form an oxide film (for example, the oxide film 11A), and the Si semiconductor support substrate and S
i Paste together the semiconductor substrate and proceed as follows 1. In step z, the Si semiconductor substrate is thinned to form a Si semiconductor active layer (for example, S
(2) In step (1) above, oxygen ions are implanted into the surface of the insulating film covering the Si semiconductor support substrate to form an oxygen-excess layer. (3) In the above (1), an impurity layer (for example, n A type impurity layer 12) is formed.

〔作用] 前記手段を採ることで作成されたSOIウェハに於いて
、Si半導体活性層と下地の酸化膜との界面として作用
するのは、実際のSi半導体活性層と酸化膜との界面で
はなく、その貼り合わせの熱処理時に酸化膜中の酸素イ
オン打ち込み層に於ける過剰な酸素がSi半導体活性層
となるSi半導体基板に拡散することで生成される酸化
物層とそのような酸素が入り込まずに残った半導体活性
層との界面となるものであり、換言すると、その界面は
Si半導体基板内に新たに生成されるものである。従っ
て、その実質的な界面に於ける状態の不安定は皆無であ
り、そして、重金属などの不純物が溜まる虞も少なくな
いことから、半導体装置を製造した場合に特性が悪影響
を受けることは少なくなる。
[Function] In the SOI wafer created by adopting the above method, it is not the actual interface between the Si semiconductor active layer and the oxide film that acts as the interface between the Si semiconductor active layer and the underlying oxide film. During the heat treatment for bonding, excess oxygen in the oxygen ion implantation layer in the oxide film diffuses into the Si semiconductor substrate that becomes the Si semiconductor active layer, forming an oxide layer and preventing such oxygen from entering. In other words, the interface is newly generated within the Si semiconductor substrate. Therefore, there is virtually no instability in the state at the interface, and there is a considerable risk that impurities such as heavy metals may accumulate, so when semiconductor devices are manufactured, their characteristics are less likely to be adversely affected. .

〔実施例〕〔Example〕

第1図乃至第4図は本発明一実施例を説明する為の工程
要所に於けるSOIウェハの要部切断側面図を表し、以
下、これ等の図を参照しつつ詳細に解説する。
1 to 4 are cross-sectional side views of essential parts of an SOI wafer at key points in the process for explaining one embodiment of the present invention, and detailed explanation will be given below with reference to these figures.

第1図参照 イオン注入法を適用することに依り、ドーズ量を例えば
5 X l (l l5(ci+−”) 、また、加速
エネルギを例えば60 (KeV)としてSi半導体基
板11にAsイオンの打ち込みを行ってn型不純物fi
12を形成する。尚、このn型不純物層12は必要に応
じて形成するものであって必須ではなく、不純物イオン
も必要に応じて選択され、Asに限られるものではない
。また、打ち込まれたAsは、熱処理を受けた段階で活
性化されることは云うまでもない。
As ions are implanted into the Si semiconductor substrate 11 by applying the ion implantation method shown in FIG. to add n-type impurity fi
form 12. Note that this n-type impurity layer 12 is formed as needed and is not essential, and the impurity ions are also selected as needed and are not limited to As. Further, it goes without saying that the implanted As is activated during the heat treatment.

第2図参照 熱酸化法を適用することに依り、Si半導体支持基板1
3に厚さが例えば1[μm〕のSiO2からなる絶縁膜
14を形成する。
By applying the thermal oxidation method (see FIG. 2), the Si semiconductor support substrate 1
An insulating film 14 made of SiO2 and having a thickness of, for example, 1 [μm] is formed on the substrate 3.

イオン注入法を適用することに依り、ドーズ量を例えば
l x l Q I5(am−2) 、また、加速エネ
ルギを例えば20 (KeV)としてSi半導体基板1
1と貼り合わせられる側の絶縁膜14に酸素イオンの打
ち込みを行って、厚さが例えば50(nm)である酸素
過剰層14Aを生成させる。
By applying the ion implantation method, the Si semiconductor substrate 1 is implanted at a dose of, for example, l x l Q I5 (am-2) and an acceleration energy of, for example, 20 (KeV).
Oxygen ions are implanted into the insulating film 14 on the side to be bonded to the insulating film 14 to form an oxygen-excess layer 14A having a thickness of, for example, 50 (nm).

第3図参照 Si半導体基板11のn型不純物N12及びSi半導体
支持基板13の酸素過剰層14Aとを対向させ、温度7
00ビC]の雰囲気で密着させ、次いで、温度を100
0(”C)とした窒素雰囲気で30(分〕間の熱処理を
施すことでSi半導体基板11とSi半導体支持基板1
3とを貼り合わせる。
Refer to FIG. 3. The n-type impurity N12 of the Si semiconductor substrate 11 and the oxygen-excess layer 14A of the Si semiconductor support substrate 13 are placed facing each other at a temperature of 7.
00V], and then the temperature was increased to 100V.
The Si semiconductor substrate 11 and the Si semiconductor support substrate 1 are heated by heat treatment for 30 (minutes) in a nitrogen atmosphere set to 0 ("C).
Paste 3 together.

この貼り合わせに於ける前記熱処理の際、酸素過剰層1
4AからSi半導体基板11中に酸素が拡散されるので
、それに依る酸化物膜11AがSi半導体基板ll中に
生成される。尚、第3図に於いては、これに依って新た
に生成された界面を記号15Aで、実際の貼り合わせ界
面を記号15Bで指示しである。
During the heat treatment in this bonding, the oxygen-excess layer 1
Since oxygen is diffused from 4A into the Si semiconductor substrate 11, an oxide film 11A is generated in the Si semiconductor substrate 11. In FIG. 3, the newly generated interface is indicated by symbol 15A, and the actual bonded interface is indicated by symbol 15B.

第4図参照 ダイヤモンド砥石を利用してSi半導体基板11の研削
を行い、厚さを例えば10〔μm〕程度とする。
Referring to FIG. 4, the Si semiconductor substrate 11 is ground using a diamond grindstone to a thickness of, for example, about 10 [μm].

アミンの水溶液にコロイダル・シリカを僅かに混入して
研磨剤とし、また、不織布からなる研磨布を用い、Si
半導体基板11の研削面を研磨して厚さ例えば3〔μm
〕のSi半導体活性層ii’ とする。
A slight amount of colloidal silica is mixed into an aqueous solution of amine as an abrasive, and a polishing cloth made of non-woven fabric is used to polish Si.
The ground surface of the semiconductor substrate 11 is polished to a thickness of, for example, 3 μm.
] as the Si semiconductor active layer ii'.

前記したところから明らかであるが、作成されたSOI
ウェハに於いて、半導体装置の動作に関与するSi半導
体活性11i11’ と酸化膜との実質的な界面は、S
i半導体活性層11′中に新たに生成されん界面15A
であって、貼り合わせ界面15Bとは異なった位置にあ
り、貼り合わせ界面15Bが半導体装置の中の構成要素
になることはない。
As is clear from the above, the created SOI
In the wafer, the substantial interface between the Si semiconductor active layer 11i11' and the oxide film, which is involved in the operation of the semiconductor device, is S
An interface 15A that is not newly generated in the i-semiconductor active layer 11'
Therefore, it is located at a different position from the bonding interface 15B, and the bonding interface 15B does not become a component in the semiconductor device.

〔発明の効果〕〔Effect of the invention〕

本発明に依るSOIウェハの製造方法に於いては、酸素
過剰層を表面にもった絶縁膜で覆われたSi半導体支持
基板並びにSi半導体基板を対向して密着させ、熱処理
を行って酸素を該Si半導体基板に拡散させて酸化物膜
を生成させると共にSi半導体支持基板とSi半導体基
板とを貼り合わせ、Si半導体基板の研削及び研磨を行
って薄膜のSi半導体活性層としている。
In the method for manufacturing an SOI wafer according to the present invention, a Si semiconductor support substrate covered with an insulating film having an oxygen-rich layer on the surface and a Si semiconductor substrate are placed in close contact with each other, and heat treatment is performed to remove oxygen. It is diffused into the Si semiconductor substrate to form an oxide film, the Si semiconductor support substrate and the Si semiconductor substrate are bonded together, and the Si semiconductor substrate is ground and polished to form a thin Si semiconductor active layer.

前記構成を採ることで作成されたSOIウェハに於いて
、31半導体活性層と下地の酸化膜との界面として作用
するのは、実際のSi半導体活性層と酸化膜との界面で
はなく、その貼り合わせの熱処理時に酸化膜中の酸素イ
オン打ち込み層に於ける過剰な酸素がSi半導体活性層
となるSi半導体基板に拡散することで生成される酸化
物層とそのような酸素が入り込まずに残った半導体活性
層との界面となるものであり、換言すると、その界面は
Si半導体基板内に新たに生成されるものである。従っ
て、その実質的な界面に於ける状態の不安定は皆無であ
り、そして、重金属などの不純物が溜まるおそれも少な
くないことから、半導体装置を製造した場合に特性が悪
影響を受けることは少なくなる。
In the SOI wafer created by adopting the above configuration, what acts as the interface between the 31 semiconductor active layer and the underlying oxide film is not the actual interface between the Si semiconductor active layer and the oxide film, but the bonded interface. During the heat treatment for bonding, excess oxygen in the oxygen ion implantation layer in the oxide film diffuses into the Si semiconductor substrate, which becomes the Si semiconductor active layer, resulting in an oxide layer and an oxide layer where such oxygen does not enter and remains. It becomes an interface with the semiconductor active layer; in other words, the interface is newly generated within the Si semiconductor substrate. Therefore, there is virtually no instability in the state at the interface, and there is a considerable risk that impurities such as heavy metals may accumulate, so when semiconductor devices are manufactured, their characteristics are less likely to be adversely affected. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は本発明一実施例を説明する為の工程
要所に於けるS○■ウェハの要部切断側面図、第5図乃
至第8図は従来例を説明する為の工程要所に於けるSO
Iウェハの要部切断側面図をそれぞれ表している。 図に於いて、11はSi半導体基板、IIAは酸化物膜
、12はn型不純物層、13は31半導体支持基板、1
4は絶縁膜、14Aは酸素過剰層、15A及び15Bは
界面をそれぞれ示している。 特許出願人   富士通株式会社 代理人弁理士  相 谷 昭 司 代理人弁理士  渡 邊 弘 − 11・31半導体基板 第1図 第2図 11’: S i半導体活性層 を 第4図 第5図 第6図
Figures 1 to 4 are cutaway side views of essential parts of an S○■ wafer at key points in the process for explaining one embodiment of the present invention, and Figures 5 to 8 are side views for explaining a conventional example. SO at key points in the process
2A and 2B each represent a cutaway side view of a main part of an I wafer. In the figure, 11 is a Si semiconductor substrate, IIA is an oxide film, 12 is an n-type impurity layer, 13 is 31 semiconductor support substrate, 1
4 is an insulating film, 14A is an oxygen-rich layer, and 15A and 15B are interfaces, respectively. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aiya Representative Patent Attorney Hiroshi Watanabe - 11/31 Semiconductor substrate Figure 1 Figure 2 Figure 11': Si semiconductor active layer Figure 4 Figure 5 Figure 6 figure

Claims (3)

【特許請求の範囲】[Claims] (1)過剰な酸素が導入された酸素過剰層を表面にもつ
絶縁膜で覆われたSi半導体支持基板並びにSi半導体
基板を対向して密着させ且つ熱処理を行って該酸素を該
Si半導体基板に拡散させて酸化物膜を生成させると共
にSi半導体支持基板とSi半導体基板とを貼り合わせ
、 次いで、前記Si半導体基板の薄膜化を行ってSi半導
体活性層とする工程 が含まれてなることを特徴とするSOIウェハの製造方
法。
(1) A Si semiconductor support substrate covered with an insulating film having an oxygen-excess layer on the surface into which excess oxygen has been introduced and a Si semiconductor substrate are placed in close contact with each other facing each other, and heat treatment is performed to transfer the oxygen to the Si semiconductor substrate. It is characterized by including the steps of: diffusing to form an oxide film, bonding a Si semiconductor support substrate and a Si semiconductor substrate, and then thinning the Si semiconductor substrate to form a Si semiconductor active layer. A method for manufacturing an SOI wafer.
(2)Si半導体支持基板を覆う絶縁膜の表面に酸素イ
オンを注入して酸素過剰層を生成させること を特徴とする請求項1記載のSOIウェハの製造方法。
(2) The method for manufacturing an SOI wafer according to claim 1, characterized in that oxygen ions are implanted into the surface of the insulating film covering the Si semiconductor support substrate to generate an oxygen-excess layer.
(3)Si半導体支持基板と貼り合わせる側に於けるS
i半導体基板の表面に導電性を付与する不純物層を形成
すること を特徴とする請求項1記載のSOIウェハの製造方法。
(3) S on the side to be bonded to the Si semiconductor support substrate
2. The method of manufacturing an SOI wafer according to claim 1, further comprising forming an impurity layer imparting conductivity on the surface of the semiconductor substrate.
JP32597390A 1990-11-29 1990-11-29 Manufacture of soi wafer Pending JPH04199608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32597390A JPH04199608A (en) 1990-11-29 1990-11-29 Manufacture of soi wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32597390A JPH04199608A (en) 1990-11-29 1990-11-29 Manufacture of soi wafer

Publications (1)

Publication Number Publication Date
JPH04199608A true JPH04199608A (en) 1992-07-20

Family

ID=18182663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32597390A Pending JPH04199608A (en) 1990-11-29 1990-11-29 Manufacture of soi wafer

Country Status (1)

Country Link
JP (1) JPH04199608A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136108A (en) * 1991-11-08 1993-06-01 Shin Etsu Handotai Co Ltd Manufacture of soi substrate
JPH06104153A (en) * 1992-03-16 1994-04-15 American Teleph & Telegr Co <Att> Manufacture of semiconductor integrated circuit
JP2013171951A (en) * 2012-02-20 2013-09-02 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same
JP2015103785A (en) * 2013-11-28 2015-06-04 京セラ株式会社 Manufacturing method of light emitting / receiving element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136108A (en) * 1991-11-08 1993-06-01 Shin Etsu Handotai Co Ltd Manufacture of soi substrate
JPH06104153A (en) * 1992-03-16 1994-04-15 American Teleph & Telegr Co <Att> Manufacture of semiconductor integrated circuit
JP2013171951A (en) * 2012-02-20 2013-09-02 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same
JP2015103785A (en) * 2013-11-28 2015-06-04 京セラ株式会社 Manufacturing method of light emitting / receiving element

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