JPH04192182A - Sense amplifier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention applies to semiconductor integrated storage devices, especially dynamic RA.
It concerns a sense amplifier that amplifies M stored data.

[Prior Art] Figure 4 is a block diagram showing the overall configuration of a conventional sense amplifier. In the figure, (1) is the sense amplifier, (2)
is the bit line connected to the sense amplifier (1), (3) is the memory array, (4) is the P-channel A7MOEL) transistor, (5) is the N-channel MO8) fungistor, (6) is the
) is Vcc, and (7) is Grld. Figure 5 is the 4th
The circuit diagram of the sense amplifier (1) shown in Fig. 6 is the memory amplifier (1).
A circuit diagram of a memory cell of array (3), in which:
(6) is a capacitor, (9) is a cell plate, and (8) is a word line with a fixed potential. FIG. 7 is a waveform diagram showing the operation of FIG. 6.

Next, the operation will be explained. The word line WL becomes aHm due to the X address, then the sense amplifier activation signal Sm becomes H1, T R1 (5) turns ON, and the signal 8
Then, the sense amplifier activation signal Sp becomes #L#, T R2 (41 goes from 0 to 0), and the signal 13v is tried to become #R". All bit lines BL, BL are amplified.

Since the signals Sv and Sg, which are sense amplifier drive signals, are connected to all sense amplifiers (1) in one column, long wiring is required, and the wiring is made of aluminum with a sheet resistance of 100 mΩ and a length of 5. If the width is 10 μm,
A wiring resistance of approximately 5 On is attached. In order to amplify the capacitance of all bit lines to 1H#, a L g, the total capacitance is 0.29F per bit line, and if there are 1024 lines, then 0.2 pr x 1024 lines/20S pF
The delay time of a long wiring is that the difference between the source and the tip of the sense amplifier drive signal is t = CR = 205pL'x 5041$ 10n
s, and the time difference t between BL- and BLn in FIG. 7 is at least 10 ns. In semiconductor integrated circuits,
In today's world where high-speed volumes with fast access times are required, a delay of 10 days is an outrageous value.

1. Problems to be Solved by the Invention Since conventional sense amplifiers are configured as described above, in order to amplify data in memory cells, it is necessary to connect the sense amplifier to the sense amplifier from the source of the sense amplifier drive signal. There is a problem in that there is a difference in delay time between the operations of the sense amplifier whose drive signal wiring is closest and the sense amplifier whose sense amplifier drive signal wiring is farthest.

This invention was made to solve the above-mentioned problems.The signal wiring from the source of the signal that drives the sense amplifier is connected to the closest sense amplifier and the farthest sense amplifier. The object of the present invention is to obtain a sense amplifier that compensates for the delay time of the sense amplifier operation and improves the sense margin.

[Means for Solving the Problems j] A sense amplifier according to the present invention is such that sense amplifiers are provided at both ends of a bit line pair, and the two sense amplifiers amplify the bit line pair.

[Effect]

Since the sense amplifier in this invention is designed to amplify from both ends of the bit line pair, the sensing time becomes faster and the sense margin improves.

[! li! Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing the overall configuration of a sense amplifier which is an embodiment of the present invention. In the figure, (1) is a sense amplifier.
The amplifier (2) is a bit line connected to the sense amplifier (1), passes through the select circuit (10), and is connected to the memory array (3). Bit line (2) is sense
Two memory arrays (3) above and below, centered around the amplifier (1)
connected to the block. Bit line (2) connects all blocks of memory array (3) with select circuit (1).
0).

2 shows an operating waveform diagram of the circuit of FIG. 1, and FIG. 3 shows a circuit diagram of the select circuit (10) of FIG. 1.

Next, the operation will be explained. If the memory array (3b) is the active region, select signal SLa="Ll, 5
Lb=aH#, 5LC=#a″, 5Ld=#L#, through the mesh array (3b) and bit line (2),
Two rows of sense amplifiers (1), upper and lower, are connected. Word 11WL2>f″El” and signal Sr3 becomes 1P
, @ No. Sp becomes “L#” and the memory array (3b)
The upper and lower sense amplifiers (1) operate. Conventional 7th
In the case of the figure, the amplification time was tI, but since the capacity is doubled, the speed is about half of t1, as shown in t2 in FIG. The time difference t between BL-, which is the closest wiring from the sense amplifier drive signal source, and BLn, which is farthest, is the same, but the amplification capacity is doubled, so access is faster and the sense margin is also higher. , 2 memory array (3θ) is the active region, the sense amplifiers in the two columns above and below are operated.

In this way, the rows of sense amplifiers are connected to the memory array (3).
Because the upper and lower blocks are shared and switched, there is no increase in area.

[Effect of the Invention J As described above, according to the present invention, sense amplifiers are provided at both ends of the bit line, and amplification is performed by the sense amplifiers at both ends of the bit line, so that high-speed access operation and , the sense margin is improved, and since the sense amplifiers are shared by the memory array blocks, there is no increase in area.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the overall configuration of a sense amplifier that is an embodiment of the present invention, Figure 2 is an operating waveform diagram of the circuit in Figure 1, and Figure 3 is a circuit diagram of the select circuit in Figure 1. , 4th
The figure is a block diagram showing the overall configuration of a conventional sense amplifier, Figure 5 is a circuit diagram of the sense amplifier circuit in Figure 4,
This figure is a circuit diagram of the memory cell of FIG. 4, and FIG. 7 is an operating waveform diagram of the circuit of FIG. 4. In the figure, (1) is the sense amplifier, (2) is the bit line, (38) to (3c) are the memory array, and (4) is the P
Channel MO8) transistor, (5) ~ channel A/M
O8) a transistor, (6) a power supply voltage, (7) a ground, and (lO) a select circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Masuo Daiiwa Figure 2 Figure 3 Figure 7 Procedural amendment (,e) July-3, 1991

Claims (1)

[Claims] A memory array including memory cells arranged orthogonally and arranged in a lattice at the intersections of word lines and bit lines each consisting of a single signal line;
In a sense amplifier that transmits cell data to a bit line and amplifies the data, sense amplifiers are provided at both ends of the bit line pair, the sense amplifiers at both ends amplify the bit line pair, and the sense amplifier - A sense amplifier characterized in that it is possible to amplify by switching both bit line pairs of memory array blocks on both sides of the amplifier.