JPH04205445A - Memory access device - Google Patents

Abstract

PURPOSE:To attain rapid access and the simplification and miniaturization of constitution by setting up the row addresses of a depth buffer similarly to that of a display memory and setting up its column addresses differently from that of the display memory. CONSTITUTION:This memory access device includes the 1st page changing processing part 5 for supplying a row address to the display memory 2 and the depth buffer 3 based upon plotting start point data and supplying also a RAS signal to the memory 2 and the buffer 3 to execute page changing processing and the 2nd page changing processing part 6 for supplying a new row address and a new RAS signal to the memory 2 and the buffer 3 to execute page changing processing when a picture element generated from a DDA 1 is changed from a certain page to another page and stopping the generation of picture elements from the DDA 1 only for a time necessary for the page changing processing. Consequently rapid access to any of the display memory 2 and the depth buffer 3 is attained without requiring an intermediate buffer.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a memory access method and device thereof, and more specifically, to perform high-speed memory access to a memory device with a long access time. The present invention relates to a novel method and apparatus for the same.

<Prior art> Graphics display devices have traditionally used high resolution,
There is a strong demand for simultaneous multi-color display, and in order to satisfy these demands and reduce the overall size and cost of the graphics display device, display memory has been developed to be dynamic.
It consists of a random access memory (hereinafter abbreviated as DRAM) or a video RAM (hereinafter abbreviated as VRAM) that writes pixel data using random access and reads multiple pixels simultaneously using sequential access. There is.

Then, a linear generator (hereinafter referred to as
As shown in FIG. 11, as a configuration for writing pixels sequentially generated by a DDA (referred to as DDA) into a display memory, pixels sequentially output from a DDA (61) are written to a dual-plane buffer (62). Write to one plane of the display memory (6
3) is adopted. In addition, the buffer (
62) and the display memory (63), a selector, a buffer for holding read pixels, and a bidirectional buffer are provided as necessary.

If such a configuration is adopted, by setting the capacity of each plane of the buffer (62) appropriately, even if the pixel generation speed by the linear generator is significantly faster than the pixel writing speed to the display memory, the display memory against, 1
By making the writing speed converted per pixel approximately the same as the pixel generation speed by the linear generator, it is possible to write pixels into the display memory without interrupting the operation of the linear generator.

<Problem to be solved by the invention> By adopting the above configuration, a high-speed display memory (63
), it is assumed that the number of memory devices making up the display memory (63) is sufficiently large. That is, since the display memory (B3) has conventionally been constructed using 256-bit memory devices, the required number of memory devices is significantly large (for example, to construct a display memory with a display area of 1280 x 1024 pixels). In this case, five memory devices are required per brane), and the bit width that can be accessed to the display memory at the same time can be increased.

However, in an attempt to reduce the mounting area of the display memory (83), the required number of memory devices is reduced by using large capacity memory devices (for example, 1
With an M-bit memory device, 1280X1
One plane of 024 pixel display memory is divided into two memories.
This can be done with your device. ). However, in this case, as the number of memory devices required decreases, the bit width that can be accessed simultaneously becomes smaller, so the pixel writing speed per pixel decreases, and the display speed of the graphics display device decreases. There is an inconvenience that the value decreases.

Further, for example, in a three-dimensional graphics display device, the bit width of data sent from the DDA (61) to the display memory (63) is, for example, 24-bit frame data, 24-bit depth data, 4-bit data, etc. The total overlay is 52 bits, and if data for n pixels and m pixels are to be read and written simultaneously in the vertical and horizontal directions, a total of 52×n×m data input/output ports are required.

Therefore, the buffer in the above dual plane configuration (
62) using a gate array, approximately 10 to 30 gate arrays each having a size of about 100 pins would be required, which would complicate the overall configuration.

In addition, the inventor of the present invention has also proposed the page mode supported by DRAM%VRAM (within the same page, the row address is set only once, and then the column
We considered speeding up the memory access itself by using a mode in which memory access can be performed by changing the address, and omitting the buffer (62).

In this case, as long as the writing of pixels within the same page is continuous, it is possible to achieve a faster write speed per pixel, and since no buffer is required, the configuration can be simplified and downsized. can be achieved. However, when writing a pixel from one page to another, it is necessary to set a row address. We found that it was not possible to achieve a significant speedup.

Furthermore, in a three-dimensional graphics display device, a depth buffer is provided in order to apply a depth buffer contention algorithm. Otherwise, the depth data is read from the depth buffer, the depth data generated by the DDA is compared with the read depth data, and the depth data selected based on the result of the comparison is sent to the depth buffer. It has also been found that simply operating the depth buffer in page mode cannot achieve a sufficient speed-up of memory access, since it is necessary to write .

<Purpose of the Invention: This invention has been made in view of the above problems,
A novel device that can achieve high-speed access, simplification and miniaturization of the configuration when writing pixels sequentially output from the DDA based on the depth buffer algorithm while the display memory and depth buffer are operating in page mode. The purpose of the present invention is to provide a memory access device that is easy to use.

Means for Solving the Problems> To achieve the above object, the memory access device of the first invention operates in page mode on three-dimensional output data from a linear generator configured with hardware. A memory access device for controlling writing to the display memory based on a depth buffer algorithm, the depth buffer being capable of random input and serial output, The row 9 address of the depth middle buffer is set to be the same as the display memory, and the column address of the depth buffer is set to be different from the display memory.

In the memory access device of the second invention, the display memory has a plurality of column addresses in the scan line direction and fewer addresses in the direction perpendicular to the scan line than in the scan line direction. It has a plurality of addresses, and the column φ address of the depth buffer has one address in the direction perpendicular to the scan line and a plurality of addresses in the direction of the scan line.

The memory access device of the third invention includes a linear generator assigned to an even-numbered scan line and a linear generator assigned to an odd-numbered scan line, and also configures a display memory. multiple memory
A large number of devices are arranged in the direction of the scan line and assigned to each linear generator, and a plurality of memory devices constituting the depth buffer are arranged in a large number in the direction perpendicular to the scan line and assigned to each linear generator. is assigned to.

Function> The memory access device of the first invention supplies three-dimensional output data from a linear generator configured with hardware to a display memory and a depth buffer operating in page mode, and When controlling writing to display memory based on a buffer algorithm, it is not enough for the display memory to simply store output data from a linear generator at high speed; read transfer for display by a CRT display device is not sufficient. By setting the page address so that the number does not increase too much,
Fast writing of output data from linear generator and C
High-speed display can be achieved by suppressing an increase in the number of read transfers for display by the RT display device.

Also, regarding the depth buffer, read transfer is not necessary for display on a CRT display device, but
Since a read transfer is required each time a line segment begins to be drawn or a scan line changes, column addresses are set to achieve high-speed write and read transfers based on the output data from the line generator. By doing so, high-speed processing of the depth buffer algorithm can be achieved. As a result, it is possible to significantly suppress a decrease in the display speed of the CRT display device, and to achieve high-speed writing of three-dimensional data sequentially output from the linear generator.

With the memory access device of the second invention, when reading and transferring the contents of the display memory for display on a CRT display device, the number of read transfers per scan line is reduced to maintain a high display speed. Moreover, the writing speed to the display memory can also be maintained quite high when drawing a line segment inclined with respect to the scan line. When processing based on the depth buffer algorithm, there is no problem even if the number of read transfers per scan line is large, so one column per scan line is By providing an address, it is possible to increase the processing speed of the depth buffer algorithm when drawing a line segment that is inclined with respect to the scan line.

With the memory access device of the third invention, access speed can be increased by preventing the same device in memory from being accessed continuously, and read transfer for display on a CRT display device is possible. In this case, data can be simultaneously read out from a plurality of memory devices arranged in the scan line direction, so that the readout speed per pixel can be approximately equal to the video rate.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of the memory access device of the present invention, which receives and receives end point data, gradient data, length data, etc. of drawn line segments from a higher-level processor (not shown). A DDA (1) that sequentially generates pixels on a drawn line segment, a display memory (2) that receives the pixels sequentially generated by DDA (1) and stores them at the corresponding address, and a depth buffer. a depth buffer (3) for storing depth values for the algorithm;
The above receiver is the initial setting for interpolation calculation based on the input data, for example, the data holding section corresponding to the drawing start point data (
Initial stage for setting the cumulative addition value holding unit) (la), setting the gradient data to the corresponding data holding unit (gradient holding unit) (lb), setting the length data to the DDA counter (lc), etc. The setting unit (4) supplies a row address (page address) to the display memory (2) and depth buffer (3) based on the drawing start point data, and also supplies a row address strobe signal (hereinafter referred to as the RAS signal) to the display memory (2) and depth buffer (3). a first page change processing unit (5) that performs page change processing by supplying D D A
1) When a pixel generated by 1) changes from one page to another, a new row address and
An address strobe signal is supplied to the display memory C) and the depth buffer (3) to perform page change processing, and D D is used for the time necessary for page change processing.
It has a second page change processing unit (6) that stops pixel generation by A (1). Furthermore, (7) is DDA
This is a write control section that outputs a column address strobe signal (hereinafter abbreviated as CAS signal) in synchronization with pixel generation according to (1), and supplies it to the display memory (2) and depth buffer (3).

Figure 2 shows the display memory (2) and depth buffer (3).
) is a diagram showing an example of page address allocation for a case where the resolution is 1024 x 1280 pixels.

That is, 512 pixels in the scan line direction,
The page area is an area of 8 pixels in the direction perpendicular to the line,
Three pages are allocated in the scan line direction and 128 pages are allocated in the direction perpendicular to the scan line. therefore,
X, y address xO.

The relationship between xl...xlO, yO, yl...y9 and page addresses rO, rl...r8 is x10.
x9. y9. y 8゜y 7. y6. y5.
y4. y3 corresponds to each bit rO, r1...r8 of the page address, respectively. However, a smaller subscript indicates the least significant bit, and a larger subscript indicates the most significant bit.

FIG. 3 is a diagram showing an example of column address assignment in each page area of the display memory. The column area is an area of 4 pixels in the scan line direction and 2 pixels in the direction perpendicular to the scan line. 12 in the line direction
8, allocate 4 columns in the direction perpendicular to the scan line.

Therefore, x2. x 3. x 4. x 5. x 8
．． x7. x8. y1 and y2 are each bit cO of the column address.

cl...corresponds to C8.

FIG. 4 is a diagram showing the allocation of VRAMs constituting one brain of the display memory to DDAs, in which VRAM0. VRAMI, VRAM2. VRAM
3 and V for D D A (1o) assigned to the odd scan line.
RAM4.

VRAM5. VRAM8. Allocate VRAM7. In other words, one brain can be constructed by using two 1M-bit VRAMs, but in order to increase the number of VRAMs that can be accessed simultaneously, the input bits of each VRAM are assigned to different planes, and one brain is divided into eight It is composed of VRAM.

FIG. 5 is a diagram showing the allocation of VRAM to two column areas adjacent in the direction perpendicular to the scan line, with VRAM0. VRA old.

VRAM2 and VRAMI are allocated in this order, and VI?
AM7. Vl? AM4. VRAM5. VRAM6 is assigned to this group, and the other VRAM2. VRAM3. VR
AM0. In addition to allocating VRAMI to this group, VRAM5, corresponding to odd-numbered scan lines,
VRAM8, VRAM7, and VRAM4 are allocated in this order.

Note that yO is used to select even channels and odd channels, xO and xi are used to select four pixels in the scan line direction, and the VRAM to be selected changes depending on yo and yt.

FIG. 6 is a diagram showing an example of column address assignment in each page area of the depth buffer.
A column area is an area of 1 pixel in the line direction and 8 pixels in the direction perpendicular to the scan line, and 512 columns are allocated in the scan line direction and 1 column is allocated in the direction perpendicular to the scan line. Therefore, x O, x 1. x
2. x 3. x 4+x 5. xB, x7. xB is each column address p)cO, cl...C8
corresponds to

Figure 7 shows the VR that constitutes one brain of the depth buffer.
FIG. 3 is a diagram illustrating the assignment of AM to DDA, with D D A (
VRAM0. VRAM2. VRAM4.
While VRAM6 is allocated, r VI? AMl, VI? AM3, VJ?
A) 15, allocate VRAM7.

FIG. 8 is a diagram showing VRAM allocation to two column areas adjacent in the scan line direction, with VRAM0 and VRAM corresponding to even-numbered column areas.
l, VRAM2, VRAM3, VRA
M4, VRAM5, VRAM6, VRAM
7 are assigned in this order, and the corresponding VRAM 4. Vl? AM5. VRAM6
．． VRAM7. VRAM0. VRAM1. VI? AM2
．． VJ? Assign AM3 to this type.

Note that VO, yl, and y2 are used to select eight pixels in a direction perpendicular to the scan line, and the VRAM to be selected changes depending on XO.

The operation of the above memory access device will be explained with reference to the timing chart shown in FIG. Note that the timing chart in FIG. 9 is based on the timing chart for pixels PO to
Compatible with P9 drawing.

After the read transfer for display by the CRT display device is performed, the RAS signal for the depth buffer (3) (see FIG. 9(A)) is set to high level, and
Display memory (2) -VRAM0. VRAM1. VRA
M2. VRAM3 and depth buffer y (3)
(1) VRAM0, VRAM4. VRAM2. V
I? AM6 I: CAS signal for ((3) (H
) (1) (J) (K) (L) (M) (N)
) to a high level. During this time, the RAS signal for the display memory (see (B) in the same figure) continues to be held at a high level, the predetermined row address (see (C) in the same figure) continues to be output, and the depth data output and depth data are output. Serial data output of buffer (3) (see (D) in the same figure), comparator output based on the depth buffer algorithm (see (E) in the same figure), depth value latch data output, brightness value data output, and inside page As for the address (see (F) in the figure), the pixel PO continues to be output.

Next, when the page mode start is instructed and the RAS signal for the depth buffer (3) (see Figure 9 (A)) and the RAS signal for the display memory (see Figure 9 (B)) go low level. , the page change process has been completed, and after that, pixel data is sequentially output by operating DDA(le). Therefore, the same figure (
D), sequentially the depth values and the corresponding read values PI, P2...P9 from the depth buffer (3)
is output, as shown in (E) in the same figure, the comparison results are sequentially output with a delay of a predetermined time by the comparator, and after a further delay of a predetermined time, as shown in (F) in the same figure, the depth value latch data is output, Luminance value data and in-page address are output.

Therefore, pixels PO, P4 . Corresponding to P8, the CAS signal for VlrAMO of the display memory (2) is set to low level, and the pixel P1. P5. In response to P9, set the CAS signal for VRAMI of display memory (2) to low level,
Display memo 1.corresponding to pixels P2 and P6. I C2) (D
For VRAM2 (7) Set the CAS signal to low level and set pixel P3. VRA of display memory (2) corresponding to P7
By setting the CAS signal for Ma to a low level, each pixel PO, Pi, . . . P9 can be sequentially written into the display memory (2). In addition, pixels PO, P2 . P4. P6
．． VRAM0 of depth buffer (3) corresponding to P8
The CAS signal for pixel P1. is set to low level. P 3
．． P5. P7. In response to P9, set the CAS signal for VRAM4 of the depth buffer (3) to low level,
Depth buffer (3) and others (7) VRAM2,
VI? By continuing to hold the CAS signal for AM6 at a high level, the depth value selected based on the comparison result can be written to the depth buffer (3).

As is clear from the above description, three-dimensional data can be written at high speed without interrupting the pixel data generation operation by the DDA.

Note that when performing a read transfer, the read transfer can be easily performed by setting the RAS signal for the depth buffer to a low level and then setting the CAS signals for all VRAMs to a low level.

It should be noted that the present invention is not limited to the above-described embodiments, and can be applied to graphics display devices with different resolutions, for example, and can also be applied to memory devices with capacities other than 1 Mbit. In addition, it is possible to change the page address, column address, and arrangement of each memory device, and it is also possible to make various design changes without changing the gist of the present invention. .

<Effects of the Invention> As described above, the first invention sets the row address and column address of the display memory in accordance with data writing and read transfer for display, and sets the column address of the depth buffer in accordance with the read transfer for data writing and display. - Since it is set in accordance with the buffer algorithm, it has the unique effect of achieving high-speed memory access that would otherwise require an intermediate buffer for both display memory and depth buffer.

The second invention also has the same unique effects as the first invention.

The third invention is capable of increasing access speed by preventing the same memory device from being accessed continuously, and moreover, when performing read transfer for display on a CRT display device, scanning and It has the unique effect of simultaneously reading data from a plurality of memory devices lined up in the line direction and making the readout speed per pixel almost equal to the video rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the memory access device of the present invention, FIG. 2 is a diagram showing an example of page address assignment, and FIG. 3 is a diagram showing column address assignment in the page area of the display memory. A diagram showing an example, FIG. 4 is a diagram showing the allocation of VRAM constituting one brain of display memory to DDA, and FIG.
Figure 6 shows an example of column address assignment in each page area of the depth buffer; Figure 7 shows an example of column address assignment in each page area of the depth buffer;
FIG. 8 is a diagram showing the allocation of VRAM to DDA constituting one brain of the buffer, FIG. 8 is a diagram showing the allocation of VRAM to two column areas adjacent in the scan line direction, and FIG. 9 is a diagram showing the memory access operation. FIG. 1O is a diagram showing a drawing example; FIG. 11 is a schematic block diagram showing a conventional example of a memory access device. (1) (le) (1o) ・-D D A, (2)
- Display memory, (3) Depth buffer, (VRAMO) (Old VRA)... (VRAM7)
...VRAM patent applicant Daikin Industries, Ltd. Agent Patent attorney Tomoji Tsugawa Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. Linear generator (1) (1e
) (1o) into a display memory (2) operating in page mode and a depth buffer (3).
) and controls writing to the display memory (2) based on a depth buffer algorithm, the depth buffer (3) being capable of random input and serial output; The row address of depth buffer (3) is set to be the same as display memory (2), and the column address of depth buffer (3) is set to be different from display memory (2). A memory access device characterized by: 2. The column address of the display memory (2) has a plurality of addresses in the scan line direction, and
It has fewer addresses in the direction perpendicular to the scan line than in the scan line direction, and the depth
Claim 1, wherein the column address of the buffer (3) has one address in the direction perpendicular to the scan line and a plurality of addresses in the direction of the scan line. memory access device. 3. It has a linear generator (1e) assigned to an even-numbered scan line and a linear generator (1o) assigned to an odd-numbered scan line, and
A plurality of memory devices (
VRAM0) (VRAM1)... (VRAM7) are allocated to each linear generator in a large number lined up in the scan line direction, and a plurality of memory devices (VRAM0) ( VR
3. The memory access device according to claim 2, wherein a large number of AM1)...(VRAM7) are allocated to each linear generator in a state perpendicular to the scan line.