JPH04200133A - Control data generating device - Google Patents

Abstract

PURPOSE:To generate a control data without giving a limit to data processing capacity by generating a data generating timing of a data generating circuit asynchronously with an output timing of a timing generating circuit. CONSTITUTION:A data generating circuit 1 receives device state information 10 to monitor a state of an external device and sends a control data 15 corresponding to the state to a data transfer control circuit 3 and sends a data transmission end signal 11 to a timing generating circuit 2 at the end of output. The timing generating circuit 2 is set by the data transmission end signal 19 and sends a data transfer enable signal 13 to a data transfer control circuit 3 and a write address counter 5. A storage circuit 6 writes the control data 15 to an address commanded by a write address signal 16 and reads a content of the address pointed out by a read address signal 17 sent from the read address counter 5 and outputs the result as an output data 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized for generating control data in data communications.

The present invention relates to a control data generation device that can generate control data using a small-scale data generation circuit without limiting data processing capacity.

〔overview〕

The present invention provides a control data generation device that inputs device status information from the outside and generates and outputs control data according to a timing signal from the outside, in which the data generation timing of the data generation circuit is asynchronous to the output timing of the timing generation circuit. By generating control data, the data generation circuit can be configured on a small scale and control data can be generated without limiting the data processing capacity.

[Conventional technology]

Conventionally, this type of data generation device is initialized by a read-side timing signal 36 and outputs a data transmission timing signal 30 and an address control signal 3, as shown in FIG.
2, a data generation circuit 20 that receives device status information 29 and generates control data 31 at a timing instructed by a data transmission timing signal 30 from the timing generation circuit 22; A write address counter 21 counts up and outputs a write address signal to designate a write address at a timing instructed by an address control signal 32 from the address control signal 32, and a write address counter 21 counts up and outputs a write address signal to specify a write address at a timing instructed by an address control signal 32 from an external address control signal 32. The read address counter 23 specifies the read address by 34, and the control data 31 from the data generation circuit 20 is sent to the address specified by the write address signal 33 from the write address counter 21.
, and a storage circuit 24 for reading out the contents of the address specified by the read address signal 34 from the read address counter 23, and generates control data for data communication.

[Problem to be solved by the invention]

In the conventional control data generation device described above, the timing on the read side must be constantly monitored in order to generate data at the timing instructed by the timing generation circuit, so the configuration of the data generation circuit becomes complicated and the scale increases. There was a downside to getting bigger.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and provides a device that allows a data generation circuit to be configured simply and on a small scale.

[Means to solve the problem]

The present invention includes a data generation circuit that generates control data by inputting device status information from the outside, and a read-side timing signal that is initialized to generate a data transmission timing signal to the data generation circuit and an address control signal. A timing generation circuit that generates a write address, a write address counter that counts up according to the timing instructed by an address control signal from this timing generation circuit, and outputs a write address signal to specify a write address, and a write address counter that specifies a write address by outputting a write address signal. A read address counter that counts up according to a read-side timing signal and generates a read address signal to specify a read address; and a read address counter that writes control data from the data generation circuit to the address specified by the write address counter, and outputs the read address. A control data generation device comprising a memory circuit that outputs the contents of an address specified by a counter as output data,
Data transfer control that temporarily stores input data sent by the data generation circuit and sends the temporarily stored input data to the storage device as control data at a timing specified by a data transfer permission signal sent by the timing generation circuit. It is characterized by being equipped with a circuit.

The data generation circuit includes means for generating a data transmission end signal at the end of input data transmission, and the write address counter is counted up at a designated time;
means for sending a count end signal when the count value reaches a preset value, and sending a write address signal for specifying a write address to the storage circuit; the write address counter includes means for receiving a data transmission end signal and a count end signal from the write address counter and transmitting a data transfer permission signal, wherein the write address counter receives a data transfer permission signal sent from the timing generation circuit. It is desirable to include a means for counting up.

[Effect]

The data generation circuit inputs device status information from the outside, monitors the status of the external device, sends control data corresponding to the status to the data transfer control circuit, and sends a data transmission end signal to the timing generation circuit when the output ends. Send. The timing generation circuit is set by this data transmission end signal and sends a data transfer permission signal to the data transfer control circuit and write address counter.

The write address counter that receives the data transfer permission signal creates a write address signal and sends it to the storage circuit.
The data transfer control circuit sends the temporarily stored input data to the storage circuit as control data.

The storage circuit writes control data to the address specified by the write address signal, and reads the contents of the address specified by the read address signal sent from the read address counter and outputs it as output data.

In this way, by generating the data generation timing of the data generation circuit asynchronously with the timing generated by the timing generation circuit, the scale of the data generation circuit can be reduced, and control data can be processed without limiting the data processing capacity. can occur.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention includes a data generation circuit 1 that inputs device status information 10 from the outside and generates input data 12, a write address counter 4 that outputs a write address signal 16 to designate a write address, and a write address counter 4 that outputs a write address signal 16 to specify a write address. The input data from the data generation circuit 1 is counted up by the read-side timing signal 19, and the read address counter 5 generates the read address signal 17 to specify the read address, and the write address counter 4 outputs the input data from the data generation circuit 1 to the address specified. A memory circuit 6 is provided for writing as control data and outputting the contents of the address designated by the read address counter 5 as output data 18. Furthermore, as a feature of the present invention, the input data 12 sent out by the data generation circuit 1 is temporarily stored. Input data 12 temporarily stored at a timing specified by a data transfer permission signal 13 sent by the timing generation circuit 2
The data transfer control circuit 3 includes a data transfer control circuit 3 that sends the data as control data 15 to the storage device 6, the data generation circuit 1 includes means for generating a data transmission end signal 11 when input data transmission is completed, and the write address counter 4 receives an instruction from the write address counter 4. It includes means for counting up at a preset time and sending out a count end signal 14 when the count value reaches a preset value, and transmits the data transmission end signal 11 from the data generation circuit 1 and the write address to the timing generation circuit 2. The counter 4 includes means for receiving an IQ completion signal 14 and transmitting a data transfer permission signal 13.

The write address counter 4 includes means for counting up at the time specified by the data transfer permission signal 13 sent by the timing generation circuit 2.

The data generation circuit 1 inputs device status information 10 from the outside, monitors the status of the external device, generates and outputs input data 12 corresponding to the status, and generates a data transmission end signal 11 after the output is completed.

The timing generation circuit 2 is set by the data transmission end signal 11, reset by the count end signal 14 from the write address counter 4, and outputs the data transfer permission signal 13. This is a circuit that can be constructed from flip-flops and the like.

Write address counter 4 receives data transfer permission signal 13
This circuit can be configured with a counter that counts when the signal is "H" and is initialized when the signal is "L", and generates and outputs the write address signal 16 for the memory circuit 6.

The data transfer control circuit 3 is configured so that the data transfer permission signal 13 is “L”.
The input data 12 is temporarily stored in the "H" state, and the stored data is output as the control data 15 when it is "H". For example, it is a circuit that can be configured with a shift register or the like.

The read address counter 5 counts up in response to a read side timing signal 19 instructed from the outside, and generates and outputs a read address signal 17 for the memory circuit 6. The memory circuit 6 writes control data 15 to the address specified by the write address signal 16, reads out the contents of the address specified by the read address signal 17, and outputs it as output data 18.

〔Effect of the invention〕

As explained above, according to the present invention, by generating the data generation timing of the data generation circuit asynchronously with the output timing of the timing generation circuit, the scale of the data generation circuit can be reduced, and the data processing capacity can be reduced. This has the advantage that control data can be generated without any restrictions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional example. 1.20...Data generation circuit, 2.22...Timing generation circuit, 3...Data transfer control circuit, 4.21
...Write address counter, 5.23...Read address counter, 6.24...Storage circuit, 10
．． 29...Device status information, 11...Data transmission end signal, 12...Input data, 13...Data transfer permission signal, 14...Count end signal, 15.31...
・Control data, 16.33...Write address signal, 17.34...Read t address signal, 18.3゛5...Output data, 19.36...Read side timing signal, 30...・Data transmission timing signal, 3
2...Address control signal.

Claims (1)

[Claims] 1. A data generation circuit that inputs device status information from the outside and generates control data; and a data generation circuit that is initialized by a read-side timing signal and generates a data transmission timing signal to the data generation circuit. , a timing generation circuit that generates an address control signal; a write address counter that counts up according to the timing instructed by the address control signal from the timing generation circuit and outputs a write address signal to specify a write address; a read address counter that counts up according to a read side timing signal instructed by a read address signal and specifies a read address by generating a read address signal; and a read address counter that writes control data from the data generation circuit to an address specified by the write address counter. ,
A control data generation device comprising a storage circuit that outputs the contents of an address specified by the read address counter as output data, wherein the input data sent out by the data generation circuit is temporarily stored, and the timing generation circuit sends out the input data. A control data generation device comprising a data transfer control circuit that sends the temporarily stored input data as control data to the storage device at a timing specified by a data transfer permission signal. 2. The data generation circuit includes means for generating a data transmission end signal when input data transmission is completed, and the write address counter is counted up at a specified time and the count value reaches a preset value. the timing generating circuit includes means for transmitting a count end signal and a write address signal for specifying a write address to the storage circuit; 2. The control data generation device according to claim 1, further comprising means for receiving a count end signal and transmitting a data transfer permission signal. 3. The control data generation device according to claim 1, wherein the write address counter includes means for counting up at a time specified in a data transfer permission signal sent by the timing generation circuit.