JPH04215317A - phase locked circuit - Google Patents

Abstract

PURPOSE:To reduce dispersion in the phase synchronization characteristic for each product by suppressing fluctuation in a natural frequency and in an attenuation against inevitable fluctuation in a conversion coefficient of a current- frequency conversion circuit caused by manufacture tolerance in the semiconductor phase synchronization circuit. CONSTITUTION:A charge pump 50 of a phase synchronization circuit is provided with a proportional charge current source 56 and a proportional discharge current source 58 supplying a charge discharge current IA proportional to a conversion current (output current) of a V-I conversion circuit 24 to a loop filter 30 through a feedback loop. A P-channel MOSFET is employed for the proportional charge current source 56 and an N-channel MOSFET is adopted for the proportional discharge current source 58. The charge pump circuit 50 is a current mirror circuit in which a current mirror circuit 42b of a V-I conversion circuit 42 is used for a pre-stage.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a phase synchronization circuit that generates a clock that synchronizes and follows the phase of an input signal.
The present invention relates to a phase locked circuit applicable to bit recording.

0002

2. Description of the Related Art Conventionally, the configuration of a phase synchronized circuit widely used in data separators, frequency multipliers, etc. of magnetic disk drives, etc. is as shown in FIG. 40 oscillation output VO
The phase of UT (oscillation frequency fOSC) is compared, and a delayed phase difference detection signal Q1 and an advanced phase difference detection signal Q2 are generated.
and a delayed phase difference detection signal Q1.
and a charge pump 20 that supplies charging and discharging current to the capacitor CF of the loop filter 30 based on the leading phase difference detection signal Q2, and a low-pass filter that constitutes a lag lead filter equivalent to the charge pump 20 in terms of circuit correlation. (LPF), and a voltage controlled oscillator (VCO) 40 that uses the filter output voltage VF as a control input and converts it into an oscillation output VOUT having an oscillation frequency fOSC according to the value. The voltage controlled oscillator 40 is a voltage-current conversion circuit (hereinafter referred to as V/I
42 (hereinafter referred to as a conversion circuit) and a current-frequency conversion circuit (hereinafter referred to as I
/F conversion circuit) 44. In addition,
The oscillation frequency fOSC of the voltage controlled oscillator 40 may be input to the phase comparator 10 via a predetermined frequency divider.

The phase comparator 10 is a digital phase comparator, and is composed of, for example, a pair of D flip-flops and a logic gate. As shown in FIG. 8, the charge pump 20 includes an insulated gate field effect transistor (hereinafter referred to as MOSFET) 22 for charging, which is turned on when the delayed phase difference detection signal Q1 is at a low level, a constant current source 24 for charging, This is a series circuit consisting of a discharging MOSFET 26 and a discharging constant current source 28, which are turned on when the leading phase difference detection signal Q2 is at a high level. The constant current source 24 for charging and the constant current source 28 for discharging are each constructed from a current mirror circuit as shown in FIG. equal to the value of the determined mirror current i1. As shown in FIG. 10, the V/I conversion circuit 42 converts the filter output voltage VF
It is comprised of a voltage-current converter 42a that varies the value of input current i2 according to the value of , and a current mirror circuit 42b that extracts the input current i2 as output current i2. Voltage-current converter 4 of this V/I converter circuit 42
2a, the converted current i2 is given by the following equation.

[0004] However, RY is the conversion current value setting resistor of the operational amplifier OP,
VDD is a power supply potential.

[0005]

SUMMARY OF THE INVENTION However, the phase locked circuit having the above-mentioned configuration has the following problems.

(2) As in the case where a phase-locked circuit is constructed as a semiconductor integrated circuit, manufacturing variations occur in the characteristics of each transistor that constitutes the phase-locked circuit. Therefore, the current-frequency conversion coefficient k of the I/F conversion circuit 44 inevitably varies from product to product. That is, in two phase-locked circuits with a conversion coefficient k and a conversion coefficient k+Δk, when the input signal SIN and the oscillation frequency fOSC of the VCO are synchronized, the respective I-F conversion circuits 44
The input currents of are i2 and i2 +Δi2, but since the charge pump 20 charges and discharges the loop filter 30 by constant current drive using the constant current sources 24 and 26, the closed loop gain G of the phase locked circuit is inevitably It varies from product to product. This variation in gain G also leads to variation in the natural frequency ωn and damping rate ζ that characterize the phase-locked circuit, and has therefore been a cause of a decrease in the yield of semiconductor phase-locked circuits.

[0007] On the other hand, the values of the electrical elements of each circuit are optimized in order to obtain phase synchronization with respect to the input signal SIN of a specific frequency. For example, charge pump 20
The value of the charging/discharging current i1, the time constant of the loop filter 30, and the input voltage versus output frequency characteristics of the VCO 40. Therefore, when the frequency of the input signal SIN is switched to a different frequency, the frequency components of jitter will naturally change, and at the time of this change, it is necessary to make adjustments to optimize the values of the above-mentioned circuit elements again. . Specifically, when clocks with different frequencies are switched and applied as input signals, it is necessary to provide multiple loop filters with different time constants and switch to the optimal loop filter in synchronization with the frequency switching. was there. That is, it is necessary to provide uniquely different loop filters for input signals of different frequencies, so for example, when realizing zone bit recording in a hard disk system, it is necessary to use multiple loop filters. is required, and the circuit configuration of the phase-locked circuit becomes complicated. This forces calculations for circuit constant optimization for each frequency of the input signal.

Therefore, the present invention solves the above problems, and the first problem is to reduce the natural frequency and damping for fluctuations in the current-frequency conversion coefficient that inevitably occur due to manufacturing variations. The second problem is to realize a phase-locked circuit that can suppress rate fluctuations, and the second problem is based on the first problem, but with a single loop filter.
It is an object of the present invention to provide a phase synchronization circuit that can obtain phase synchronization characteristics that can correspond to input signals after the change even when input signals of different frequencies are switched and applied.

[0009]

[Means for Solving the Problems] A phase-locked circuit according to the present invention has the same configuration as a general phase-locked circuit, including a phase comparison means, a charge pump means, a loop filter means, a voltage
It has current conversion means and current-frequency conversion means. The phase comparison means compares the phase of the first input signal, which is the reference signal, and the phase of the second input signal based on the oscillation output from the current-frequency conversion means, and outputs a phase difference detection signal. The charge pump means sends a drive current to charge or discharge the loop filter means based on the phase difference detection signal. The voltage-to-current converting means has a converted current value setting resistor, and depending on its value produces a converted current that is substantially proportional to the difference between the output voltage of the loop filter means and the power supply voltage. The current-frequency conversion means provides an oscillation output with an oscillation frequency substantially proportional to the value of the converted current as a source of a clock signal. The voltage-current conversion means and the current-frequency conversion means constitute voltage-controlled oscillation means.

In such a configuration, in order to solve the first problem, the first means taken by the present invention is to use a constant current source as the current source of the drive current in the charge pump means. The present invention is characterized in that a feedback loop is used as a proportional current source to flow a current proportional to the converted current of the voltage-current converting means. The specific configuration of the phase comparison means includes a first flip-flop that receives one of the first input signal and the second input signal as a clock input and outputs a delayed phase difference detection signal; A second flip-flop which uses the other of the two input signals as a clock input and outputs a leading phase difference detection signal, and a second flip-flop which has two inputs, a delayed phase difference detection signal and a leading phase difference detection signal, It has a logic circuit that generates a reset signal. Under the configuration of such a phase comparison means, the specific configuration of the proportional current source is proportional charging, in which a charging drive current substantially proportional to the value of the converted current is caused to flow, triggered by the generation of the delayed phase difference detection signal. A current source and a proportional discharge current source are provided to flow a discharge drive current substantially proportional to the value of the converted current upon generation of the leading phase difference detection signal. On the other hand, the specific configuration of the voltage-current conversion means includes a voltage-current converter that generates an input current according to the value of the conversion current setting resistor, and a mirror current that generates a mirror current that is substantially equal to the value of the input current. It has a current mirror circuit that extracts the converted current. The proportional charging current source and the proportional discharging current source can be configured as a current mirror circuit having the current mirror circuit as a front stage.

In order to solve the above second problem, the second means taken by the present invention is to use a first capacitor means interposed between the output terminal and the first power supply voltage as a loop filter means. , the second capacitor means interposed between the output terminal and the second power supply voltage, and the capacitance ratio thereof is changed with the total capacitance of the first and second capacitor means unchanged upon generation of the phase difference detection signal. A configuration having variable capacity ratio control means is adopted. The specific configuration of the first capacitor means includes a fixed connection capacitor means connected between the output terminal and the first power supply voltage, and a fixed connection capacitor means connected between the output terminal and the first or second power supply voltage. switched-connected capacitor means connected between the output terminal and the second power supply voltage; and fixed-connection capacitor means connected between the output terminal and the second or first power supply voltage. and switched-connected capacitor means. On the other hand, the specific configuration of the capacitance ratio variable control means is a switching means for selectively connecting the switch-connected capacitor means. It is desirable that the phase synchronization circuit as described above be configured as a one-chip semiconductor integrated circuit.

0012

[Operation] Even in such a phase-locked circuit, the current-frequency conversion coefficient of the voltage-current conversion means inevitably varies from product to product due to manufacturing variations. However, since the loop filter is charged and discharged with a drive current that is substantially proportional to the conversion current of the voltage-current conversion circuit in the preceding stage,
A closed loop gain G is proportionally connected to the conversion current and the current-frequency conversion coefficient. On the other hand, as is clear from the characteristics of the current-frequency conversion circuit, when the input signal and the oscillation frequency are synchronized, the oscillation frequency is the same in any phase locked circuit. Therefore, even if there are variations in the current-frequency conversion coefficients, no variation in the closed-loop gain G occurs. This means that the natural frequency ωn and the damping rate ζ remain unchanged. Therefore, the phase locking characteristics of each phase locking circuit can be made uniform, contributing to an improvement in the yield in terms of phase locking characteristics. For a particular phase-locked circuit, stability of phase-locked characteristics against temperature changes is guaranteed.

[0013] Furthermore, the configuration of the loop filter means includes first capacitor means interposed between the output terminal and the first power supply voltage, and second capacitor means interposed between the output terminal and the second power supply voltage. In the case of employing a capacitance ratio control means that changes the capacitance ratio of the first and second capacitor means while keeping the total capacitance of the first and second capacitor means unchanged, triggered by the generation of the phase difference detection signal. First, a cap-like voltage change occurs at the output terminal. This corresponds to the voltage drop across the resistor in the conventional loop filter. Thereafter, a relatively slow voltage change occurs at the output terminal due to the drive current of the charge pump. Therefore, a loop filter having no resistance and consisting only of capacitor means is substantially equivalent to the conventional one. By using such a loop filter, the synchronization followability for input signals of different frequencies is improved. In other words, even if the input signal has a different frequency, by switching the value of the conversion current value setting resistor in inverse proportion to the frequency, the oscillation frequency and natural frequency ωn can be made proportional to the frequency of the input signal and automatically follow it. be able to. In other words, the lock-in range can be expanded. On the other hand, the attenuation rate ζ can be kept at a constant value. Therefore, without using a plurality of different loop filters, the present invention can be applied to devices that employ zone bit recording, etc. by simply switching the conversion current value setting resistors of different values.

[0014]

Embodiments Next, embodiments of the present invention will be described based on the accompanying drawings.

(First Embodiment) FIG. 1 is a block diagram showing a first embodiment of a phase locked circuit according to the present invention. The phase locked circuit of this embodiment includes a phase comparator 10, a charge pump 50, a loop filter 30,
The voltage controlled oscillator 40 includes a V/I conversion circuit 42 and an I/F conversion circuit 44. The phase comparator 10 compares the phase of the input signal SIN, which is a reference signal, with the phase of the oscillation frequency fOSC of the voltage controlled oscillator 40, and outputs a delayed phase difference detection signal Q1 and an advanced phase difference detection signal Q2. As shown in Fig. 2, D outputs a delayed phase difference detection signal Q1 using the input signal SIN as a clock input.
A flip-flop 12, a D flip-flop 14 that uses the oscillation output VOUT as a clock input and outputs an advanced phase difference detection signal Q2, and a NAND that uses the detection signals Q and Q2 as two inputs and generates a reset signal for both the D flip-flops 12 and 14. It is composed of a gate 16.

The charge pump 50 includes a charging switching MOSFET 52 that is turned on when the delayed phase difference detection signal Q1 is at a low level, and a discharging switching MOSFET 52 that is turned on when the leading phase difference detection signal Q2 is at a high level.
T54, a proportional charging current source 56 that flows a charging current proportional to the value of the output current of the V/I conversion circuit 42, and a proportional discharge current source that flows a discharge current proportional to the value of the output current of the V/I conversion circuit 42. This is a series circuit consisting of 58 and 58. As shown in FIG. 3, the proportional charging current source 56 in this embodiment is a P-type MOSFET, and the proportional discharging current source 58 is an N-type MOSFET.
It is T.

The loop filter 30, which is a low-pass filter, constitutes a lag lead filter equivalent to the charge pump 50 in terms of circuit correlation, and is composed of a resistor RF and a capacitor CF.
This is an equivalent series circuit with

V/I conversion circuit 42 of voltage controlled oscillator 40
is the input current i2 depending on the value of the filter output voltage VF
It consists of a voltage-current converter 42a that varies the value of , and a current mirror circuit 42b that extracts the input current i2 as an output current i2. This converted current i2
is given by Equation 1 as before.

Transistors Tr2 and Tr3 in the V/I conversion circuit 42 constitute a current mirror circuit, and the current amplification factors of transistors Tr3 and Tr4 are equal. Therefore, the mirror current flowing through transistors Tr3 and Tr4 becomes equal to the input current i2. On the other hand, a MOSFET serving as a current source 56 for proportional charging of the charge pump 50
is gate-controlled by the output signal V1, but its MOSF
The channel widths of the gates of ET and transistor Tr4 are the same, and their characteristics are the same. Therefore, the charging current is equal to the current i2. Similarly, the MOSFET of the proportional discharge current source 58 of the charge pump 50 is gate-controlled by the output signal V2;
The channel widths of the gates of transistor Tr3 and transistor Tr3 are the same, and their characteristics are the same. Therefore, the discharge current is also equal to the current i2. In this embodiment, the shape of each transistor is the same due to the semiconductor manufacturing process, but the channel width of MOSFET 56 is set to n times that of transistor Tr4, and the channel width of MOSFET 58 is set to n times that of transistor Tr3. By doing so, the values of the charging current and the discharging current can be set to n times the value of the output current i2. Therefore, when the charging/discharging current is generally expressed as IA, it is given by:

I/F conversion circuit 44 of voltage controlled oscillator 40
consists of a well-known ring oscillator circuit as shown in FIG.
, a pair of comparators 44b, and a flip-flop circuit 44c consisting of a pair of NOR gates. This I/F conversion circuit 44 charges and discharges a capacitor C0 using a constant current source, creates a sawtooth waveform from the potential using a pair of comparators 44b, and generates a sawtooth waveform in a flip-flop circuit 44.
It is a self-excited oscillator that divides the frequency by 1/2 by 4c and shapes it into a square wave. Transistor Tr5 of constant current source circuit 44a for charging and discharging
Since the characteristics of the transistor Tr4 of the V-I conversion circuit 42 are the same, the charging/discharging current for the capacitor C0 is equal to the current i2. Therefore, I/F conversion circuit 4
As a characteristic of 4, the output frequency fOSC is proportional to the input current i2, so the following equation is derived.

[0021] Here, when formula 1 is substituted into formula 3, the following is obtained. This is the input voltage VF of the VCO versus the oscillation frequency f
Represents the OSC relationship. Normally, the value of the resistor RY is set so that oscillation occurs at a desired center frequency when VF=VDD/2. Transforming Equation 4, we get the voltage-frequency conversion coefficient (ΔfOSC /ΔV
F) is given by the absolute value k/RY. Here, the voltage-frequency conversion coefficient is generally expressed in radians, so
Letting the voltage-frequency conversion coefficient expressed in radians be Kv, it is expressed as follows.

Furthermore, the charge/discharge current (drive current) of the charge pump 50 controlled by the phase difference detection signals Q1 and Q2 of the digital phase comparator 10 is IA, and the conversion including the phase comparator 10 and the charge pump 50 is Coefficient K
As is well known, C is expressed as follows. Substituting Equation 2 into Equation 7 gives the following equation. Therefore, from equations 7 and 8, the closed loop gain G of the phase locked circuit is given by the following equation.

As is well known, the closed-loop transfer function H(S) of a secondary loop using a lag-lead filter as the loop fill 30, as in the phase-locked circuit according to the above embodiment, is expressed as follows. Here, ωn is the natural frequency of the loop, ζ is the damping rate (
damping factor), and each is. These values determine the characteristics of the phase locked circuit. Therefore, even if variations occur in the characteristics of the transistors constituting the phase-locked circuit due to the semiconductor manufacturing process, for example, it is desirable that the values of the natural frequency ωn and the damping rate ζ are not affected.

Here, the conversion coefficient k of the I/F conversion circuit 44
Let us consider the case where the value changes to (k+Δk) due to manufacturing variations. A state in which the oscillation frequency fOSC is synchronized with the same input signal SIN (during lock-in operation)
Then, the oscillation frequency fOSC is the same in both circuits with conversion coefficient k and conversion coefficient (k+Δk). Therefore, from Equation 3, the following holds true. Here, (i2 +Δi2) is the output current of the VI conversion circuit in the I-F conversion circuit 44 of the conversion coefficient (k+Δk). On the other hand, the closed loop gain G(k+Δk) in such a phase-locked circuit is given by Equation 9. Therefore, since the numerator of this equation is zero as is clear from Equation 13, the variation ΔG in the closed-loop gain is ΔG=0. In other words, even if the conversion coefficient k of the I-F conversion circuit 44 changes due to variations in transistor characteristics, the closed loop gain G
No fluctuation occurs.

As a result, as is clear from equations 11 and 12, the natural frequency ωn of the loop does not vary, and the damping rate ζ remains unchanged.

In this way, in this embodiment, the output current (mirror current i) of the V-I conversion circuit 42 is
2) By using current sources 56 and 58 that flow charging and discharging currents proportional to 2), the I-
Even if the conversion coefficient k of the F conversion circuit 44 fluctuates, the fluctuations in the natural frequency ωn and the damping rate ζ can be suppressed. Therefore, the phase locking characteristics of each phase locking circuit can be made uniform,
Contributes to improved yield in terms of phase locking characteristics. Also, of course,
An operational temperature compensation function is also provided.

(Second Embodiment) FIG. 5 is a block diagram showing a second embodiment of the present invention. In this embodiment as well, the V/I conversion circuit 4
Current sources 56 and 58 are provided to flow a charging/discharging current proportional to the output current (converted current) of the second embodiment, and the same effect as in the first embodiment is achieved, but the difference from the first embodiment is that the loop This is due to the configuration of the filter 60. As shown in FIG. 6, the configuration of the loop filter 60 includes a fixedly connected capacitor C1 interposed between the output terminal 62 and the power supply high potential VDD,
A fixedly connected capacitor C2 interposed between the output terminal 62 and the power supply low potential VSS (=0) and a switch SW1
By switching the switch SW2, a switch-connected capacitor C3 is inserted between the output terminal 62 and the power supply high potential VDD or the power supply low potential VSS, and by switching the switch SW2, the capacitor C3 is connected between the output terminal 62 and the power supply high potential VDD or the power supply low potential VSS. It consists of a capacitor C4 with a switched connection.

Here, the switch SW1 is the phase comparator 10.
When a delayed phase difference detection signal Q1 is generated from side a to b
Switch to the side. In addition, switch SW2 is the phase comparator 1
Proceeding from 0, when the phase difference detection signal Q2 is generated, it switches from the d side to the c side. The switches SW1 and SW2 constitute variable capacity ratio control means, as will be described later. When in phase synchronization, the switch SW1 is in contact with the a side, and the switch SW2 is in contact with the b side.

Now, consider the case where the advanced phase difference detection signal Q2 is generated from the phase comparator 10 and SW2 is switched from the d side to the c side. At this time, the filter output voltage VF
Assuming that Δq4 changes from VA to VB, the amount of charge transfer Δq4 from the capacitor C4 before and after switching is expressed as follows. Similarly, the charge transfer amount Δq3 of the capacitor C3 is expressed as follows. Therefore, the residual difference Δq in the amount of charge transfer from capacitor C4 to capacitor C3 can be calculated using Equation 16 and Equation 1.
From 7. However, C3 = C4 = CB. Here, if C1 = C2 = CA, the residual difference Δq
is equally distributed between capacitors C1 and C2, so the amount of charge Δq2 flowing into capacitor C2 is as follows. Since the amount of change ΔV in the output voltage due to the amount of charge Δq2 flowing in is VB −VA , the following holds true, and when VB −VA is determined from this equation, the following is derived.

Here, when the loop filter 30 consisting of a resistor RF and a capacitor CF used in the first embodiment is charged and discharged by the drive current IA from the charge pump 50, the output voltage VF of the loop filter 30 is as follows. expressed. On the other hand, when a similar operation is performed in this embodiment, the voltage VF is first changed to SW by the generation of the phase difference signal.
2 is switched from the d side to the c side, a voltage change amount ΔV occurs in a gap manner, and then the capacitors C1 and C2 due to the drive current IA of the charge pump 50
, C3, and C4 change with a relatively slow time-dependent potential change. That is, the output voltage VF of the loop filter 60 in this embodiment is related to: Comparing Equations 22 and 23, the relationship is as follows. The voltage drop due to RF in the first embodiment is the second
In the embodiment, this corresponds to the gap-like voltage change amount ΔV caused by switching SW2 triggered by the generation of the phase difference signal. This means that even if the resistor RF used in the first embodiment is not present, it can be substantially replaced by the loop filter 60. . Note that Equation 24 is based on the capacitor C
1, C2, C3, and C4 is constant.

By the way, the above-mentioned natural frequency ωn (for example, 10 Mbps to 15 Mbps) is normally determined according to the value of the frequency fIN of the input signal SIN. That is, generally the relationship ωn ∝fIN is desirable. On the other hand, regarding the attenuation factor ζ, regardless of the value of the frequency fIN of the input signal SIN, engineers in the technical field to which phase-locked circuits belong usually have a fixed value of ζ = 2-1/2≒0.7. are often selected. Here, using Equation 1 and Equation 9, Equation 11 can be transformed as follows. The natural frequency ωn is inversely proportional to the external converted current value setting resistor RY of the V/I conversion circuit 42. As mentioned above, in a phase-locked circuit, ωn ∝f
Since it is desirable to have a relationship of Connecting). Therefore, as a result, when the input signal SIN is switched to a signal with a different frequency, by changing the value of the external resistor RY, the oscillation frequency fOSC of the VCO can be changed.
not only changes automatically in proportion to the frequency fIN of the input signal, but also the natural frequency ωn changes automatically in proportion to it.

Regarding the attenuation rate ζ, since CF is constant, the value of the attenuation rate ζ remains unchanged even if the resistance RY is changed. That is, as mentioned above, the natural frequency ωn is the resistance RY
is inversely proportional to. On the other hand, from equations 1 and 2, IA is RY
Since RF is inversely proportional to IA and from equation 24, RF is inversely proportional to RY. Therefore,
Since CF is a constant, from Equation 12, the attenuation rate ζ is a constant unrelated to the resistance RY, and the value of the attenuation rate ζ remains unchanged even if the value of the resistance RY is changed.

[0033] In this way, even when clocks of different frequencies are switched and applied as input signals,
For example, by switching the value of the external conversion current value setting resistor RY in inverse proportion to the frequency of the input signal triggered by the generation of the phase difference detection signals Q1, Q2 or the zone switching signal, the oscillation frequency fOSC of the VCO and the specific The frequency ωn can be made proportional to the frequency of the input signal to automatically follow it, and the so-called lock-in range can be expanded. The attenuation rate ζ can be maintained at a constant value. Therefore, for example, Zone Bit Recording (ZBR), which plans to increase the storage capacity by changing the data transfer rate (in other words, the magnetization reversal interval) between the inner track and the outer track, is used.
), there is no need to provide a plurality of loop filters with different time constants as in the conventional case. In this embodiment, this can be done by simply switching the converted current value setting resistors RY and RY', so the number of components of the loop filter can be significantly reduced. Of course, it is also possible to integrate a plurality of converted current value setting resistors RY into a semiconductor integrated circuit (one chip), but in such a case, the number of input/output pins of the semiconductor integrated circuit can also be reduced.

[0034]

As explained above, the present invention does not use a constant current source as the current source of the drive current in the charge pump means, but uses a feedback loop to generate a current proportional to the conversion current of the voltage-current conversion means. Since it is characterized by the fact that it is a proportional current source, it has the following effects.

■ The closed loop gain G is the conversion current and the current -
It is connected in a proportional relationship to the frequency conversion coefficient. Due to manufacturing variations, the current-frequency conversion coefficient of the voltage-current conversion means varies from product to product, but given the characteristics of the current-frequency conversion circuit, when the input signal and oscillation frequency are synchronized, no phase synchronization occurs. Since the oscillation frequency is the same in the circuit, even if there is a variation in the current-frequency conversion coefficient, a variation in the closed loop gain G does not occur. As a result, the natural frequency ωn and the damping rate ζ are not changed. Therefore, the phase locking characteristics of each phase locking circuit can be made uniform,
Contributes to improved yield in terms of phase locking characteristics. When looking at a certain product, the temperature compensation function is exhibited.

[0036]■ The loop filter means is connected to the first and second
When configured with a capacitor means and a capacitance ratio control means, even if the input signal has a different frequency, the oscillation frequency and natural vibration can be adjusted by switching the value of the conversion current value setting resistor in inverse proportion to the frequency. The number ωn can be made proportional to the frequency of the input signal and automatically tracked. In other words, the lock-in range can be expanded. Also, the damping rate ζ
can be kept at a constant value. Therefore, by using a single loop filter and simply switching the conversion current value setting resistors of different values, the present invention can be applied to devices that employ zone bit recording, etc., and the number of parts or circuit elements can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a phase locked circuit according to the present invention.

FIG. 2 is a circuit diagram showing a phase comparator in the same embodiment.

FIG. 3 is a circuit diagram showing a charge pump and a voltage-current conversion circuit in the same embodiment.

FIG. 4 is a circuit diagram showing a current-frequency conversion circuit in the same embodiment.

FIG. 5 is a block diagram showing a second embodiment of the phase locked circuit according to the present invention.

FIG. 6 is a circuit diagram showing a loop filter in the same embodiment.

FIG. 7 is a block diagram showing a conventional phase synchronization circuit.

FIG. 8 is a circuit diagram showing a schematic configuration of a charge pump in the conventional example.

FIG. 9 is a circuit diagram showing a detailed circuit configuration of the charge pump.

FIG. 10 is a circuit diagram showing a voltage-current conversion circuit in the conventional example.

[Explanation of symbols]

10... Phase synchronized circuit 12, 14... D flip-flop 16... NA
ND gates 30, 60...Loop filter 40...Voltage controlled oscillator (VCO) 42...Voltage-current conversion circuit (V-I conversion circuit) 42
a... Voltage-current conversion section 42b... Current mirror circuit 44... Current-frequency conversion circuit (IF conversion circuit) 4
4a...Charging/discharging constant current source circuit 44b...Pair of comparators 44c...Flip-flop 50...Charge pump 56...Proportional charging current source 58...Proportional discharging current source 62... Output terminal RF ... Loop filter resistance CF ... Loop filter capacitor CO ...
Capacitor RY of I-F conversion circuit...Conversion current value setting resistor C1, C2...Fixed connection capacitor C3, C
4...Switched connection capacitors SW1, SW2 ・
...Switch Q1 ...Lagging phase difference detection signal Q2 ...Advanced phase difference detection signal IA ...Charge pump drive current i2 ...V
- Conversion current SIN of the I conversion circuit...Input signal VOUT...Oscillation output fosc...Oscillation frequency

Claims (9)

[Claims] 1. A phase comparison means for comparing the phase of a first input signal serving as a reference signal and the phase of a second input signal and outputting a phase difference detection signal; charge pump means for supplying a drive current to charge or discharge the loop filter means; and a conversion current value setting resistor, the value of which is substantially proportional to the difference between the output voltage of the loop filter means and the power supply voltage. a voltage-to-current conversion means for generating a converted current, and a current-to-frequency conversion means for sending out an oscillation output having an oscillation frequency substantially proportional to the value of the converted current as a source of a second input signal. A phase-locked circuit, characterized in that the current source of the drive current in the charge pump means is a proportional current source through which a current substantially proportional to the conversion current flows. 2. The phase locked circuit according to claim 1, wherein the phase comparison means receives one of the first input signal and the second input signal as a clock input and outputs a delayed phase difference detection signal. a first flip-flop;
a second flip-flop which uses the other of the input signal and the second input signal as a clock input and outputs a leading phase difference detection signal; A phase-locked circuit comprising a logic circuit that generates reset signals for first and second flip-flops. 3. The phase-locked circuit according to claim 2, wherein the proportional current source generates a charging drive current that is substantially proportional to the value of the converted current, triggered by the generation of the delayed phase difference detection signal. Phase synchronization characterized by comprising a proportional charging current source to flow, and a proportional discharge current source to flow a discharge drive current substantially proportional to the value of the converted current triggered by the generation of the advanced phase difference detection signal. circuit. 4. The phase-locked circuit according to claim 3, wherein the voltage-current conversion means includes a voltage-current converter that generates an input current according to a value of the converted current value setting resistor; A phase synchronized circuit comprising a current mirror circuit that extracts a mirror current substantially equal to the value of the input current as the converted current. 5. The phase locked circuit according to claim 4, wherein the proportional charging current source and the proportional discharging current source are current mirror circuits having the current mirror circuit as a front stage. synchronous circuit. 6. A phase comparison means for comparing the phase of a first input signal serving as a reference signal with a phase of a second input signal and outputting a phase difference detection signal; charge pump means for supplying a drive current to charge or discharge the loop filter means; and a conversion current value setting resistor, the value of which is substantially proportional to the difference between the output voltage of the loop filter means and the power supply voltage. a voltage-to-current conversion means for generating a converted current, and a current-to-frequency conversion means for sending out an oscillation output having an oscillation frequency substantially proportional to the value of the converted current as a source of a second input signal. The current source of the drive current in the charge pump means is a proportional current source that carries a current substantially proportional to the conversion current, and the loop filter means is connected between an output terminal and a first A first capacitor means interposed between the power supply voltage, a second capacitor means interposed between the output terminal and the second power supply voltage, and the first and second capacitor means interposed between the output terminal and the second power supply voltage. and capacitance ratio variable control means for changing the capacitance ratio while keeping the total capacitance of the capacitor means unchanged. 7. The phase-locked circuit according to claim 6, wherein the first capacitor means includes a fixed connection capacitor means connected between the output terminal and the first power supply voltage; switched-connected capacitor means switchably connected between the output terminal and the second power supply voltage, the second capacitor means having fixedly connected capacitor means connected between the output terminal and the second power supply voltage; A phase synchronized circuit comprising switched capacitor means switchably connected between the output terminal and the second or first power supply voltage. 8. The phase-locked circuit according to claim 6 or 7, wherein the capacitance ratio variable control means is a switching means for selectively connecting the switched connection capacitor means. synchronous circuit. 9. The phase-locked circuit according to claim 1, wherein the phase-locked circuit is a one-chip semiconductor integrated circuit.