JPH04216613A - Transmission mask substrate for charged particle exposure and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a charged particle beam transmitting mask, and specifically, the present invention relates to a charged particle beam transmitting mask, and specifically, the present invention relates to a charged particle beam transmitting mask, and specifically, it
The present invention relates to an improvement of a transmission mask substrate for charged beams having a structure in which a plate and a lower Si plate are bonded together.

In recent years, with the increasing density of integrated circuits, new exposure methods using charged beams, such as electron beams or ion beams, or X-rays, are being considered instead of photolithography, which has been the mainstream for forming fine patterns for many years. It has been put into practical use.

[0003] Among these, electron beam exposure, which forms a pattern using an electron beam, is a so-called "one-stroke" process.
Because this is a drawing method, the finer the pattern, the more it is necessary to expose it with a beam with a smaller beam diameter, and as a result, the exposure time becomes enormously longer. In order to solve this problem, a so-called block exposure method was devised.

Transmission mask used in block exposure method (
Stencil mask) is S from the point of view of workability and strength.
It is best to manufacture using i-wafer. In this case, if the thickness of the Si plate is the same as the depth of the transmission hole, the lateral area of the transmission hole will become large, which will cause problems such as easy attachment of dust and charge-up. Only the formation area is made as thin as possible (
(membrane) and a pattern is formed on it.

[0005]

[Prior Art] As a method of manufacturing such a mask,
In order to precisely control the thickness of the thin film portion, there is a method shown in Figure 3. That is, the surface of a wafer (bonded wafer) having a structure in which two Si plates 31 and 33 are bonded together with an oxide film 32 in between as shown in FIG. 3(a) is as shown in FIG. 3(b). , the lower Si plate 31 is covered with a mask layer 34 such as a nitride film or a composite film of a nitride film and an oxide film, and an opening 35 is formed by patterning the lower Si plate 31 as shown in FIG. ), when the lower Si plate 31 is pattern-etched using a caustic potash solution, the etching is stopped when the oxide film layer 32 is exposed because the etching is blocked by the oxide film layer 32, and then the mask layer is etched. By removing 34, a mask substrate is obtained in which a thin film portion 36 on which a mask pattern is fabricated remains, as shown in FIG. 3(e).

When performing electron beam exposure using this bonded mask, the upper Si plate 33 of the bonded wafer is
is insulated by the oxide film layer 32, so the upper Si
The plate 33 is easily charged up. Due to the electric field caused by this charge, the charged beam trajectory bends irregularly near the surface of the Si plate 33, and as a result, the writing accuracy is significantly reduced.

In order to solve this problem, after forming a slot 37 penetrating from the upper Si plate 33 to the lower Si plate 31 as shown in FIG. A conductor film 38 is formed. In this way, the upper Si plate 33 and the lower Si plate 31 are electrically connected. Since the upper Si plate 33 is thus grounded via the lower Si plate 31, charging up of the upper Si plate 33 is prevented.

[0008]

However, in this method, anisotropic etching of the lower Si plate 31 is used to form the slots 37. Therefore, the contact area between the upper Si plate 33 and the conductive film 38 cannot be made very large. Therefore, it is not desirable to sufficiently reduce the grounding resistance of the upper Si plate 33. Another problem is that it is not easy to uniformly form the conductor film 38 on all wafers.

[0009] Therefore, the present invention significantly reduces the grounding resistance of the upper Si plate 33 to completely prevent charge-up.
Moreover, the purpose is to provide a highly productive mask substrate having a bonded structure.

0010

[Means for Solving the Problems] These problems are solved by the following means. That is, a mask substrate for creating a desired pattern using a charged beam has a structure in which an upper Si plate and a lower Si plate are bonded together with an intermediate layer having at least an insulating layer region and a conductive layer region in between. The upper Si plate and the lower Si plate are electrically connected by the conductive layer.

[0011] Such a mask substrate consists of a step of forming an oxide film on the surface of the lower Si plate, a step of forming a mask layer on the oxide film to form a pattern that will become the opening, and a step of forming the lower part in the opening. a step of removing the oxide film down to the Si plate to form a groove portion; a step of embedding a conductive film in the groove portion; a step of polishing the oxide film layer including the conductive film to a flat surface; It can be manufactured by a process of bonding an upper Si plate onto the oxide film and a process of polishing the upper Si plate and the lower Si plate to a desired thickness.

[0012] Also, from the viewpoint of bonding strength and practicality, the conductor film is made of a poly-Si layer or a high impurity concentration Si layer.
Good epi layer.

[0013]

[Function] In the mask substrate structure described above, it is not only possible to electrically conduct the upper Si plate and the lower Si plate at the stage of bonding wafers, but also to make the upper Si plate and the lower Si plate electrically conductive due to the arrangement of the oxide film layer in the intermediate layer. , the contact area between the upper Si plate and the conductive film can be made much larger than that of the conventional method. Therefore, the grounding resistance of the upper Si plate is significantly reduced. . Furthermore, since the contact area is not determined by etching as in the past, there is no variation between wafers, that is, between mask substrates.

[0014]

[Embodiments] Examples of the present invention will be described below with reference to the drawings. Figures 1 (a) and (b) show two types of mask substrates using silicon wafers.

FIG. 1(a) shows a cross-sectional view of a bonded wafer mask substrate having an intermediate layer having a large area of oxide film in the center and a conductor film around it. The upper two figures in FIG. 1(a) show a plan sectional view and a side sectional view, respectively, of the original bonded wafer. The upper Si plate 6 and the lower Si plate 1 are electrically connected by the conductor film 5. The remaining area of the oxide film layer is a membrane-like area formed by etching the lower Si plate 1, and the corresponding upper Si layer is etched into a membrane-like area.
A mask pattern is formed in the area of the plate. When it is necessary that the mask pattern forming area be as large as possible, the structure shown in FIG. 1(a) is suitable.

On the other hand, FIG. 1(b) shows a case where the oxide film layer is dispersed in the intermediate layer of the bonded wafer, and the conductor film is provided in the other regions of the intermediate layer. 2 shows a cross-sectional view of the mask substrate of FIG. Figure 1 (
The upper two figures in b) represent a plan and side cross-sectional view, respectively, of the original bonded wafer. In this case, after etching the lower Si plate 1, a grid-shaped “beam” is formed.
remains, so the membrane is strong. Therefore,
If the area of the mask pattern forming area may be small but you want to ensure the strength of the membrane, use the method shown in Figure 1 (
b) The structure is appropriate.

Next, a method for manufacturing the present mask substrate will be explained with reference to FIG. FIG. 2 is a schematic cross-sectional view showing each step of manufacturing the mask substrate. Figure (a) shows a lower Si plate 1 on which the intermediate layer of the mask substrate is formed. As shown in (b), lower Si plate 1
A silicon oxide (SiO2) film 2 is formed on the top surface of the
Furthermore, a mask layer 3 made of a resist film is formed thereon. Next, as shown in (c), the mask layer 3 is patterned to form openings 4.
Next, as shown in (d), the SiO2 film 2 is removed using the patterned mask layer 3 as a mask. This oxide film etching is performed by dry etching using methane tetrafluoride or methane trifluoride. Next, as shown in (e), the patterned mask layer 3 is removed by oxygen (O2) plasma etching. The mask layer 3 can also be removed using a mixed solution of hydrogen peroxide (H202) and sulfuric acid (H2SO4). Next, as shown in (f),
In (d), a conductive film 5 such as poly-Si is buried in the part where the SiO2 film 2 was removed by the CVD method, and then the conductive film 5 is polished together with the remaining SiO2 film 2 to planarize it. be done. This flattening is carried out to the extent that sufficient strength is ensured when the layers are bonded together next time. Next, as shown in (g), the upper Si plate 6
However, the lower S
It is heated while being aligned with the upper surface of the i-plate 1, and as a result, the upper Si plate 6 and the lower Si plate 1 are bonded together. Next, as shown in (h), the upper Si plate 6 and the lower Si plate 1 are polished to a desired thickness.
Finally, as shown in (i), lower Si plate 1
The mask substrate is pattern-etched using a KOH solution to form a membrane part, and the mask substrate is completed.

[0018]

Effects of the Invention In the charged beam mask having the mask substrate according to the present invention, since the electrical connection between the upper Si plate and the lower Si plate is reliable, the upper S
Charge-up on the i-board side can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of two types of mask substrates according to the present invention.

[Figure 2] Schematic cross-sectional views showing the manufacturing process of the mask substrate according to the present invention, (a) is a diagram of the lower Si plate, (b)
(c) is a diagram in which an oxide film and a mask layer are formed on the upper surface of the lower Si plate, (c) is a diagram in which an opening is formed in the mask layer, (d) is a diagram in which the Si oxide film is pattern-etched, ( (e) is a diagram after the patterned mask layer has been removed, and (f) is a diagram in which a conductor film is embedded in the area from which the Si oxide film in (d) has been removed, and the conductor film is then buried together with the remaining Si oxide film. Diagram of the film being polished and flattened,
(g) shows the upper Si plate and lower Si plate bonded together, (h) shows the upper Si plate and lower Si plate polished to the desired thickness, (i) the membrane part is formed,
FIG. 3 is a diagram of a completed mask substrate.

[Figure 3] Schematic cross-sectional diagrams showing the manufacturing process of conventional mask substrates. (a) is a diagram of a bonded wafer with a Si oxide film sandwiched between them, and (b) is a diagram showing the bonded wafer of (a) covered with a mask layer. (c) is the lower S
Figure with openings created by patterning the i-board, (d)
(e) is a diagram of the lower Si plate with pattern etching.
1 is a diagram of a mask substrate with a mask layer removed and a thin film portion left behind; FIG.

FIG. 4 is a diagram showing a conductor film formed on the inner surface of a hole in a lower Si plate of a conventional mask substrate.

[Explanation of symbols]

1, 31 Lower silicon plate 2, 32 Silicon oxide film 3, 34 Mask layer 4, 35 Opening 5, 38 Conductor film 6, 33 Upper silicon plate

Claims (1)

[Claims] [Claim 1] It is characterized by having an intermediate layer consisting of an insulating layer region and a conductive layer region penetrating both sides of the layer, and two silicon plates bonded from both sides with the intermediate layer interposed therebetween. [Claim 2] An intermediate layer consisting of an insulating layer region and a conductive layer region penetrating both sides of the layer, and a silicon layer on one side bonded from both sides via the intermediate layer. A transmission mask substrate for charged particle exposure, comprising: a silicon plate on the other side from which a portion of the intermediate layer adjacent to the insulating layer region is removed to expose the insulating layer. [Claim 3] ] (a) forming a silicon oxide film on the surface of the lower silicon plate; (b) forming a mask layer on the oxide film and forming an opening by pattern etching; (c) oxidizing the opening. (d) embedding a conductor film in the oxide film region removed in step (c); (e) including the conductor film layer; (f) forming an intermediate layer by planarizing the oxide layer; (f) bonding an upper silicon plate onto the intermediate layer; (g)
polishing the upper silicon plate and the lower silicon plate to a predetermined thickness; and (h) removing a portion of the intermediate layer adjacent to the oxide film region of the lower silicon plate to expose the oxide film layer. 1. A method of manufacturing a transmission mask substrate for charged particle exposure, comprising the steps of: