JPH04213133A - Storage key control system - Google Patents

Abstract

PURPOSE:To decrease the overhead of an access to a main storage device, and to attain the high speed of an information processor by updating a change bit in a storage key, at the time of the first change of a certain page of the main storage device in a store-in system. CONSTITUTION:The copy of a change bit C bit in the storage key is set in a TLB, and at the time of the first writing in the block of the page of an LBS corresponding to the TLB entry, a CP bit in the TLB is set to be 1, and a request for setting the C bit to be 1 is made to the main storage device. Thus, it is not necessary for a CPU to perform an access to the main storage device for changing the C bit in the storage key, each time the writing in the LBS is operated, and the overhead is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage key control method for reflecting changes to buffer storage in changed bits in the storage key in a computer system having storage keys and store-in type buffer storage.

0002

2. Description of the Related Art In many computer systems, a virtual memory system is adopted in order to effectively utilize main memory. Virtual memory method uses program locality to
Only the parts that are frequently used at each point during program execution are placed in main memory, other parts are placed in auxiliary storage, and are read into main memory as needed as the program progresses. It is something. This results in
It is also possible to execute programs that are larger than the main memory capacity. In order to implement virtual memory, main memory is divided into areas of a certain size called pages, and transfers from auxiliary storage to main memory are performed in units of pages.
(page-in) and storage (page-out) from the main memory to the auxiliary storage device.

[0003] At the time of page out, pages that have not been changed in the main memory do not need to be stored in the auxiliary storage device. Information indicating whether or not a page has been changed is included in main memory control information called a storage key.

FIG. 4 shows the structure of the storage key. The storage key consists of a 4-bit access control key (ACC), a retrieval prevention bit (F), a reference bit (R), and a modification bit (C).
). The ACC bit is compared to a 4-bit access key within the central processing unit (CPU). Storage in the main storage device is permitted only when the access key of the central processing unit and the access control key (ACC) of the storage key match. Retrieval from the main memory is permitted if both match and the value of the F bit is 0. The R bit is set to 1 when data in a page is referenced. The R bit is reset to 0 at regular intervals, allowing the OS to know which page was accessed at each time. Based on this information, the OS creates a recent usage frequency of each page existing in main memory, and when it becomes necessary to perform a new page-in, it pages out the least frequently accessed page. The C bit is set to 1 when data is stored in a page of main memory. If the C bit of the page to be paged out is 1, the OS confirms that a mismatch has occurred between the page held in auxiliary storage and the page in main memory, and Write the page back to auxiliary storage. However, if this bit is 0, the page on the auxiliary storage device and the page on the main storage device match, and there is no need to take the trouble to write the page on the main storage device back to the auxiliary storage device. This reduces access to slow auxiliary storage and improves system performance.

[0005] Buffer storage (LBS) has copies of blocks obtained by subdividing data stored in a low-speed, large-capacity main memory in a high-speed, small-capacity cache memory. By layering the storage devices in this way, the apparent access time from the CPU to the storage devices is shortened. This LBS control method is roughly divided into two types: a store-through method and a store-in method. In the store-through method, if the target data is not in the LBS during fetch access to retrieve data from the LBS or main memory, the block is moved in from the main memory to the LBS. In store access, if there is no store destination data in the LBS, the store is performed only in the main memory, and the LB
If there is data to be stored in S, the data is stored in both the LBS and the main storage. That is, in the store-through method, the contents of the LBS are always reflected in the main memory. In the store-in method, in either fetch access or store access, if there is no target data in the LBS, the block is moved in from the main storage device to the LBS.

[0006] Furthermore, in the case of store access, the store is performed only in the LBS. When a write is performed to LBS, LB
Indicates that S has been modified, and sets the modification bit CL bit provided in the TAG memory to 1. Reflection from LBS to main memory is performed when the change bit CL bit of the block to be replaced at the time of move-in is 1, or when the CL bit of another CPU or input/output device is 1. This is the case when a certain block is required. This writing back from the LBS to the main storage device is called moveout. Performance is improved by providing the Cl bit in this manner and eliminating unnecessary moveouts.

The store-through method does not require a move-out operation, so it is easier to control than the store-in method. However, in the store-through method, if there is no data to store in the LBS, the data is stored only in the main memory, and if there is data in the LBS, the data is stored in both the LBS and the main memory, so each CPU Each time a store access occurs, a store to the main memory device occurs, and as the number of CPUs sharing the main memory device increases, there is a drawback that the waiting time for accessing the main memory device increases. Therefore, as the number of CPUs sharing a main memory device increases, there is a tendency to adopt a store-in type LBS that can reduce accesses from the CPUs to the main memory.

Next, the C bit in the storage key will be explained. FIG. 5 shows the address and data flow when storing operands. The store address is sent to the ALU from the instruction control unit (Instruction unit or I unit) that controls the main pipeline.
The information is sent from the arithmetic control section (Execution, ie, E unit) to the storage control section (Storage unit, ie, S unit). The TLB is accessed by a part of the logical address from the I unit, and when the TLB is hit, the page frame address registered in the TLB and the page index in the logical address are combined to obtain a physical address. When a TLB mishit occurs, a dynamic address translation circuit (DAT circuit) determines a page frame address corresponding to the logical address and registers it in the TLB. The TAG is accessed at the same time as the TLB, and the physical address and TL registered in the TAG are
The physical addresses obtained from B are compared. When the two match, data from the E unit is written to the LBS. If there is a mishit, a block fetch request is issued to the main memory, the corresponding block is read into the LBS, and then data is written. The C bit of the storage key must be set to 1 when data is written to the LBS. In the store-through type LBS, since the store is performed in both the LBS and the main memory, the main memory can recognize that the store has been performed and set the C bit to 1.

However, in a store-in type LBS, since a store is performed only in the LBS, the main storage cannot detect the store when it occurs. Therefore,
Each time a store occurs to the LBS, it is necessary to notify the main memory from the CPU in order to set the control bit of the main memory key to 1. Especially when the number of CPUs increases, the The feature of the store-in method, which can suppress communication, could not be fully utilized.

0010

In the store-in method, each time a write is made to the LBS, it is necessary to request the main storage device to update the change bit C bit of the storage key, resulting in a large overhead.

[0011] In the store-in method, the present invention reduces the overhead of accessing the main memory by updating the change bit of the storage key when a certain page in the main memory is first modified. The purpose is to speed up information processing equipment.

0012

[Means for Solving the Problems] As shown in FIG. 1, the present invention comprises a store-in type buffer storage 1 and a dynamic address translation mechanism 2 for converting a logical address into a physical address.
and a TLB 3 that holds the results of dynamic address translation and performs high-speed translation from logical addresses to physical addresses, one or more central processing units 4, and memory provided for each page in main memory. Main memory 6 with key 5
The present invention relates to an information processing device having: By providing a control bit in the TLB 3 that indicates that a change bit in the storage key 5 has been updated, only when a certain page in the main storage 6 is changed for the first time, the main storage 6
It has storage key change bit updating means 8 for requesting update of the change bit in the storage key 5.

[0013]

[Operation] The TLB has a copy of the changed bit C bit in the storage key, and when a block of the page of the LBS corresponding to the TLB entry is first written, the TLB
It sets the CP bit in the memory to 1 and issues a request to the main memory to set the C bit to 1. This results in L
There is no need for the CPU to access the main memory to change the C bit of the storage key every time a write is performed to the BS, reducing overhead.

[0014]

Embodiment FIG. 2 shows an embodiment of an S unit for carrying out the present invention. FIG. 3 is a time chart of this S unit. This S unit operates according to a pipeline indicated by (P-T-B-R). P is prio
ity, T is TLB TAG access, B
represents the cycle of Buffer access, and R represents the cycle of result. TLAR (T cycle
Logical Address Register)
holds the logical address sent from the I unit in the P cycle for T cycles. A line of the TLB is selected by a portion of the logical address held by the TLAR. T
The LB is composed of one or more ways, and has a comparison device COM1 corresponding to each way, a signal generation circuit indicating a matched way, and physical address and CP bit selection circuits SEL1 and SEL2. There is. This signal generation circuit is TWNR (TLB Way Num
ber Register), TLB write way determination circuit D1. The logical address registered in this entry and the upper bit group of TLAR are compared and if they match, the upper bit group of the physical address held in the same entry and the CP bit are
It is output through EL2. If a matching way does not exist, a dynamic address translation (DAT) circuit is activated by a signal indicating a TLB miss, and a physical address corresponding to the logical address is calculated and registered in the TLB. At this time, the CP bit is reset to 0 and written. After registration, the TLB is accessed again and a TLB match is always detected. TAG is the address information of the data held in the LBS and the corresponding LBS.
It holds a CL bit indicating whether the line has undergone a change. The TAG is made up of a plurality of ways and has a signal generation circuit that indicates a matched way. TLAR
A line is selected using part of the logical address held in the TLB, the upper bits of the physical address in the entry are read out, and the physical address sent from the TLB and the comparator COM are read out.
If a matching way exists after comparison in step 2, a signal indicating the hit way is generated. This signal is LWNR (
LBS Way Number Register),
It is sent to the LBS via the LBS write WAY determination circuit D2. When a TAG misses, a request is issued to the main memory to fetch the main memory contents of the physical address sent from the TLB, and at the same time, the TAG corresponding to the way and entry of the moved-in LBS is moved in to the LBS. physical address and CL in the entry of
The bit is registered. At this time, the CL bit is 0. After registration, the TAG is re-accessed and always
An AG match is detected.

BAAR (B cycle Absolute)
te AddressRegister) holds the physical address corresponding to the logical address for B cycles. The upper bit group of the physical address is sent from the TLB, while the lower bit group is sent from the lower bit group (Byte Index) of the logical address of the TLAR.

[0016] STAAR (Store Absolute)
e Address Register) holds the physical address of the storage destination. TWNR holds a signal indicating the way in which the TLB has been hit, and is referenced when determining the way to set the CP bit to 1. LWNR is T
It holds a signal indicating the way of the AG hit and is referenced when determining the TAG way to access the LBS and set the CL bit to 1. EUSTDR(E
Unit Store Data Register)
holds store data from the E unit. The I
IU STDV sent from the unit (IU
nit Store Data Valid) signal. PCFR(Page Change Fla
gRegister) holds the CP bit indicating page changes read from the TLB. In addition, L.S.
The B data selector SEL3 is for selecting data read from each way of the LBS and sending it to the I unit or the E unit.

STDR (Store Data Reg)
ister) aligns and holds the output of EUSTDR so that it is written to a predetermined address of the LBS. The output of STDR is BDIR (B cycle Data
in Register). The TLB write way determining circuit D1 selects a TLB way using the value held in TWNR, and if the value of PCFR is 0, sends a signal (CG) indicating that writing is possible to the selected TLB way. LBS write way determination circuit D
2 selects the TAG and LBS ways using the value held in LWNR. Sends a write enable signal (CG) to the selected TAG way and indicates a change in the LBS block.
Set the L bit to 1. If the AND of the signal that is the inverted value of PCFR and the signal (STORE ACCESS) indicating that a store flow is being executed is 1, set SET MCU REQ to 1, and
Notify U that there is a request to main storage. At the next timing, a tag indicating the content of the request and the target address are sent to the main storage device.

Referring to FIG. 2, the operation of the S unit will be explained in more detail. Here, it is assumed that the logical address and the physical address consist of 31 bits. Bits 1-11 of the logical address are segment index, bits 12-19 are page index, bits 20-31
is a byte index. The byte index is an intra-page displacement and is equal to bits 20-31 of the physical address.

[0019]TLB is PRIMARY and ALTERN
It consists of two ways of ATE. One way is composed of 256 lines, and each line holds a pair of logical address bits 1 to 11, physical address bits 1 to 19, and a page change bit (Cp).

[0020] TAG and LBS consist of 8 ways,
It is assumed that one way consists of 64 lines. TAG ways and lines have a one-to-one correspondence with LBS ways and lines, and hold address information for data in the LBS and a change bit (Cl) that indicates that the data in the LBS has been changed by a store. are doing. T
The address held by AG is either a logical address or a physical address, but here we will consider the case where it holds bits 1 to 19 of the physical address. It is assumed that one line of the LBS holds the contents of the main memory in blocks of 64 bytes.

TLAR holds the operand logical address sent from one unit in P cycles for T cycles. Bit 12 of the logical address held by TLAR
~Select TLB line by bit 19 and PRIMA
Read the logical address and physical address from RY and ALTERNATE respectively. The logical address read from the TLB is determined by the logical address comparator COM1.
It is compared with bits 1 to 11 of LAR. Logical address comparator COM1 is PRIMARY and ALTERN
ATE and are simultaneously checked for logical address matching. A signal indicating that the logical addresses match from the two logical address comparators is sent to the physical address selector SEL1 and the Cp bit selector SEL2, and the PR
PR if the logical addresses on the IMARY side match.
If the physical address on the IMARY side and the Cp bit are selected and the logical address on the ALTERNATE side match, the physical address on the ALTERNATE side and the Cp bit are selected.
A bit is selected. Also, the logical address comparator CO
The result of M1 is held in TWNR. Selected Cp
The bit is held in the PCFR and is referenced when registering the Cp bit in the TLB.

[0022] Also, bits 20 to 25 of TLAR
selects the TAG line and reads out data addresses in the LBS simultaneously from eight ways. A physical address comparator COM2 provided for each way compares the physical address read from the TAG with the physical address read from the TLB. The comparison result is held in the LWNR and is referenced when selecting the LBS way and when selecting the TAG way that registers the Cl bit.

[0023] The TLB write way determination circuit D1
PRIM of TLB with output of WNR and PCFR as input
Cp for either ARY or ALTERNATE
Decide whether to set the bit and send a write enable signal to that way. The LBS write way determination circuit D2 receives the output of the LWNR, determines which way of the LBS is to be accessed, and which way of the TAG to set the Cl bit, and sends a write enable signal to each.

BAAR holds the physical address selected by physical address selector SEL1 in the B cycle. STAAR holds the output of BAAR after the R cycle of the store request. MRQAR(MCU ReQues
tAddress Register) is STAA
A physical address is sent to the MCU using the output of R as an input. Register R sets bits 20 to 25 of TLAR to B
This output is held for a cycle and selects the LBS line.

The data to be stored is sent from the E unit, and the IU STD indicates that this data is valid.
It receives the V signal from the I unit and takes in the data to EUSTDR. The output of EUSTDR is matched to the address of LBS by the ALIGN circuit, taken into BDIR via STDR, and written to LBS.

[0026] When the value of PCFR is 0, that is, the page change bit Cp = 0 and STORE ACCESS is 1.
In other words, only when the page is first stored, the output data of AND is 1, and this is set as SET.
Latch MCU REQ to issue a request to the MCU and set the change bit in the memory key of the main memory to 1. During the second and subsequent stores, the output signal of PCFR is 1, so the output of AND is 0, and SET MCU
REQ is not set. Therefore, no access is made to the main memory.

Next, the embodiment shown in FIG. 2 will be explained using the timing chart shown in FIG. First, in the P cycle, one unit sends a store request and a logical address to which the store should be performed. The first flow of stores is initiated when this request is prioritized. In the T cycle, TLAR takes in and holds the logical address 00001004 sent from 1 unit in the P cycle. This logical address selects the TLB and TAG lines. As a result of comparing the logical addresses by the logical address comparator COM1, the PRIMARY side matches and is converted to the physical address 000E404. As a result of comparing the physical address read from TAG and the physical address obtained from TLB in physical address comparator COM2, way 3 of TAG is hit, and it is detected that the block to be stored exists in way 3 of LBS. be done.

The translated physical address is held in BAAR in the B cycle. BAAR output to STAA
R holds as input the physical address to be stored from the R cycle onward. Also, after the R cycle, LBS way number 3 is assigned to LWNR, and PRIMARY is assigned to TWNR.
Data indicating this is retained. During this R cycle, an IU STDV signal is sent from the I unit, and store data is sent from the E unit. The S unit that receives the IU STDV signal sends an O
Set the P STORE REQUEST signal. At the same time, an STV (STatus Valid) signal is returned to the I unit indicating that the processing of the store request has been completed.

The OP STORE REQUEST signal initiates the first flow of stores. In this P cycle, the value 0 of the Cp bit read from the TLB in the T cycle of the first flow is held in the PCFR. Since PCFR=0 in the state of store access,
The output of AND in Figure 2 becomes 1 and SETMCU REQ
The latch is set. EU STORE DATA “0043” is sent to EUSTDR using the IU STDV signal sent in the previous cycle as a timing signal.
D5F2”.

Next, in the T cycle, the TLAR selects the same TLB and TAG line as the line selected in the first flow of the store. The way to choose is TW
Referring to the values of NR and LWNR, TLB is PRIMARY
Way 3 is selected for TAG. Selected TL
Write 1 as the Cp bit to the line on the PRIMARY side of B. The selected line of way 3 of TAG has CL indicating that the LBS data has been changed.
Write 1 as a bit. Also, SET MCU REQ is set in the P cycle, and SET KEY STORAG is set as the content of the request.
E CHANGE BIT is sent to MCU. At the same time, the output of STAAR is taken into MRQAR as the address of the storage key and sent to MCU. Note that in this flow, there is no need to convert a logical address into a physical address, so the BYPASS TLB signal is set so that address conversion by TLB is not performed.

Next, in cycle B, store data is written to the selected line of way 3 of the LBS, and all processing is completed. MC in set MCU request
Tell U that there is a request and set key storage change at the next timing
Transfers the request bit to the MCU. In other words, the contents of set MCU request are set key
This corresponds to the storage change bit. M
The CU request register tells the MCU the address of which key to operate. That is,
Since keys are held in page units, it is difficult to know which key's change bit should be set to 1 unless you consider the address. The register that notifies the address for this purpose is MRQR (MCU Request Register).
star). Then, MRQR gives a storage key address 0000E400 in page units.

As mentioned above, whereas conventionally a signal to set the change bit C bit of the main memory was sent to the MSU every time a store was performed, in the present invention, the signal to set the change bit C bit of the main memory was sent only for the first store. Bye.

The C bit remains 1 for a page once modified until it is paged out. Therefore, if it is set during the first store, it is sufficient to change it only during the first store, no matter how many times subsequent store instructions arrive.

[0034]

According to the present invention, in the store-in method, by making a request to set the change bit C bit to 1 to the main memory only at the first store, By reducing the number of accesses, even faster operation of the computer device can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram of one embodiment of the invention.

FIG. 3 is a time chart of this embodiment.

FIG. 4 is a diagram showing a storage key.

FIG. 5 is a block diagram of a conventional example.

[Explanation of symbols]

1 Buffer memory 2 DAT circuit 4 Central processing unit 5 Memory key 6 Main memory

Claims (1)

[Claims] [Claim 1] Store-in type buffer storage (1)
, a dynamic address translation mechanism (2) that converts logical addresses to physical addresses, and T that holds the results of dynamic address translation and performs high-speed translation from logical addresses to physical addresses.
An information processing system comprising one or more central processing units (4) having a LB (3), and a main memory (6) having a memory key (5) provided for each page in the main memory. In the device, a control bit (7) indicating that a change bit in the storage key has been updated is provided in the TLB, and based on the control bit (7), a change is made to a page in the main memory for the first time. Main memory (6)
A storage key control system characterized by comprising storage key change bit updating means (8) for requesting update of a change bit in a storage key (5).