JPH04236382A - Integrated magnetoresistance effect element circuit - Google Patents

Abstract

PURPOSE:To decrease the number of magnetoresistance effect elements to a half and miniaturize a chip or reduce power current in an integration magnetoresistance effect element. CONSTITUTION:An integration magnetoresistance effect circuit consists of magnetoresistance effect elements 2, 3 which detect several different magnetic fields and change those resistance values, a current mirror circuit which is connected with the magnetoresistance effect elements 2, 3 and consists of transistors 4, 5 in order to equalize current to flow through these, and an amplifier circuit 6 which amplifies the potential difference between junctions of magnetoresistance effect elements 2, 3 and transistors 4, 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated magnetoresistive element (hereinafter referred to as an MR element) circuit, and particularly to its circuit configuration.

0002

[Prior Art] Conventionally, this type of integrated MR element circuit has
As shown in FIG. 7, the first and fourth sensors detect the same magnetic field.
MR elements 2 and 18 and second and third MR elements 3 and 17, which similarly detect the same magnetic field, are bridge-connected, and the potential difference between their midpoint potentials is amplified by an amplifier 6 to obtain an output. It was configured.

[0003] First to fourth MR elements 2, 3, 17, 18
As the initial resistance value R0 of each M when the magnetic field is detected,
If the resistance fluctuation value of the R element is ΔR, the first and fourth MR
When the elements 2 and 18 detect a magnetic field, the potential difference ΔV1 becomes ΔV1 = (-VCC·4R)÷2R0 (1), where VCC is the voltage value of the DC voltage source. Similarly, when the second and third MR elements 3 and 17 detect a magnetic field, ΔV2 = (VCC 4R) ÷ 2RO (2), and these potential differences are used as input and amplified by the amplifier 6 to obtain an output. Ta.

0004

[Problem to be solved by the invention] This conventional integrated MR
Since the element circuit uses four MR elements, the element chip area becomes large, and if the chip area is limited, the resistance value of the element cannot be increased, and as a result, it is difficult to reduce the power supply current. There are drawbacks such as:

[0005]

[Means for Solving the Problems] The integrated MR element circuit of the present invention includes two MR elements, a current mirror circuit in which each of these two MR elements is connected to a current input terminal and a current output terminal, and The current mirror circuit includes a differential amplifier circuit that amplifies the potential difference between the current input terminal and the current output terminal of the current mirror circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

The first and second MR elements 2 and 3 detect different magnetic fields, and their resistance values change. 1st MR
One end of the element 2 is connected to the collector and base of the first NPN transistor 4, and one end of the second MR element 3 is connected to the collector of the second NPN transistor 5. The bases and emitters of the first and second NPN transistors 4 and 5 are commonly connected to form a current mirror circuit. First and second NPN transistors 4
, 5 are created on the same plane and have very similar characteristics. A DC voltage source 1 is connected between the other ends of the first and second MR elements 2 and 3 and the emitters of the first and second NPN transistors 4 and 5. MR element 2,
3 and the current mirror circuit are connected to a differential amplification type amplifier 6 that amplifies the potential difference between them. Since the NPN transistors 4 and 5 form a current mirror circuit, the currents I1 and I2 flowing therein are I1 = I
2 ...(3) There is a relationship. In addition, the voltage value of DC voltage source 1 is VCC,
If the base-emitter voltage of NPN transistors 4 and 5 is VBE, and the resistances of MR elements 2 and 3 are R2 and R3, then N
Collector voltages V1 and V2 of PN transistors 4 and 5
are respectively V1 = VCC - I1 R2... (4) V2 = VCC
-I2 R3... (5) I1 = I2 = (VCC-V
BE)÷R2...(6) Due to changes in the magnetic field, the MR element 2
When the resistance value changes by 4R, the potential difference ΔV between the collector voltages V2 and V1 becomes ΔV=(VCC-VBE)×(-4R
)÷R0...(6). Similarly, when MR element 3 changes, ΔV=(VCC-VBE)×(4R)÷R0
...(7).

[0009] The potential difference of ΔV is amplified by an amplifier circuit 6,
You can get the output.

FIG. 2 shows an embodiment in which an NPN transistor 7 between the base and emitter is added between the collector and base of the NPN transistor 4 in order to reduce the influence of the base currents of the NPN transistors 4 and 5.

FIG. 3 shows an embodiment in which the circuit is constructed with PNP transistors 8 to 10 instead of NPN transistors 4, 5, and 7.

FIG. 4 shows NMOS transistors 11 and 12.
This is an example in which a circuit is constructed using the following.

FIG. 5 shows how the NPN transistors 13 and 14 are connected between the MR element and the NPN transistor 4 and between the MR element 3.
This is an embodiment in which fluctuations in input/output current due to base currents of transistors added between the NPN transistor 5 and the NPN transistor 5 and used in the current mirror circuit are reduced.

FIG. 6 shows an embodiment in which diodes 15 and 16 are added to level shift the input voltage to the amplifier 6.

[0015]

As explained above, the present invention adds a current mirror circuit to each MR element that detects different magnetic fields, and detects and amplifies the difference voltage by differential amplification. The number can be reduced by half, resulting in reductions in chip area and power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional MR element circuit.

[Explanation of symbols]

1 DC voltage source 2, 3, 17, 18 MR element 4, 5, 7, 13, 14 NPN transistor 8
, 9, 10 PNP transistor 11, 12
MOS transistor 6 Amplifier 15, 16 Diode

Claims (5)

[Claims] 1. First and second magnetoresistive elements, one end of which is connected to one terminal of a DC power source, one end of the first magnetoresistive element is connected to a power input terminal, and one end of the first magnetoresistive element is connected to a power input terminal, a current mirror circuit in which one end of the second magnetoresistive element is connected to a current output end and a common terminal is connected to the other terminal of the DC power supply; and one end of each of the first and second magnetoresistive elements. 1. An integrated magnetoresistive element circuit comprising: an amplifier circuit to which first and second inputs are connected and which amplifies a voltage difference therebetween. 2. The current mirror circuit includes a first transistor having a collector and a base electrically connected to the current input terminal, and a collector of the first transistor having a collector electrically connected to the current output terminal. A second transistor whose base is electrically connected to the base, whose emitter is electrically connected to the emitter of the first transistor, and whose emitter is electrically connected to the common terminal. 2. The integrated magnetoresistive element circuit according to item 1. 3. The current mirror circuit has a base connected to the collector of the first transistor, and an emitter connected to the base of the first transistor, between the collector and the base of the first transistor. 3. The integrated magnetoresistive element circuit according to claim 2, further comprising a third transistor. 4. The integrated magnetoresistive element circuit according to claim 2, wherein the first and second transistors of the current mirror circuit are each comprised of a field effect transistor. 5. The current mirror circuit includes a fourth transistor whose collector is connected to the one end of the first magnetoresistive element and whose emitter is connected to the collector of the first transistor, and a collector and a base. is connected to the one end of the second magnetoresistive element and the base of the fourth NPN transistor, and includes a fifth NPN transistor whose emitter is connected to the collector of the second transistor. An integrated magnetoresistive element circuit according to claim 2, characterized in that the integrated magnetoresistive element circuit is characterized in that: