JPH04239919A - information processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Object of the invention]

0002

TECHNICAL FIELD The present invention relates to an information processing device that executes branch instructions at high speed.

0003

2. Description of the Related Art In recent years, with the advancement of LSI technology, many high-performance microprocessors (hereinafter referred to as information processing devices) that have high processing power integrated into a single chip have been developed. FIG. 4 is a block diagram showing the configuration of a conventional information processing device.
FIG. 5 is an operation timing chart when this information processing device executes a general instruction.

(1) The memory control unit 130 fetches an instruction from the memory address indicated by the fetch counter in the fetch control unit 132 and stores it in the instruction queue 140. (2) The decoder 110 obtains an instruction from the instruction queue 140, decodes it, and generates an instruction length. (3) The execution unit 120 executes an operation based on the processing code, register code, and operation size from the decoder 110, and further updates the program counter based on the actual execution instruction length from the decoder 110. In this way, by pipelining decoding and instruction execution, high-speed processing of general instructions is achieved.

However, if a branch instruction exists, the branch destination instruction cannot be executed at high speed. Here, Figure 6
FIG. 7 shows the operation timing when executing an instruction sequence including a branch instruction such as the following. In Figure 6, BRA is a branch instruction, AD
D is the branch destination instruction. The processing procedure for a branch instruction is as follows. (1) In the data path 121, a branch destination address is calculated by adding the branch address offset in the instruction code to the current program counter value (address calculation cycle in the figure). (2) Using the calculated branch destination address, the memory control unit 130 fetches the branch destination instruction sequence (fetch start cycle in the figure). (3) Start execution of the fetched branch destination instruction sequence (ADD instruction execution cycle in the figure).

[0006] Here, after the branch destination address is calculated in the data path 121, it is possible to start fetching the branch destination instruction string. Furthermore, when it becomes possible to fetch a branch destination instruction, the instructions fetched after the branch instruction (hereinafter referred to as old instructions) are being fetched. For this reason, the decoder 110 cannot immediately proceed to fetching the branch destination instruction sequence (ADD instruction fetch in the figure), and the decoder 110 becomes idle. As a result, a large amount of time is required to transition from execution of the branch instruction to execution of the example branch destination instruction.

[0007]

As described above, in the conventional information processing apparatus, after calculating the branch destination address in the data path, fetching of the branch destination instruction sequence is started. Furthermore, since the old instruction string is being fetched, fetching to the branch destination instruction string is not started immediately. With these,
There is a problem in that the execution unit remains in an idle state for a long time while fetching a branch destination instruction sequence, resulting in a significant delay in transition to the branch destination instruction sequence.

The present invention has been made in view of the above-mentioned conventional circumstances, and its purpose is to immediately stop fetching the old instruction sequence when a branch instruction is recognized, and at the same time to read the branch destination address. An object of the present invention is to provide an information processing device that can significantly speed up the execution of branch instructions by performing calculations using a fetch control unit.

[Configuration of the invention]

0010

[Means for Solving the Problem] In order to achieve the above object, the present invention, upon recognizing that an acquired instruction is a branch instruction, immediately instructs to stop fetching of instructions after the branch instruction, and at the same time A decoder that requests address calculation, an instruction fetch means that stops fetching instructions after the branch instruction according to instructions from this decoder, and a branch destination address calculation means that executes branch destination address calculation according to a request from this decoder. The branch destination instruction is quickly executed by the instruction fetching device fetching the branch destination instruction at the branch destination address calculated by the branch destination address calculation device.

[0011]

With the above structure, the present invention instructs the fetch control unit from the decoder to stop fetching the old instruction sequence at the same time as branch instruction decoding starts. At the same time, the fetch control unit immediately calculates the branch destination address upon request from the decoder. The branch destination instruction at the calculated branch destination address is fetched by the fetch control unit, and the branch destination instruction is quickly executed.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. The overall configuration of the information processing device of this invention is the same as that shown in FIG. The information processing device shown in FIG. 4 includes a decoder 110, an execution unit 120, a memory control unit 1
30 and an instruction queue 140.

The decoder 110 includes an instruction register 111 that temporarily holds a machine language instruction code to be decoded, a decode sequencer 112 that controls decoding state transitions, and a control signal generator 11 that generates a predetermined control signal in a predetermined state.
Consists of 3. The control signal generation unit 113 generates a predetermined control signal according to the machine language instruction code from the instruction register 111 and the state number from the decode sequencer 112. The control signal generation unit 113 sends instruction processing code, register code,
Outputs the instruction length. Furthermore, control signals such as a fetch start instruction and a fetch stop instruction, which is a feature of the present invention, are output to the memory control unit 130. Further, from the instruction register 111, the immediate data and jump destination address present in the instruction code are transferred to the control signal generation unit 11.
3, the data is transferred to the literal buffer in the data path 121 and the fetch control unit 132.

The decoder 110 performs the following processing. (1) A request is made to the instruction queue 140 to obtain an instruction, and the instruction is obtained and decoded. If the second and third words are required, an acquisition request is further issued to the instruction queue 140. (2) If the instruction obtained from the instruction queue 140 includes displacement and immediate data, store this in the literal buffer in the data path 121. (3) Immediately after decoding a branch instruction or shampoo instruction, a fetch stop or queue clear instruction is issued. Furthermore, if possible, it requests the memory control unit 130 to calculate the branch destination address and start fetching the branch destination instruction string. (4) A condition is determined at the time of a conditional branch instruction, and when the condition is satisfied, a request is made to the memory control unit 130 to start fetching the branch destination instruction sequence.

The execution unit 120 is composed of a data path 121 and an execution sequencer 122, and based on the processing code obtained by decoding the machine language instruction with the decoder 110,
This is a block that executes calculations. The data path 121 is
It consists of various registers, arithmetic units, buses, and literal buffers. Furthermore, although the execution sequencer 122 is composed of a state transition circuit and a control signal generation circuit, it may also be configured as a microprogram. data path 12
1, an execution sequencer 122 controls arithmetic registers and arithmetic units to perform arithmetic operations. Furthermore, the program counter in the memory control unit 130 is updated under the control of the execution sequencer 122. Execution sequencer 122
is a control signal for starting a state transition according to a processing code from the decoder 110 and controlling the data path 121 in a predetermined state, or a data access control unit 13
Outputs a memory access request for 1.

The memory control section 130 is composed of a data access control section 131 and a fetch control section 132, the details of which will be described later. The data access control unit 131 manages timing cycles of the memory bus. According to instructions from the execution sequencer 122, calculation data is read from and written to the memory at a specified address. When there is no memory access instruction from the execution sequencer 122 and there is space in the instruction queue 140, an instruction is fetched using the fetch counter value in the fetch control unit 132 as an address and stored in the instruction queue 140.
An instruction is issued to the fetch control unit 132 to increment the fetch counter.

The instruction queue 140 is a FIFO (Firs
t_In, First_Out) configuration, the fetched instruction is stored under the control of the data access control unit 131, and if there is a request from the decoder 110, the fetched instruction is stored in the decoder 1.
Outputs the command to 10.

FIG. 1 is a block diagram showing the detailed configuration of the fetch control section 132. The fetch control unit 132 includes a program counter 11, a program counter updater 12, and a branch destination address adder 13, which is the core of this invention.
, fetch counter 14, fetch counter updater 15
, and MUX (multiplexers) 16 and 17.

[0019] Program counter (hereinafter abbreviated as PC)
11 indicates the address of the instruction currently being executed by the execution unit 120. The program counter updater 12 adds the actual executed instruction length to the PC 11 and outputs the address of the next executed instruction, that is, the instruction currently being decoded (hereinafter referred to as the next PC value). When executing a normal continuous instruction sequence, the execution sequencer 122 selects P
C11 is updated with the next PC value. When the execution instruction sequence becomes discontinuous due to the execution of a branch instruction, etc., the new P
C value is transferred via the internal data bus, and with this value the PC
Update 11.

[0020] Fetch counter (hereinafter abbreviated as FC) 1
4 is updated independently of the PC 11. During normal fetching of consecutive instructions, each word is updated by the output value of the fetch counter updater 15 under the control of the data access control unit 131 every time one instruction is fetched. When decoding a branch instruction, the output of the branch destination address adder 13 is stored in the FC 14 according to instructions from the decoder 110. The branch destination address adder 13 is configured to always add a bit area in which a branch offset exists during instruction decoding to the next PC value. Note that the next PC value is used as the base of the branch destination address when decoding a branch instruction.
This is because the address of the branch instruction is indicated by the next PC value. By providing this branch destination address adder 13, calculation of the branch destination address is started in parallel with the start of instruction decoding. If the decoded instruction is a branch instruction, the multiplexer 17 at the input stage of the FC 14 is controlled so that the output of the branch destination address adder 13 is stored in the FC 14 . In cases other than branch instructions, meaningless addition is performed, but the addition result is discarded as is, and the multiplexer 16 is controlled to update the PC 11 with the incremented value.

Next, the operation of branch instruction processing by the information processing apparatus of the present invention will be explained. Operation timing diagrams when the instruction sequence shown in FIG. 6 is executed are shown in FIGS. 2 and 3. (1) The instruction register 111 of the decoder 110 starts decoding an instruction. When the decoder 110 recognizes that this instruction is a branch instruction, it issues a fetch stop instruction to the memory control unit 130 so as not to enter a new fetch, and clears the instruction queue 140. The fetched data is not stored in the instruction queue 140 even if it has entered a new fetch. Further, the decoder 110 stores the branch destination address offset in a literal buffer in the data path 121 (see FIG.
and the fetch stop cycle in FIG. 3).

In parallel with the fetch stop instruction from the decoder 110, the branch destination address adder 13 in the fetch control unit 132 starts adding the branch destination address offset and the next PC value. Since the bit position where the branch destination address offset exists in the branch instruction code is fixed, the branch destination address adder 13 always detects the presence of the branch destination address offset regardless of whether this instruction is a branch instruction or not. Adds the bit area and the next PC value. Therefore, if it is not a branch instruction, a completely meaningless operation will be performed, but if it is a branch instruction, the data path 12
1, the branch destination address for fetching by the fetch control unit 132 is calculated before starting the branch destination address calculation during execution. During this clock cycle, a branch destination address for fetching is stored in the FC 14 (address calculation cycle in the figure).

(2) The decoder 110 issues an instruction to the fetch control unit 132 to start fetching the branch destination instruction sequence. The fetch control unit 132 waits until the memory access by fetching the old instruction is completed, and if the memory access is completed, starts fetching the branch destination instruction sequence. Since we have already issued an instruction to stop fetching the old instruction string in (1), we can quickly start fetching the branch destination instruction string (
(fetch start cycle in the same figure). (3) The processing code of the branch instruction is transferred from the decoder 110 to the execution sequencer 122. After that, the branch destination instruction is fetched into the instruction queue 140, so
From here, decoding of the branch destination instruction sequence starts (instruction cycle to the execution unit in the figure).

Next, a description will be given of the processing performed by the execution unit 120 to which the processing code for the branch instruction is passed. (4) Based on instructions from the execution sequencer 122, the data path 12
1, the branch destination address offset stored in the literal buffer and the PC value are added to calculate the branch destination address at the time of execution. (5) The calculated branch destination address is sent to the fetch control unit 13
The data is stored in the PC 11 in the PC 2. As a result, the branch destination instruction is executed (ADD instruction execution cycle in the figure).

As can be seen from FIGS. 2 and 3, regardless of the phase relationship between fetch and decoding due to the difference in timing, the loss in decoding due to a branch instruction is suppressed to one clock. Compared to the conventional timing shown in FIG. 7, since the fetch of the old instruction is stopped at the same time as decoding, and the address is calculated at the same time, the idle period during decoding is shortened. As a result, while conventionally there was a waiting time of 5 clocks from the execution of the BRA instruction to the execution of the ADD instruction, this is shortened to 2 clocks in the present invention.

As described above, by immediately stopping the fetching of the old instruction when the decoder 110 recognizes a branch instruction, it is possible to quickly move on to fetching the branch destination instruction sequence. Furthermore, since the branch destination address for fetching can be immediately obtained by the branch destination address adder 13, it is possible to quickly move to fetching the branch destination instruction string. With these, speeding up of branch instructions can be realized.

The present invention can be used as is to speed up not only branch instructions but also branch subroutine instructions. Furthermore, although the branch destination address adder 13 is not used for absolute addressing jump instructions and jump subroutine instructions, other speed-up techniques, such as stopping the fetching of the old instruction sequence at the same time as jump instruction decoding starts, can be used as is. It can be applied. Also,
It can also be applied directly to conditional branch instructions. in this case,
Fetch stops at the same time as conditional branch instruction decoding starts,
The calculation of the branch destination address is the same, and the decode judges the condition, and if the condition is met, it starts fetching with the calculated branch destination address, and if the condition is met, it starts fetching with the incremented fetch address as usual. good. Since the frequency of appearance of these instructions together is relatively high,
This invention also leads to improvement in overall processing speed.

Furthermore, the present invention is not limited to the configuration described in this embodiment. For example, in this embodiment, the decode sequencer 112 and the execution sequencer 12
Although the two are separated, the same effect can be obtained even if they are integrated into one as in the past. In this case, the basis for calculating the branch destination address is the program counter value. The old instruction fetch is stopped at the same time as the instruction is executed, and the branch destination address is calculated using the branch-dedicated adder. Although the processing speed will be lower than when the decoder 110 is separated, a significant speed improvement can be expected compared to when these measures are not taken.

[0029]

As described above, according to the information processing device of the present invention, when the decoder recognizes a branch instruction, it stops fetching the instruction sequence after the branch instruction, and further decodes the branch instruction. The branch destination address is calculated in parallel in the fetch control unit. As a result, it is possible to immediately proceed to fetching the branch destination instruction sequence, and it is possible to realize a significant increase in the speed of branch instructions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a fetch control unit that is a feature of an information processing device of the present invention.

FIG. 2 is a timing diagram when a branch instruction is executed according to the present invention.

FIG. 3 is a timing diagram when the phase is shifted from that in FIG. 2;

FIG. 4 is a block diagram of a conventional information processing device.

FIG. 5 is a timing diagram when a general instruction is executed by a conventional information processing device.

FIG. 6 is an example of an instruction sequence including a branch instruction.

FIG. 7 is a timing diagram when a conventional information processing device executes a branch instruction.

[Explanation of symbols]

11 Program counter 12 Program counter updater 13 Branch destination address adder 14 Fetch counter 15 Fetch counter updater 16, 17 MUX (multiplexer) 110 Decoder 111 Instruction register 112 Decode sequencer 113 Control signal generation unit 120 Execution unit 121 Data path 122 Execution Sequencer 130 Memory control unit 131 Data access control unit 132 Fetch control unit 140 Instruction queue

Claims (1)

[Claims] 1. A decoder that, upon recognizing that the acquired instruction is a branch instruction, immediately instructs to stop fetching instructions after the branch instruction and simultaneously requests calculation of a branch destination address; The branch destination of the branch destination address calculated by the branch destination address calculation device is provided with an instruction fetch unit that stops fetching of subsequent instructions, and a branch destination address calculation unit that executes branch destination address calculation according to a request from the decoder. An information processing device characterized in that a branch destination instruction is quickly executed by fetching the instruction by the instruction fetching means.