JPH04230077A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

[Industrial Application Field] The present invention is a NAND cell type EEP
It relates to semiconductor storage devices such as ROM.

0002

2. Description of the Related Art EEPROMs using electrically rewritable memory cells having floating gates and control gates are known. Among these, an EEPROM in which a plurality of memory cells are connected in series so that adjacent ones share the source and drain diffusion layers to form a NAND cell is attracting attention as a device that can be highly integrated.

However, this type of EEPROM has the following problems. One is that the memory cells in the periphery of the cell array region where the memory cells are arranged are different in shape and characteristics from those inside. There are two reasons for this. Generally, in this type of memory cell, the floating gate is arranged so as to partially extend from the element region onto the field region in order to sufficiently increase the coupling capacitance between the floating gate and the control gate. However, the field area outside the cell array area has a larger area than the field area formed alternately with the element area inside the cell array area. Therefore, when a field oxide film is formed using the normal LOCOS method, the swell of the field oxide film in a wide field area outside the cell array area becomes larger than the swell of the field oxide film for isolating cells inside the cell array area. . As a result, the shape of the floating gate and control gate to be processed differs between the interior of the cell array region and the peripheral portion thereof, which have different flatness. This causes variations in memory cell characteristics. Another reason is that the seepage effect of impurities in the anti-inversion layer formed by ion implantation in the field region is different between the field region located inside the cell array region and the peripheral portion of the cell array. This is because a sufficiently large amount of impurity is introduced into a wide field region outside the cell array region compared to a narrow field region inside the cell array region. This also appears as variations in the characteristics of the memory cells.

The second problem is that in this type of EEPORM, a high potential boosted from the power supply potential is used for writing and erasing data, so the reliability of MOS transistors in the peripheral circuits to which these high potentials are applied is affected. It is difficult to ensure that In order to ensure the reliability of MOS transistors to which a high potential is applied, it is necessary to make their gate oxide films sufficiently thick. In accordance with this, if the thickness of the gate oxide film of a MOS transistor using a power supply potential is increased, the gate length cannot be shortened in order to reduce short channel effects and the like.

Another problem is that when a CMOS circuit is used as a peripheral circuit, channel ion implantation is usually required to optimize the characteristics of each of the p-channel MOS transistor and the n-channel MOS transistor, which increases the manufacturing process. becomes complicated.

A similar problem occurs in NAND cell type EEPRO.
It exists not only in M but also in NOR type EEPROM, and not only in EEPROM but also in various semiconductor memory devices such as DRAM and SRAM.

[0007]

[Problems to be Solved by the Invention] As described above, conventional semiconductor memory devices have problems in peripheral circuits that use high potential, where memory cell characteristics differ between the inside of the memory cell array area and the peripheral area. There have been problems in that the gate length of a MOS transistor cannot be miniaturized, and that the manufacturing process becomes complicated if a CMOS peripheral circuit is used.

An object of the present invention is to provide a semiconductor memory device that solves these problems and improves its characteristics.

[Configuration of the invention]

0010

[Means for Solving the Problems] Firstly, in a semiconductor memory device having a cell array in which a plurality of memory cells are arranged and formed on a semiconductor substrate, the present invention provides a structure in which a cell array inside the cell array is provided at the end of a field region outside the cell array region. A feature is that a dummy element region is formed to make memory cell characteristics uniform.

Second, the present invention provides a semiconductor memory device in which a cell array consisting of a plurality of electrically rewritable memory cells and a peripheral circuit for controlling writing, erasing, and reading of this cell array are formed on a semiconductor substrate. , a MOS transistor to which the power supply potential in the peripheral circuit is applied to the gate, and a MOS transistor to which a high potential higher than the power supply potential is applied to the gate.
A feature is that the gate oxide films of the S transistors have different thicknesses.

Thirdly, the present invention provides that a cell array consisting of a plurality of electrically rewritable memory cells is formed in a second conductivity type well of a first conductivity type semiconductor substrate, and a second conductivity type separate from the cell array area is formed. In a semiconductor memory device in which a peripheral circuit for controlling writing, erasing, and reading of a cell array formed in a type well is formed, a first conductive channel MOS transistor formed in the second conductive type well in the peripheral circuit; The method is characterized in that channel ion implantation of the second conductive channel MOS transistor formed in the first conductive type well formed in the second conductive type well is performed simultaneously.

[0013]

[Operation] According to the present invention, by providing a dummy element region at the end of the field region outside the cell array region,
The pattern processing conditions and impurity seepage effect in the cell array region become uniform throughout the cell array region, thus improving the uniformity of memory cell characteristics.

Further, according to the present invention, the gate insulating film thickness of the MOS transistor to which a high potential is applied and the MOS transistor to which a power supply potential is applied in the peripheral circuit is made different depending on the applied potential. It is possible to achieve both miniaturization of elements within a circuit and ensuring reliability.

Furthermore, according to the present invention, by forming a double well structure in the peripheral circuit and performing channel ion implantation of the p-channel MOS transistor and the n-channel MOS transistor simultaneously, desired threshold values can be obtained for each of the p-channel MOS transistors and the n-channel MOS transistor. The manufacturing process can be simplified.

[0016]

Embodiments Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 shows a NAND cell type EE according to an embodiment of the present invention.
This is a layout showing the NAND cell of PROM, and is shown in Figure 2.
(a) and (b) are A-A' and B-B' in Figure 1, respectively.
3 is a cross-sectional view, and FIG. 3 is an equivalent circuit of a NAND cell array. In this embodiment, a NAND cell is constructed by connecting four memory cells M1 to M4 and two selection gates S1 and S2 in series so that adjacent ones share their source and drain diffusion layers. ing. NAND like this
Cells are arranged in a matrix to form a cell array. The drain of the NAND cell is connected to the bit line BL via the selection gate S1, and the source is connected to the ground line SS via the selection gate S2. Control gates CG1 to CG4 of each memory cell are continuously arranged to intersect with a bit line to form a word line. In this embodiment, the NAND cell is composed of four memory cells, but generally one NAND cell can be composed of 2n memory cells.

A specific memory cell structure will be explained with reference to FIG. In this embodiment, an n-type silicon substrate 1 is used, and a p-type well 2 is formed in this substrate 1.
A cell array is configured. As will be explained later, the peripheral circuit is formed in a p-type well formed separately from the cell array region. The NAND cell has L in the p-type well 2.
An element isolation oxide film 10 is formed by the OCOS method, and floating gates 4 (41 to 44) are formed via the first gate oxide film 3 in the element region surrounded by this element isolation oxide film 10. 2 Control gate 6 via gate oxide film 5
(61-64) are formed. First gate oxide film 3
is a thermal oxide film with a thickness of 5 to 20 nm, and the second gate oxide film 5 is a thermal oxide film with a thickness of 15 to 40 nm. Furthermore, the floating gate 4 is formed of a first layer of polycrystalline silicon with a thickness of 50 to 400 nm, and the control gate 6 is formed of a second layer of polycrystalline silicon with a thickness of 100 to 400 nm. Four memory cells are connected in series so that the n-type diffusion layer 9 serving as the source and drain of each memory cell is shared by adjacent memory cells. The substrate on which the gate and diffusion layer are formed is covered with a CVD insulating film 7, and a bit line 8 is provided on this.

In the two selection gates S1 and S2, the gate oxide film 32 is formed to have a thickness of 25 to 40 nm, which is thicker than that of the memory cell. The gate electrodes 45 and 46 are formed using the same first layer polycrystalline silicon film as the floating gate 4. Wiring lines 65 and 66 formed of the same second layer polycrystalline silicon film as the control gate 6 are connected to the gate electrodes 4.
5 and 46, and are connected to gate electrodes 45 and 46 via through holes at predetermined intervals.

The floating gate 4 and control gate 6 of each memory cell, the gate electrodes 45 and 46 of the selection gate, and the wiring 65
, 66 are simultaneously patterned using the same etching mask in the gate length direction. The n-type layer 9, which becomes the source and drain diffusion layers, is formed by ion-implanting arsenic or phosphorus using these gate electrodes and interconnections as masks.

The floating gate 4 of the memory cell is shown in FIG. 2(a).
As shown in FIG. 2, the pattern is formed so that it runs over the field oxide film 10 from the element region, so that the capacitance C1 between the control gate 4 and the substrate 1 of the memory cell is equal to the capacitance C2 between the floating gate 4 and the control gate 6. is set smaller than . This will be explained using specific numerical examples. 1μ
According to the m rule, the floating gate 4 and the control gate 6 have a width of 1 μm and a channel length of 1 μm. Further, the floating gate 4 is extended by 1 μm on both sides over the field region. 1st
The gate oxide film 3 is 20 nm thick, and the second gate oxide film 5 is 35 nm thick.
Let it be nm. When the dielectric constant of the thermal oxide film is ε, the coupling capacitances C1 and C2 are as follows, respectively: C1=ε/0.02 C2=3ε/0.035. That is, the condition C1<C2 is satisfied.

FIG. 4 shows the layout of the peripheral portion of the cell array region and the field region portion in contact therewith. In the field region at the end of the cell array in the direction in which the control gate line runs, that is, in the word line direction, a dummy element region 11 is formed as shown by diagonal lines. Let a be the interval between element regions in the cell array region, and let a be the interval between the endmost element region in the cell array region and the dummy element region 11 formed in the field region. An n-type diffusion layer is not formed in this dummy element region 11 unlike in the cell array region. The p-type well in the cell array region is formed to the bottom of this dummy element region, and this dummy element region 1
The Al wiring 13 disposed on the high concentration p-type diffusion layer 12
It is in contact with the p-type well through. 14 is its contact portion. This Al wiring 13 is also connected to the third
It is also brought into contact with a ground line 15 formed of a layered polycrystalline silicon film. 16 is its contact portion.

The dummy element region is provided not only outside the cell array region but also inside the cell array region in a portion that becomes a wide field region for each predetermined bit for wiring contacts and the like. 5 and 6 show the layout of those parts.

FIG. 5 shows a field region inside the cell array region in which a contact portion 17 for bringing the two-layer polycrystalline silicon films of selection gate lines SG1 and SG2 into contact with each other is provided. Even within the cell array region, the field region in which such a contact portion 17 is provided has a larger area than field regions in other cell array regions. Therefore, a dummy element region 18 as shown by diagonal lines is provided in such a field region.

FIG. 6 shows a layout of a portion where the ground line 15 and the p-type well are connected by the Al wiring 23 inside the cell array region. Since this portion also becomes a wide field region due to the Al wiring 13 and its contacts, a dummy element region 19 as shown by diagonal lines is provided here as well. The Al wiring 13 contacts the p-type well through the heavily doped p-type layer 21 at the contact portion 22, and also contacts the ground line 15 made of the third layer polycrystalline silicon film at the contact portion 20.

FIG. 7 shows a cross section taken along the line AA' in FIG. 4 in comparison with a conventional structure without a dummy element region. Figure 7 (
As shown in b), in the conventional structure, the step of the field oxide film 10 is larger at the edge of the cell array region than inside the cell array region, and therefore the flatness during processing of floating gates and control gates is different from that inside the cell array region. . Further, the impurity seepage effect of the inversion prevention layer 23 is large for the memory cells at the end of the cell array region. As described above, these are the causes of variations in memory cell characteristics within the cell array region. On the other hand, in this embodiment, as shown in FIG. 7(a), the dummy element region 11 is formed at the end of the field region outside the cell array region, so that all the memory cells in the cell array region are connected to the gate electrode. The effects of processing conditions and impurity seepage from the anti-inversion layer are made equal. The same applies to the wide field region portions in the cell array region shown in FIGS. 5 and 6. Therefore, according to this embodiment, memory cell characteristics with excellent uniformity can be obtained.

FIG. 8 shows a portion of a MOS transistor (hereinafter referred to as a Vpp-based MOS transistor) to which a high potential, for example, a boosted potential Vpp (for example, 20 V) in the peripheral circuit section is applied, and a gate to which a power supply potential Vcc (for example, 5 V) is applied. (hereinafter referred to as Vc
This is the structure of a c-type MOS transistor. The peripheral circuit is formed in a p-type well 24 that is formed separately from the p-type well 2 in which the cell array is formed. Vpp-based MO
For example, the S transistor part has a gate oxide film 25 of 50 nm.
1, and the Vcc system MOS transistor part is 20 to 25n.
The gate oxide film 252 has a thickness of m. Each gate electrode 261, 262 is patterned simultaneously using the same polycrystalline silicon. Also, n becomes the source and drain.
The type diffusion layer 27 is also formed in self-alignment using each gate electrode as a mask. The Vpp type MOS transistor has a so-called LDD structure in which a low concentration n-type layer 28 is provided in the portions of the source and drain diffusion layers that are in contact with the channel.

The thickness of the gate oxide film is determined in the following manner. First, Vpp-based MOS
A gate oxide film 251 of the transistor is formed by thermal oxidation. The film thickness at this time is, for example, the final required film thickness of 50 nm, taking into consideration that the film thickness will be increased by later thermal oxidation.
It is assumed that m is 44 nm. Then, the gate oxide film 251 in the Vcc-based MOS transistor region is removed by etching, and thermal oxidation is performed again to form the gate oxide film 252 of the Vcc-based MOS transistor with a thickness of 20 to 25 nm. As a result, the previously formed gate oxide film 251 has a desired final thickness of 50 nm.

Note that the gate oxide film can be formed by thermal oxidation method or by
A rapid thermal annealing (RTA) method may also be used. The oxidizing atmosphere may be dry O2, N2 or A
HCl, O2, H2O, etc. diluted with an inert gas such as r, etc. may be used, or a combination of these may be used.

9 and 10 similarly show the V of the peripheral circuit.
This is another example of a structure in which gate oxide films are formed separately for a pp-type MOS transistor and a Vcc-type MOS transistor.

In FIG. 9, first, a Vpp-based gate oxide film 2 is formed.
51 is formed with a thickness of 25 nm by, for example, a thermal oxidation method. Thereafter, the gate oxide film in the Vcc-based MOS transistor region is removed, and the gate oxide film 29 formed by the TEOS film is removed.
is formed simultaneously in the Vcc and Vpp systems. The subsequent steps are as usual. In the Vpp type MOS transistor region, the gate oxide film has a two-layer structure of a thermal oxide film and a TEOS film, and in the Vcc type, it has a single layer TEOS film. Therefore, by selecting the respective film thicknesses, Vpp system and Vcc
The gate breakdown voltage of each MOS transistor in the system can be set to a desired value.

In this structure, the Vpp type gate oxide film in particular has a two-layer structure, thereby reliably preventing short-circuit accidents due to pinholes and the like, thereby improving reliability. TEOS as the second gate insulating film between the floating gate and control gate of the memory cell
When using a film, at the same time Vcc in the peripheral circuit
Forming the gate oxide film of the system MOS transistor simplifies the process. The TEOS film may be subjected to heat treatment after film formation. For example, by performing heat treatment in an atmosphere containing O 2 , the TEOS film becomes denser, improving reliability, and at the same time, the etching rate with the NH 4 F solution is reduced, improving the process margin.

In FIG. 10, first, as shown in (a), V
A gate oxide film 251 having a final thickness is formed in the pp-based MOS transistor region. and photoresist 30
Vcc-based MO using NH4F solution.
The oxide film in the S transistor region is removed by etching. Next, while leaving the photoresist 30, LPD (Liquid Phase Deposits) is applied using this as a mask.
ition) method, as shown in (b), the Vcc system M
A gate oxide film 31 of the OS transistor is formed. Specifically, this LPD method is a method of depositing a silicon oxide film by adding an H2BO3 solution to a saturated solution of SiO2 powder (eg, silica gel) dissolved in an aqueous solution of, for example, H2SiO3. After this, the gate electrode and the source and drain diffusion layers may be formed using normal steps.

With this method, separate Vpp-based and Vcc-based gate oxide films can be formed without affecting each other. Therefore, the controllability of the film thickness is excellent. Note that a hydrophobic film such as polycrystalline silicon or the like can be used instead of the photoresist.

Although Vpp-based and Vcc-based MOS transistors have been described in FIGS. 8 to 10, an intermediate potential VppM (for example, 10 V) is normally used in addition to Vcc and Vpp in a NAND cell type EEPROM. Therefore, it is desirable that the gate oxide films of the Vcc, Vpp and VppM type MOS transistors be made to have different values so as to have optimum values. This can be easily achieved by employing the method described in FIGS. 8 to 10.

Next, threshold control of various MOS transistors in the peripheral circuit will be explained. CMO peripheral circuits
In case of S configuration, p channel MOS transistor and n
It is necessary to optimally set the threshold values of each channel MOS transistor. Further, even in the same n-channel MOS transistor, since the gate oxide film thickness is different between the Vcc type and the Vpp type, it is necessary to optimally set the threshold value for each of them. If these threshold settings were performed by separate channel ion implantations, the process would become very complicated. In this embodiment, the threshold control process is simplified, as will be explained below.

FIG. 11 shows a p-type well 2 in which a cell array is formed, and a p-type well 24 for peripheral circuits separated from the p-type well 2, in which an E-type, n-channel Vpp type MOS is provided. Transistor Qn1 and Vcc system MO
It shows how an S transistor Qn2 and an E type, p channel Vcc type MOS transistor Qp are formed. The p-channel MOS transistor Qp is formed in this double well structure by further forming an n-type well 32 within the p-type well 24.

FIGS. 12 to 14 show the manufacturing process of this peripheral circuit section.

First, as shown in FIG. 12, a p-type well 24 is formed in the substrate 1, and then an n-type well 32 is formed within the p-type well 24. Thereafter, a field oxide film 10 is formed by the LOCOS method. Then, thermal oxidation is performed to obtain approximately 4
A 4 nm gate oxide film 33 is formed and a photoresist is applied to cover the region of the Vpp type MOS transistor Qn1. Mask 34 is patterned to etch away the gate oxide film in other areas.

After that, the photoresist mask 34 is removed and thermal oxidation is performed again to reduce Vcc as shown in FIG.
A gate oxide film 35 in the system MOS transistor Qn1 and Qp region is formed to a thickness of 20 to 25 nm. At this time, the film thickness of the gate oxide film 33 in the Vpp-type MOS transistor region previously formed increases to a desired final film thickness of about 50 nm. Next, in this state, Vpp type W type, n channel MOS transistor Qn1, Vcc type E type, n
Channel MOS transistor Qn2 and E type, p
Boron ions are implanted into the region of the channel MOS transistor Qp for threshold control. Other areas are covered with mask material. Next, although not shown in the figure, ion implantation is performed for necessary threshold voltage control in the D type MOS transistor region and the like.

Next, as shown in FIG. 14, a gate electrode 35 is formed by depositing and patterning a polycrystalline silicon film, and respective source and drain layers are formed. The Vpp type MOS transistor Qn1 has an LDD structure consisting of a heavily doped n-type layer 37 and a shallower n-type layer 38 with a lower concentration. Further, the Vcc type n-channel MOS transistor Qn2 has an LDD structure including a heavily doped n-type layer 39 and a deeper lightly doped n-type layer 40. Also in the Vcc system p-channel MOS transistor Qp, the highly doped p-type layer 4
1 and a low concentration p-type layer 42 deeper than this.

FIG. 15 shows the above-mentioned boron ion implantation and MOS transistors Qn1, Qn2 and p-channel M.
It shows the relationship between the threshold voltages of the OS transistor Qp. As is clear from the figure, by simultaneously implanting boron ions into the channel regions of these different MOS transistors Qn1, Qn2, and Qp, each can be made into an E type having a predetermined threshold value. In other words, since the region of the p-channel MOS transistor Qp is an n-type well 32 with a higher concentration than the p-type well 24, the excessively high threshold voltage is lowered to some extent by boron ion implantation, and the region of the n-channel MOS transistor Qn2 is The E type can be used, which has a threshold value approximately equal in absolute value to that of the E type. Also, Vpp type n-channel MOS transistor Qn1
and the Vcc system n-channel MOS transistor Qn2, there is a difference in the threshold voltage due to the difference in gate oxide film thickness, but this degree of difference can be easily prevented from causing operational problems by devising circuit technology. It is. Or,
A dummy oxide film of, for example, 10 nm is formed in the region of the MOS transistor Qn2 of the thin gate oxide film 35 before forming the gate oxide film.
It is also possible to bring the threshold values of n-channel MOS transistors Qn1 and Q2 closer to each other by performing ion implantation in a state where transistors are formed.

Next, the NAND cell type EEPR of this embodiment
The operation of OM will be explained. In the following operation description, the boosted potential used for data erasing is assumed to be Vpp1, and the boosted potential used for data writing is assumed to be Vpp2. For example, Vpp1=
18V and Vpp2=12 to 20V, but these may be used as a common boosted potential. First, data erasure is performed on all memory cells in a selected NAND cell at once. At this time, all control gate lines CG1 to CG4 in the NAND cell are set to 0V, and the n-type silicon substrate 1,
A boosted potential Vpp1 is applied to the p-type well 2, bit line BL, and selection gate lines SG1 and SG2 in the cell array region. As a result, electrons are emitted from the floating gate to the p-type well in all memory cells due to tunnel current. Due to this electron emission, the threshold voltage of the memory cell moves in the negative direction and becomes "0".

Next, writing data to the NAND cell is as follows:
Memory cell M4 farther from the bit line in the NAND cell
This is done in order from That is, when writing data to the memory cell M4, for example, (1/2) Vpp1 is applied as the intermediate potential VppM to the selection gate line SG1 on the drain side, the selection gate line SG2 on the source side is set to 0V, and the control of the memory cell M4 is performed. Vpp2 is applied to the gate line CG4, and intermediate potential VppM is applied to the remaining control gate lines CG1 to CG3. P-type well 2 and substrate 1 are set to 0V. Bit line B
0V is applied to L according to data “0” and “1”, respectively.
, an intermediate potential VppM is applied. For example, when 0V is applied to the bit line BL, this is transmitted to the drain of the selected memory cell M4 through the unselected memory cells M1 to M3, and from the drain to the floating gate of the memory cell M4 to which a high potential is applied to the control gate. Electrons are injected by tunnel current. As a result, the threshold value moves in the positive direction and data "1" is written. When the intermediate potential VppM is applied to the bit line, the state of the selected memory cell does not change and the data remains at "0".

Thereafter, data is written to the memory cells M3, M2, and M1 by sequentially setting the selection control gate line to Vpp.

Data reading is performed using the selection gate lines CG1, CG2 and the control gate lines CG1 to CG connected to the non-selected memory cells.
3, the selected control gate line CG4 is given 0V, and the bit line BL is given Vcc (for example, 5V).
A predetermined read potential of cc or smaller is applied. Thereby, data "0" or "1" can be determined depending on whether a current flows through the bit line BL.

Table 1 summarizes the potential relationship of each part in each of the above operation modes.

[0047]

[Table 1] Although the embodiments of NAND cell type EEPROM have been described above, the present invention can be similarly applied to NOR type EEPROM, and can also be applied to DRAM and SRAM.
It can be applied to various other semiconductor memory devices such as.

[0048]

According to the present invention, by providing dummy element regions inside and outside the cell array region, it is possible to provide a semiconductor memory device with uniform memory cell characteristics and improved characteristics.

[Brief explanation of the drawing]

FIG. 1: NAND of EEPROM according to an embodiment of the present invention
Top view of the cell.

FIG. 2 is a sectional view taken along line AA' and line BB' in FIG. 1;

FIG. 3 is an equivalent circuit diagram of the cell array of the same embodiment.

FIG. 4 is a plan view showing the structure of the peripheral part of the cell array region of the same embodiment.

FIG. 5 is a plan view showing the structure of a selection gate line contact portion inside the cell array of the same embodiment.

FIG. 6 is a plan view showing the structure of a ground line contact portion inside the cell array of the same embodiment.

FIG. 7 is a cross-sectional view showing the A-A' cross-sectional structure in FIG. 4 in comparison with a conventional example;

FIG. 8 is a cross-sectional view showing the transistor structure of the peripheral circuit of the same embodiment.

FIG. 9 is a cross-sectional view showing another transistor structure of the peripheral circuit.

FIG. 10 is a cross-sectional view showing still another transistor structure of the peripheral circuit.

FIG. 11 is a cross-sectional view showing three types of transistor structures in a peripheral circuit.

12 is a cross-sectional view showing the manufacturing process of the peripheral circuit section of FIG. 11. FIG.

13 is a cross-sectional view showing the manufacturing process of the peripheral circuit section of FIG. 11; FIG.

14 is a cross-sectional view showing the manufacturing process of the peripheral circuit section shown in FIG. 11; FIG.

FIG. 15 is a diagram showing threshold characteristics of three types of transistors.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... P-type well, 4... Floating gate, 6... Control gate, 8... Bit line, 13, 18, 19
...Dummy element area.

Claims (7)

[Claims] 1. A semiconductor memory device having a cell array in which a plurality of memory cells are arranged and formed on a semiconductor substrate, wherein a dummy element region is formed at an end of a field region outside the cell array region. Device. 2. The semiconductor memory device according to claim 1, wherein a dummy element region is formed in a wide field region provided for wiring contact for each predetermined bit in the cell array region. 3. The memory cell is an electrically rewritable memory cell in which a floating gate and a control gate are stacked, and a plurality of memory cells share their source and drain diffusion layers with adjacent ones. connected in series with NA
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device constitutes an ND cell. 4. A semiconductor substrate, a cell array comprising a plurality of electrically rewritable memory cells formed on the substrate, and a peripheral circuit for controlling writing, erasing, and reading of the cell array formed on the substrate. In the semiconductor memory device, the film thickness of the gate oxide film of a MOS transistor in the peripheral circuit to which a power supply potential is applied to the gate and a MOS transistor to which a high potential higher than the power supply potential is applied to the gate is made different. A semiconductor storage device. 5. A first conductivity type semiconductor substrate, and a second conductivity type semiconductor substrate of this substrate.
Writing, erasing, and reading of a cell array formed in a conductivity type well and consisting of a plurality of electrically rewritable memory cells, and a cell array formed in a second conductivity type well different from the cell array area of the substrate. a first conductive channel MOS transistor formed in the second conductive type well in the peripheral circuit; and a first conductive channel MOS transistor formed in the second conductive type well in the peripheral circuit; A semiconductor memory device characterized in that channel ion implantation of a second conductive channel MOS transistor formed in a well is performed at the same time. 6. A semiconductor substrate, a cell array formed on the substrate and comprising a plurality of electrically rewritable memory cells, and a peripheral circuit for controlling writing, erasing, and reading of the cell array formed on the substrate. In the semiconductor memory device, channel ion implantation of a MOS transistor in the peripheral circuit to which a power supply potential is applied to the gate and a MOS transistor to which a high potential higher than the power supply potential is applied to the gate is performed simultaneously. semiconductor storage device. 7. The memory cell has a floating gate and a control gate formed in layers, and a plurality of memory cells are connected in series with adjacent ones sharing their source and drain diffusion layers to form a NAND cell. 7. The semiconductor memory device according to claim 4, characterized in that: