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JPH0423388A - Printed board - Google Patents

Printed board

Info

Publication number
JPH0423388A
JPH0423388A JP2123431A JP12343190A JPH0423388A JP H0423388 A JPH0423388 A JP H0423388A JP 2123431 A JP2123431 A JP 2123431A JP 12343190 A JP12343190 A JP 12343190A JP H0423388 A JPH0423388 A JP H0423388A
Authority
JP
Japan
Prior art keywords
printed circuit
circuit board
terminals
solder
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2123431A
Other languages
Japanese (ja)
Inventor
Hitoshi Kudo
均 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2123431A priority Critical patent/JPH0423388A/en
Publication of JPH0423388A publication Critical patent/JPH0423388A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ワードプロセッサ、パーソナルコンピュータ
、CAD端末等の回路を構成するプリント基板に関する
もので、特に高密度で各種素子の端子が配置されたプリ
ント基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a printed circuit board that constitutes the circuits of word processors, personal computers, CAD terminals, etc., and particularly relates to a printed circuit board on which terminals for various elements are arranged at high density. It is something.

従来の技術 半導体集積素子の集積化が進んでいるが、半導体集積素
子だけで回路が構成できることは少なく、個別半導体素
子(ダイオード、パワートランジスタなと)や受動素子
(抵抗、コンデンサなと)とがプリント基板上で配置、
配線されて回路か構成される場合が一般的である。また
同時に複数個の半導体集積回路が組み合わされることが
多い。1つの半導体集積素子内部の配線幅(1〜5μm
)に較べてプリント基板上の配線は、1ran〜5 +
n+n程度と太く配線そのものの集積度としては、効率
かあまり良くない。従って両面配線や、3層から5層の
積層配線構造が採用されることもある。
Conventional technology Although the integration of semiconductor integrated devices is progressing, it is rare that a circuit can be constructed only with semiconductor integrated devices, and individual semiconductor devices (diodes, power transistors, etc.) and passive elements (resistors, capacitors, etc.) placed on the printed circuit board,
Generally, it is wired to form a circuit. Furthermore, a plurality of semiconductor integrated circuits are often combined at the same time. Wiring width inside one semiconductor integrated device (1 to 5 μm
), the wiring on the printed circuit board is 1ran~5+
The wiring is as thick as n+n, and its efficiency is not very good in terms of the degree of integration of the wiring itself. Therefore, double-sided wiring or a laminated wiring structure of three to five layers may be employed.

第5図に素“子(能動素子としての半導体素子や、各種
受動素子の一般的な総称としてチップという表現がされ
る)の端子がプリント基板に実装された状態を示す。第
5図では、接続端子が各種素子の2方向に配置された例
である。各接続端子1は、プリント基板2上のプリント
配線3に対応して、半田4により所定の固定位置で電気
的に接続されている。プリント配線の非接続部5は、表
面に絶縁被膜6が被覆しているため、半田4はっかない
。この図の例では、あらかじめ素子は接着剤でプリント
基板に固定されたのち、半田で電気的に固定・接続され
る。
Figure 5 shows a state in which the terminals of an element (semiconductor elements as active elements and chips as a general term for various passive elements) are mounted on a printed circuit board. This is an example in which connection terminals are arranged in two directions of various elements. Each connection terminal 1 is electrically connected at a predetermined fixed position by solder 4 in correspondence with a printed wiring 3 on a printed circuit board 2. .The unconnected parts 5 of the printed wiring are coated with an insulating film 6 on the surface, so the solder 4 is not applied.In the example shown in this figure, the element is fixed to the printed circuit board with adhesive in advance, and then soldered. Electrically fixed and connected.

発明が解決しようとする課題 素子内部の集積度に較べて、プリント基板上の集積度は
あまり高くないため、ビン数が多く、かつそれらピッチ
間のピッチの微細な素子(半導体集積回路素子等)のプ
リント基板上への集積は端子接続で問題が発生する可能
性が高い 半導体素子の多機能化、高機能化に伴い、半導体素子の
端子数は次第に増加する傾向にある。たとえば、DSP
(デジタルシグナルプロセッサ)やMPU(マイクロプ
ロセシングユニット)テハ200ビンを超える多ピンの
パッケージが使われており、256ビンのPGA (ピ
ングリッドアレイ)や、QFP (クアドロフラットパ
ッケージ)か実用化されている。また取り扱うデータ量
の増大と、処理の高速化のためにデータバス、命令バス
幅も32ビツトや64ビツトとなり、端子数の多いコネ
クタや接続端子が必要になってきている。
Problem to be Solved by the Invention Since the degree of integration on a printed circuit board is not very high compared to the degree of integration inside the device, devices with a large number of bins and a fine pitch between them (semiconductor integrated circuit devices, etc.) There is a high possibility that problems will occur with terminal connections when integrated onto printed circuit boards.As semiconductor devices become more multifunctional and sophisticated, the number of terminals on semiconductor devices tends to gradually increase. For example, DSP
(Digital Signal Processor) and MPU (Micro Processing Unit) A multi-pin package with more than 200 bins is used, and 256-bin PGA (Pin Grid Array) and QFP (Quadro Flat Package) are in practical use. . Furthermore, as the amount of data to be handled increases and processing speed increases, the width of the data bus and command bus has become 32 bits or 64 bits, and connectors and connection terminals with a large number of terminals have become necessary.

一方で、装置の大きさは小さいものが要求されるため、
半導体素子のパッケージやコネクタは、高密度化が不可
欠になっている。現在のところ、プリント基板上では、
0.5岨ピ・ソチ程度か実用化されているが、さらに小
さいピンチでの実装か求められている。しかしプリント
基板上の配線ピッチを狭めると隣の配線との短絡の危険
性が飛躍的に高くなる。チップに設けられた接続端子(
リード)も配線ピッチに従って小さくなるため、容易に
変形しプリント基板への実装時に隣の配線と接続されて
しまう。こうした問題を解決するために、プリント基板
実装率の直前になるまで、端子(リード)を切り離さな
いでおく方法が試みられているが、十分な解決策にはな
っていない。
On the other hand, since the size of the device is required to be small,
High density is essential for semiconductor device packages and connectors. Currently, on printed circuit boards,
It has been put into practical use with a pinch size of about 0.5 mm, but there is a need for an even smaller pinch size. However, narrowing the wiring pitch on a printed circuit board dramatically increases the risk of short circuits with adjacent wiring. Connection terminal provided on the chip (
Leads also become smaller in accordance with the wiring pitch, so they are easily deformed and connected to adjacent wiring when mounted on a printed circuit board. In order to solve these problems, attempts have been made to leave the terminals (leads) uncut until just before the printed circuit board mounting rate, but this has not been a sufficient solution.

第6図に素子の端子が変形により、プリント基板上で接
続され短絡する様子を示す。接続端子1は、リード(接
続端子)の切り離し時やその後の輸送時に、機械的な力
を受けて変形し易い。特にピッチが小さくなると接続端
子1の機械的強度は低下し、変形し易くなると同時に、
少しの変形量でとなりの端子と接触して不良を発生させ
る。第6図では、接続端子1は、プリント基板3の本来
の接続部分をはずれてななめに、半田4によって固定さ
れるため、となりの接続端子との間で半田4か電気的に
接続している。
FIG. 6 shows how the terminals of an element are connected on a printed circuit board and short-circuited due to deformation. The connection terminal 1 is easily deformed by mechanical force when the lead (connection terminal) is separated or during subsequent transportation. In particular, when the pitch becomes smaller, the mechanical strength of the connecting terminal 1 decreases, making it easier to deform, and at the same time,
A small amount of deformation will cause contact with the adjacent terminal and cause a failure. In FIG. 6, the connecting terminal 1 is fixed with solder 4 diagonally away from the original connecting part of the printed circuit board 3, so that the solder 4 is electrically connected to the adjacent connecting terminal. .

第7図に、半田量か多すぎて素子の端子かプリント基板
上で接続され短絡する様子を示す。接続端子1は、リー
ド(接続端子)の切り離し後、あらかしめ半田づけを容
易にするためにリードには半田がぬられている。プリン
ト基板に実装するときに、リードについた半田が流れて
、となりの端子と接触して不良を発生させる。
FIG. 7 shows a situation in which the terminals of the element are connected on the printed circuit board due to too much solder, resulting in a short circuit. After the leads (connecting terminals) are separated, the connecting terminals 1 are coated with solder to facilitate caulking and soldering. When mounting on a printed circuit board, the solder on the leads flows and comes into contact with the adjacent terminals, causing defects.

maを解決するための手段 接続端子が、配線ピッチに伴って細くなるのは避けられ
ないし、細くなることによって機械的強度が低下するの
も避けられないことである。従って、接続端子が多少変
形しても、不良とならないような対策が必要である。半
田量が不適切で不良が発生する場合でも、同様である。
Means for solving ma It is unavoidable that the connecting terminal becomes thinner as the wiring pitch increases, and it is also unavoidable that the mechanical strength decreases as the connecting terminal becomes thinner. Therefore, it is necessary to take measures to prevent the connection terminal from becoming defective even if the connection terminal is slightly deformed. The same applies even if a defect occurs due to an inappropriate amount of solder.

従来の技術では、プリント基板はほとんど平坦で、その
上に導電層を形成し、所定のパターンに従いエツチング
しているため、導電層は他のプリント基板面よりも高い
位置にある。この位置関係を逆転させて、溝のなかに導
電層を埋め込めば、多少の接続端子の変形かあっても、
それら端子の位置決めが容易になり、余分の半田かあっ
ても隣接する端子間で半田ブリッジの可能性も減少して
、不良になりにくい構造を提供することができる。
In the prior art, the printed circuit board is generally flat, and a conductive layer is formed thereon and etched according to a predetermined pattern, so that the conductive layer is at a higher level than other printed circuit board surfaces. If this positional relationship is reversed and a conductive layer is buried in the groove, even if the connection terminal is slightly deformed,
Positioning of these terminals becomes easier, and even if there is excess solder, the possibility of solder bridging between adjacent terminals is reduced, making it possible to provide a structure that is less prone to defects.

すなわち、各種素子を固定保持し、回路を構成する基板
において、前記各種素子の接続端子に対応する基板面が
、前記各種素子の接続端子間に対応する基板面よりも、
内部に低く凹部を形成させる事により、接続部の不良発
生を低減するものである。
That is, in a substrate that holds various elements fixedly and constitutes a circuit, the surface of the substrate corresponding to the connection terminals of the various elements is larger than the surface of the substrate corresponding to the connection terminals of the various elements.
By forming a low concave portion inside, the occurrence of defects at the connection portion is reduced.

作用 凹部内に接続部があるため、リードが変形していても、
壁の部分に抑えられて隣のリードに近づきすぎない。ま
た、凹部がより量の多い半田を蓄えることができるため
、流れ出た半田が端子間で接触することがなくなる。
Since the connection part is inside the working recess, even if the lead is deformed,
The wall prevents you from getting too close to the adjacent reed. Furthermore, since the recess can store a larger amount of solder, the solder that flows out will not come into contact between the terminals.

実施例 以下本発明の実施例を図面を用いて説明する。Example Embodiments of the present invention will be described below with reference to the drawings.

第1図は、従来例で説明したように素子(能動素子とし
ての半導体素子や、各種受動素子の一般的な総称として
チップという表現がされる)の端子かプリント基板に実
装された状態を示す。第1図では、接続端子が各種素子
の2方向に配置された例がある。各接続端子1は、プリ
ント基板2上のプリント配線3に対応して、半田4によ
り所定の固定位置で電気的に接続されている。プリント
配線の非接続部5は、表面に絶縁被膜6が被覆している
ため、半田4はつかない。この図の例では、あらかじめ
素子は接着剤でプリント基板に固定されたのち、半田で
電気的に固定・接続される。
Figure 1 shows a state where an element (semiconductor element as an active element and a chip is a general term for various passive elements) is mounted on a terminal or a printed circuit board as explained in the conventional example. . In FIG. 1, there is an example in which connection terminals are arranged in two directions of various elements. Each connection terminal 1 is electrically connected to a printed wiring 3 on a printed circuit board 2 at a predetermined fixed position by solder 4. The surface of the unconnected portion 5 of the printed wiring is covered with an insulating film 6, so that the solder 4 does not stick to it. In the example shown in this figure, the elements are first fixed to the printed circuit board with adhesive and then electrically fixed and connected with solder.

第2図に、素子の端子が変形し、従来プリント基板上で
接続され短絡される場合を示す。接続端子1は、リード
(接続端子)の切り離し時やその後の輸送時に、機械的
な力を受けて変形し易い。
FIG. 2 shows a case where the terminals of an element are deformed and connected and shorted on a conventional printed circuit board. The connection terminal 1 is easily deformed by mechanical force when the lead (connection terminal) is separated or during subsequent transportation.

特にピッチが小さくなると接続端子1の機械的強度は低
下し、変形し易くなると同時に、少しの変形量でとなり
の端子と接触して不良を発生させる。第2図では、接続
端子1は、プリント基板3の本来の接続部分をはずれて
ななめになっているが、凹部の壁によって隣の端子に問
題となるほと接近しないため、となりの接続端子との間
で半田4か電気的に接続する事はない。
In particular, when the pitch becomes small, the mechanical strength of the connecting terminal 1 decreases, making it easy to deform, and at the same time, even a small amount of deformation causes contact with an adjacent terminal, resulting in a defect. In Fig. 2, the connection terminal 1 is diagonally removed from the original connection part of the printed circuit board 3, but because the wall of the recess prevents it from coming close enough to the adjacent terminal to cause a problem, There is no solder 4 or electrical connection between them.

第3図に、従来、半田量か多すぎて素子の端子かプリン
ト基板上で接続され短絡する場合を示す。接続端子1は
、リード(接続端子)の切り離し後、あらかしめ半田づ
けを容易にするためにリードには半田がぬられている。
FIG. 3 shows a conventional case in which the amount of solder is too large and the terminals of an element are connected on a printed circuit board, resulting in a short circuit. After the leads (connecting terminals) are separated, the connecting terminals 1 are coated with solder to facilitate caulking and soldering.

プリント基板に実装するときに、リードについた半田が
流れて、となりの端子と接触して不良を発生させるが、
本実施例では、凹部がより多くの半田を蓄えるため、隣
の端子と接続されることはない。
When mounting on a printed circuit board, the solder on the leads may flow and come into contact with the adjacent terminals, causing defects.
In this embodiment, since the recess stores more solder, it is not connected to an adjacent terminal.

以上説明した、凹部の大きさは、接続端子の厚さや幅に
よって最適な値が変わるが、あまりに深くするのは工程
処理を困難にし、歩留りを低下させるし、あまりに浅い
凹部では十分な効果が得られないので、おおよそ深さは
、接続端子(リード)の厚さの1倍から3倍(おおよそ
0.5〜3m1.I)、凹部の幅は、0.05〜0 、
5 mm幅程度か適している。
As explained above, the optimal value for the size of the recess changes depending on the thickness and width of the connection terminal, but making it too deep will make the process difficult and reduce the yield, while a recess that is too shallow will not provide sufficient effect. Therefore, the depth is approximately 1 to 3 times the thickness of the connecting terminal (lead) (approximately 0.5 to 3 m1.I), and the width of the recess is 0.05 to 0.0 m.
A width of about 5 mm is suitable.

第4図は、本発明の凹部を形成する方法について説明し
たものである。第4図(alでは、なんら表面に配線パ
ターンが形成されていないプリント基板41上に、凹部
をあらかしめ形成するため、レジスト42の所定パター
ンか形成されている。第4図(blでは、次にレジスト
42をマスクとしてプリント基板41を所定量(0,5
mmから3 mm )エツチングした状態が示されてい
る。第4図(C1では、レジスト42を除去後プリント
配線となる金属薄膜43(0,1m+aから0.5−)
を形成し、接続端子用レジスト44のパターンを形成し
た状態が示されている。第4図fd)では、接続端子用
レジスト44をマスクとして、金属薄膜43をエツチン
グした状態か示されており、以後通常の方法でプリント
基板に、半導体集積素子をマウント(実装)する。
FIG. 4 illustrates a method for forming a recess according to the present invention. In FIG. 4 (al), a predetermined pattern of resist 42 is formed on a printed circuit board 41 on which no wiring pattern is formed on the surface, in order to roughly form recesses. Using the resist 42 as a mask, a predetermined amount (0,5
mm to 3 mm) is shown in the etched state. FIG. 4 (In C1, metal thin film 43 (from 0.1m+a to 0.5-) that will become printed wiring after removing resist 42
A state in which a pattern of a resist 44 for connection terminals has been formed is shown. FIG. 4fd) shows the state in which the metal thin film 43 is etched using the connection terminal resist 44 as a mask, and the semiconductor integrated element is then mounted on a printed circuit board using a normal method.

プリント基板の材質としては、特に限定する必要はなく
、エボキン樹脂やガラス繊維積層板なとを用いることが
できる。
The material of the printed circuit board is not particularly limited, and Evokin resin, glass fiber laminate, etc. can be used.

発明の詳細 な説明したように、本発明では、IM〜0.5mmピン
チ以下の半導体集積回路素子のリード(接続端子)を、
プリント基板に実装するに際し、あらかしめ接続端子と
プリント基板配線部との接続部を、他のプリント基板面
よりも低くし、凹部を形成することにより、隣接する接
続端子間の短絡による接続不良を防止することかできる
As described in detail, in the present invention, the leads (connection terminals) of semiconductor integrated circuit elements with a pinch size of IM to 0.5 mm or less,
When mounting on a printed circuit board, the connection between the staking connection terminal and the printed circuit board wiring section is made lower than the other printed circuit board surface and a recess is formed to prevent connection failures due to short circuits between adjacent connection terminals. It can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図、第3図は本発明の詳細な説明する図で
あり、各図の(alは平面図、(blと(C1は断面図
である。第4図(al〜+dlはそれぞれ本発明の製造
方法を説明する図、第5図、第6図、第7図は従来例を
説明する図であり、各図の(alは平面図、(blと(
C1は断面図である。 1・・・・・・接続端子、2・・・・・・プリント基板
、3・・・・・プリント配線、4・・・・・・半田。 代理人の氏名 弁理士 粟野重孝 はか1名第 図 (oL) L−+B′ (b) / 、・接続搗j 5・・・プリンヒ色己却咳非i餘糸九名p6・・・東色
未1串良PI莫 (C) (b) し6′ (C)
FIGS. 1, 2, and 3 are diagrams explaining the present invention in detail, and in each figure (al is a plan view, (bl and (C1 are sectional views). are diagrams for explaining the manufacturing method of the present invention, and Figures 5, 6, and 7 are diagrams for explaining the conventional example, and in each figure (al is a plan view, (bl and (
C1 is a cross-sectional view. 1... Connection terminal, 2... Printed circuit board, 3... Printed wiring, 4... Solder. Name of agent Patent attorney Shigetaka Awano 1 person Figure (oL) L-+B' (b) / ,・Connection 5...Principal color self-dismissal cough non-i 9 people p6...East Iromi 1 Kushiryo PI Mo (C) (b) Shi6' (C)

Claims (1)

【特許請求の範囲】[Claims] 基板と、前記基板に固定保持される素子と、前記基板の
所定位置に形成された凹部を備え、前記素子が前記凹部
内に固定保持することを特徴とするプリント基板。
1. A printed circuit board comprising a substrate, an element fixedly held on the substrate, and a recess formed in a predetermined position of the substrate, the element fixed and held within the recess.
JP2123431A 1990-05-14 1990-05-14 Printed board Pending JPH0423388A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2123431A JPH0423388A (en) 1990-05-14 1990-05-14 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2123431A JPH0423388A (en) 1990-05-14 1990-05-14 Printed board

Publications (1)

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JPH0423388A true JPH0423388A (en) 1992-01-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012070381A1 (en) * 2010-11-22 2012-05-31 日本電気株式会社 Mounting structure and mounting method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636485B2 (en) * 1982-07-26 1988-02-10 Kogyo Gijutsuin

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636485B2 (en) * 1982-07-26 1988-02-10 Kogyo Gijutsuin

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012070381A1 (en) * 2010-11-22 2012-05-31 日本電気株式会社 Mounting structure and mounting method
US9204551B2 (en) 2010-11-22 2015-12-01 Lenovo Innovations Limited (Hong Kong) Mounting structure and mounting method

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