JPH04245475A - Manufacture of photosemiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a photodiode in high performances while making the formation and the miniaturization of an NPN transistor 13 compatible with each other by laminating a P<-> type epitaxial layer. CONSTITUTION:A lower side separating region 16 is formed on the surface of a P type substrate 11 and then a P type epitaxial layer 17 is formed. Next, the impurities for the formation on an N type collector region 19 are ion- implanted firstly to thermal diffuse the lower side separation region 16 and the collector region 19. Later, an upper side separation region 20, a P type base region 23, an N type emitter region 24 and the N<+> type diffused region 27 of a photodiode 26 are formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an optical semiconductor device that integrates a photodiode and a bipolar IC.

0002

[Prior Art] Optical semiconductor devices in which a light-receiving element and peripheral circuitry are integrated and formed monolithically are expected to reduce costs, unlike hybrid ICs in which the light-receiving element and circuit elements are made separately. , which has the advantage of being resistant to noise caused by external electromagnetic fields.

As a light receiving element of a conventional optical semiconductor device,
For example, the structure described in Japanese Unexamined Patent Publication No. 61-47664 is known. That is, as shown in FIG. 20, a P-type substrate (1)
The N type epitaxial layer (2) formed above, the island region (4) separated by the P+ type isolation region (3), the P type diffusion region (5) formed on the surface of the island region (4), and the N
+ type diffusion region (6), P type diffusion region (5) and N
The PN junction with the mold island region (4) is configured as a photodiode (7). (8) is an N+ type buried layer.

By the way, in terms of improving the performance of the photodiode (7), it is better to increase the resistivity of the island region (4) which becomes the cathode, thereby reducing the capacitance. Therefore, in the same Japanese Patent Application Laid-Open No. 61-47664, an N-type well region (10) is formed in an NPN transistor (9), and by supplementing the impurity concentration of the region that will become the collector, a photodiode (
An example of improving the performance of 7) has been disclosed.

[0005]

[Problems to be Solved by the Invention] However, when an epitaxial layer (2) is grown on a P-type substrate (1),
The epitaxial layer (2) is composed of boron (B) from the substrate (1).
) due to autodoping or unexpected entry from outside.
subject to ingress of type impurities. Therefore, if the specific resistance of the N-type epitaxial layer (2) is increased, it becomes difficult to maintain the epitaxial layer (2) as an N-type, and there is a drawback that it is difficult to control the resistance value and conductivity type.

Furthermore, due to the above-mentioned situation, it is not possible to increase the specific resistance, so the width of the depletion layer formed at the PN junction of the photodiode (7) cannot be increased, and therefore the junction capacitance, which affects the characteristics of the photodiode (7), cannot be increased. There were some drawbacks that could not be reduced sufficiently. Furthermore, there is a drawback that the response speed of the photodiode (7) deteriorates due to the transit time of carriers generated outside the depletion layer, which are generated deep in the P-type diffusion region (5) or the epitaxial layer (2).

Furthermore, in order to make the well region (10) suitable as the collector of the NPN transistor (9),
The well region (10) needs to be formed with a fairly low impurity concentration and a fairly deep diffusion depth. If such a region is heat-treated at the same time as the separation region (3), the heat treatment will take a long time, so the lateral diffusion of the separation region (3) will increase the area occupied on the surface of the epitaxial layer (2). there were.

[0008]

[Means for Solving the Problems] The present invention has been made in view of the various drawbacks mentioned above, and is directed to impurities forming an N+ type buried layer (14) on the surface of a P type substrate (11) and a P+ type isolation region. (15) A step of introducing impurities to form the lower isolation region (16), a step of laminating a P-type epitaxial layer (17) on the substrate (11), and a step of embedding the surface of the epitaxial layer (17). A step of ion-implanting an impurity to form an N-type collector region (19) in a portion corresponding to the layer (14), and applying heat treatment to the substrate (11) to form a lower isolation region (16) and a collector region (19). a step of diffusing N to a desired depth; a step of forming an upper isolation region (20) connected to the lower isolation region (16); a step of forming a base region (23) of the NPN transistor (13);
A high-performance IC with a built-in photodiode is provided by comprising a step of forming an emitter region (24) of a PN transistor (13) and an N+ type diffusion region (27) of a photodiode (26).

[0009]

[Operation] According to the present invention, since the P type epitaxial layer (17) is formed on the P type substrate (11), the P type epitaxial layer (17) is formed on the P type substrate (11).
) There is no need to cancel out P-type impurities due to autodoping. Therefore, a nearly intrinsic high resistivity layer can be easily manufactured.

Furthermore, by obtaining a nearly intrinsic high resistivity layer, the depletion layer can be expanded until it reaches the substrate (11), and the capacitance of the photodiode (26) can be reduced. Furthermore, by expanding the depletion layer until it reaches the substrate (11), the generation of carriers generated outside the depletion layer on the anode side can be reduced. Since the N+ type diffusion region (27) on the cathode side can be formed in a shallow region with high impurity concentration by emitter diffusion, generation of carriers generated outside the depletion layer can be suppressed.
Moreover, the traveling time of generated carriers can be shortened.

Furthermore, the collector region (19) and the lower isolation region (16) are first diffused, and then the upper isolation region (20) is diffused.
), the collector region (19) should be formed with a low impurity concentration and a deep diffusion depth, and the isolation region (15) should be formed with a deep diffusion depth.
It is possible to achieve both the reduction of the area occupied by the

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. First, a P-type silicon single crystal substrate (11) with a specific resistance of 40 to 60 Ωcm is prepared, and the substrate (11
) The surface is thermally oxidized to form an oxide film (12). This oxide film (12) is photoetched and used as a selective mask, and the surface of the substrate (11) is doped with antimony (Sb) which forms the N+ type buried layer (14) of the NPN transistor (13) (FIG. 1).

Next, the selection mask is changed and the buried layer (
14) of the lower separation area (15) so as to surround the separation area (14).
16) is doped with boron (B) to form (FIG. 2). Next, the oxide film (12) used as a selective mask is completely removed, the substrate (11) is placed on a susceptor of an epitaxial growth apparatus, and the substrate (11) is heated by lamp heating.
While applying a high temperature of about 40℃, SiH2C was added to the reaction tube.
By introducing l2 gas and H2 gas, the film thickness is 10~1
A 5μ non-doped epitaxial layer (17) is grown. When grown in this way without doping, the substrate (11
By autodoping boron (B) from ), the entire epitaxial layer (17) can be formed into a P-type layer with a nearly intrinsic resistivity of 200 to 1500 Ω·cm (when completed) (FIG. 3).

Next, the surface of the epitaxial layer (17) is thermally oxidized to form an oxide film (18), which is then photoetched to form a selective mask. And the embedding layer (1
NP on the surface of the epitaxial layer (17) corresponding to 4).
Phosphorus (P) is ion-implanted to form the N-type collector region (19) of the N-transistor (13) (FIG. 4). Next, the entire substrate (11) is heat-treated at 1100°C for several hours to form the collector region (19) and the lower separation region (
16) and diffusing the buried layer (14). Through this diffusion, the lower isolation region (16) is deeply diffused to more than half the thickness of the epitaxial layer (17), and the collector region (16) is deeply diffused to more than half the thickness of the epitaxial layer (17).
9) is deeply diffused until it connects with the N+ type buried layer (14) (FIG. 5).

Next, an upper isolation region (20) of the isolation region (15) is formed from the surface of the epitaxial layer (17),
An epitaxial layer (17) is formed in the first and second island regions (21) and (22) by connecting them to the lower isolation region (16) (FIG. 6). Since the upper isolation region (20) can have a shallower diffusion depth than the lower isolation region (16), lateral diffusion can be reduced accordingly. Therefore, the upper separation area (2
0) is narrower than that of the lower separation region (16) and occupies a smaller area.

Next, P is applied to the surface of the collector region (19).
A base region (23) of an NPN transistor (13) is formed by selectively diffusing type impurities (FIG. 7). This process is
It may also be used for forming the upper separation region (20). Next, N-type impurities are selectively diffused from the surface of the epitaxial layer (17) to form the emitter region (13) of the NPN transistor (13).
24), forming the collector contact region (25) and the N+ type diffusion region (27) of the photodiode (26); After that, a contact hole is formed in the oxide film (18), and the electrode (28) (2) is deposited with Al and photoetched.
9) Arrange (30) (Fig. 8).

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be explained using 7. The difference from the previous embodiment is that the second island region (22) is N-type inverted between the collector region (19) and the second buried layer (31). First, a P-type silicon single crystal substrate (11
) is prepared, and the surface of the substrate (11) is thermally oxidized to form an oxide film (1
2) Form. This oxide film (12) is photoetched and used as a selective mask, and the surface of the substrate (11) is doped with antimony (Sb) which forms the N+ type buried layer (14) of the NPN transistor (13) (FIG. 9).

Next, using the selection mask for forming the buried layer (14) as it is, 10% of phosphorus (P) is formed to form the second buried layer (31) of the NPN transistor (13).
Ion implantation is performed at a dose of about 14 (FIG. 10). Note that the introduction of impurities for the buried layer (14) and the second buried layer (
31) The order of introducing impurities can be reversed. Next, the selection mask is changed and boron (B) is doped to form the lower isolation region (16) of the isolation region (15) so as to surround the buried layer (14) (FIG. 11).

Next, an oxide film (1
2) is completely removed, the substrate (11) is placed on the susceptor of an epitaxial growth apparatus, and the substrate (11) is heated by lamp heating.
By applying a high temperature of about 1140°C to 11) and introducing SiH2Cl2 gas and H2 gas into the reaction tube, a non-doped epitaxial layer (11) with a film thickness of 10 to 15 μm is formed.
7) Grow. When grown in a non-doped manner in this way, the entire epitaxial layer (17) is formed by auto-doping of boron (B) from the substrate (11), with a resistivity of 200 to 1500 Ωcm, which is close to intrinsic, when completed.
- Can be made into a mold layer (FIG. 12).

Next, the surface of the epitaxial layer (17) is thermally oxidized to form an oxide film (18), which is then photoetched to form a selective mask. The N-type collector region (1) of the NPN transistor (13) is then placed on the surface of the epitaxial layer (17) corresponding to the second buried layer (31).
Phosphorus (P) forming 9) is ion-implanted at a dose of about 1014 (FIG. 13).

[0021] Next, the entire substrate (11) is heat treated at 1100°C for several hours to form a collector region (19).
), the lower isolation region (16), the buried layer (14), and the second buried layer (31). Through this diffusion, the lower isolation region (16) is diffused to a depth of about 10 μm to more than half the thickness of the epitaxial layer (17), the collector region (19) is diffused to a depth of 5 to 6 μm, and the second buried layer (31) is diffused to a depth of about 7 μm.
~9μ diffused and connected to each other (Figure 14).

Next, an upper isolation region (20) of the isolation region (15) surrounding the collector region (19) is formed from the surface of the epitaxial layer (17), and a lower isolation region (16) is formed.
An epitaxial layer (17) is formed in the first and second island regions (21) and (22) by connecting them with each other (FIG. 15). Since the upper isolation region (20) can have a shallower diffusion depth than the lower isolation region (16), lateral diffusion can be reduced accordingly. Therefore, the width of the upper separation region (20) is narrower than that of the lower separation region (16), and the occupied area is smaller.

Next, P is applied to the surface of the collector region (19).
A base region (23) of an NPN transistor (13) is formed by selectively diffusing type impurities (FIG. 16). This step may also be used to form the upper isolation region (20). Next, N type impurities are selectively diffused from the surface of the epitaxial layer (17) to form the emitter region (24) of the NPN transistor (13), the collector contact region (25), and the N+ type diffusion region (27) of the photodiode (26). do. After that, contact holes are formed in the oxide film (18), and electrodes (28) (
29) (30) is arranged (Fig. 17).

In the device formed by the manufacturing method described above, the N+ type diffusion region (27) formed on almost the entire surface of the first island region (21) is connected to the P type epitaxial layer (17) and the P type epitaxial layer (17).
A photodiode (26) is formed by forming a junction. The operation of the photodiode (26) will be explained below. When a ground potential (GND) is applied to the electrode (29) of the photodiode (26) and a reverse bias voltage such as +5V is applied to the electrode (28), a depletion layer (32 ) is formed. The width of the depletion layer (32) is 10 μ or more due to the high resistivity of the epitaxial layer (17), and the width of the epitaxial layer (
17) and the isolation region (15) as well as the boundary between the epitaxial layer (17) and the substrate (11). The specific resistance of the substrate (11) is 40 to 60Ω
- If you use a cm size, it can be expanded to the inside of the board (11).

Therefore, an extremely thick depletion layer (32) comparable to the thickness of the epitaxial layer (17) can be obtained.
The capacity of the photodiode (26) can be reduced and the response speed can be increased. In addition, the structure of the present application is an island region (
21) and the isolation region (15), there is no junction capacitance between the N-type island region (4) and the P+-type isolation region (3), which was seen in the example of FIG. The capacity of the photodiode (26) can also be reduced.

On the other hand, electron-hole pairs are generated outside the depletion layer (32) by the incident light, and carriers (33) generated outside the depletion layer are generated.
and is involved in photocurrent. These carriers (33) generated outside the depletion layer diffuse through the P-type or N-type region as shown in FIG. 19 and then reach the depletion layer (32), so the diffusion time deteriorates the response speed of the photodiode (26). It becomes a factor that causes However, the N+ type diffusion region (
27) is a region with high impurity concentration due to the emitter diffusion of the NPN transistor (13), so the carriers (33) generated outside the depletion layer generated in the N+ type diffusion region (27) have an extremely short lifetime and disappear immediately. Moreover, the carriers (33) generated outside the depletion layer that could not be completely annihilated can reach the depletion layer (32) in an extremely short time because the N+ type diffusion region (27) is a shallow region. Therefore, carriers generated outside the depletion layer (33) generated in the N+ type diffusion region (27)
has almost no effect on the response speed of the photodiode (26).

Furthermore, in the P-type substrate (11), most of the incident light is absorbed by the thick depletion layer (32) comparable to the thickness of the epitaxial layer (17).
In 1), the number of carriers (33) generated outside the depletion layer is small. Therefore, the delay current is small and the photodiode (26)
There is no deterioration in the response speed. Further, on the cathode side, the series resistance can be reduced because the electrode (28) is taken out from the N+ type diffusion region (27) with high impurity concentration, and on the anode side, the electrode (29) is taken out from the P+ type isolation region (15) with high impurity concentration. Since it takes out the series resistance can be reduced. Therefore, the speed of the photodiode (26) can be increased.

In the second island region (22), since the N-type collector region (19) inverts the conductivity type of the second island region (22), it is possible to form an NPN transistor (13). Become. Moreover, the collector region (19) and the lower isolation region (16) are formed before the upper isolation region (20) is formed.
), it is necessary to form a region with a low impurity concentration and diffusion depth appropriate for the collector of the NPN transistor (13), and to form an isolation region (13).
5), the area occupied on the surface of the epitaxial layer (17) can be reduced. Therefore, the high performance of the photodiode (26), the coexistence of the NPN transistor (13), and the I
It is possible to reduce the C chip size.

Further, according to the second embodiment, the substrate (11
) The second buried layer (31) formed by diffusion from the surface of the epitaxial layer (17) is connected to the collector region (19) formed by diffusion from the surface of the epitaxial layer (17).
17) can be made thicker and the diffusion time can be shortened. Furthermore, since the impurity concentration of the second buried layer (31) increases as it approaches the substrate (11), the VCE (sat) of the NPN transistor (13) can be reduced.

[0030]

[Effects of the Invention] As explained above, according to the present invention,
■ A P-type epitaxial layer (
17), a high resistivity layer can be stably obtained compared to stacking N-type inverted epitaxial layers.

■ A thick depletion layer (
32), the capacitor of the photodiode (26) can be reduced and the speed can be improved. ■ Island area (2
1) and the isolation region (15) do not form a PN junction, so the capacitor of the photodiode (26) can be reduced. (2) Since a PN junction is formed in the N+ type diffusion region (27) with a shallow high impurity concentration by emitter diffusion, the delay current due to carriers (33) generated outside the depletion layer is small, and the response speed of the photodiode (26) can be improved.

(2) Since most of the incident light can be absorbed by the thick depletion layer (32), less carriers (33) are generated outside the depletion layer in the substrate (11). (2) Since a PN junction is formed in the shallow N+ type diffusion region (27), light with a short wavelength λ of 400 nm can be handled. It has this effect. Therefore, a photodiode (26) with high sensitivity and excellent response speed can be incorporated into the IC.

Furthermore, in the NPN transistor (13), the collector region (19) is formed of a P-type epitaxial layer (
Since the conductivity type of 17) is inverted, NPN type transistors can coexist. Furthermore, since the upper isolation region (20) is formed after sufficiently diffusing the lower isolation region (16) and the collector region (19), it is possible to form a region with a low impurity concentration and diffusion depth appropriate for the collector. , it is possible to simultaneously reduce the area occupied by the separation region (15) on the surface of the epitaxial layer (17).

■ According to the second embodiment, the substrate (11
) The second buried layer (31) formed by diffusion from the surface of the epitaxial layer (17) is connected to the collector region (19) formed by diffusion from the surface of the epitaxial layer (17).
17) can improve the performance of the photodiode (26), the heat treatment time can be shortened, and VCE (sat) can be reduced compared to the first embodiment.

As described above, according to the present invention, a high-performance photodiode (26) can be incorporated into a miniaturized bipolar IC by forming a P-type epitaxial layer (17).

[Brief explanation of the drawing]

FIG. 1 is a first cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 2 is a second cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 3 is a third sectional view illustrating the manufacturing method of the present invention.

FIG. 4 is a fourth sectional view illustrating the manufacturing method of the present invention.

FIG. 5 is a fifth sectional view illustrating the manufacturing method of the present invention.

FIG. 6 is a sixth cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 7 is a seventh cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 8 is an eighth cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 9 is a first drawing illustrating a second embodiment of the present invention.

FIG. 10 is a second drawing illustrating a second embodiment of the present invention.

FIG. 11 is a third drawing illustrating a second embodiment of the present invention.

FIG. 12 is a fourth drawing illustrating a second embodiment of the present invention.

FIG. 13 is a fifth drawing illustrating a second embodiment of the present invention.

FIG. 14 is a sixth drawing illustrating a second embodiment of the present invention.

FIG. 15 is a seventh drawing illustrating a second embodiment of the present invention.

FIG. 16 is an eighth drawing illustrating a second embodiment of the present invention.

FIG. 17 is a ninth drawing illustrating a second embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a photodiode (26).

FIG. 19 is a band diagram of the photodiode (26).

FIG. 20 is a sectional view showing a conventional example.

Claims (7)

[Claims] 1. A step of introducing an impurity to form a buried layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, and forming a lower isolation region of an isolation region of one conductivity type on the surface of the semiconductor substrate. a step of introducing an impurity, a step of stacking an epitaxial layer of one conductivity type on the substrate, and a step of ion-implanting an impurity to form a collector region of the opposite conductivity type in a portion of the surface of the epitaxial layer corresponding to the buried layer. applying a heat treatment to the entire substrate to diffuse the lower isolation region of the isolation region upwardly and the collector region downward; and separating the upper isolation region from the surface of the epitaxial layer. forming a region and connecting it to the lower isolation region to form first and second island regions; forming a base region of one conductivity type on the surface of the second island region; A reverse conductivity type emitter region is provided in the second island region, and a photodiode P emitter region is provided in the first island region.
A method for manufacturing an optical semiconductor device, comprising the step of forming a diffusion region of opposite conductivity type to form an N junction. 2. The substrate has a specific resistance of 40 to 60 Ω·c.
2. The method for manufacturing an optical semiconductor device according to claim 1, wherein m. 3. The epitaxial layer has a specific resistance of 20
2. The method of manufacturing an optical semiconductor device according to claim 1, wherein the resistance is 0 to 1500 Ω·cm. 4. A step of introducing an impurity for forming a buried layer of an opposite conductivity type and an impurity for forming a second buried layer of an opposite conductivity type into the same region of a surface of a semiconductor substrate of one conductivity type, and the semiconductor substrate a step of introducing an impurity to form a lower isolation region of an isolation region of one conductivity type on the surface of the substrate, a step of laminating an epitaxial layer of one conductivity type on the substrate, and a step of forming an epitaxial layer corresponding to the buried layer on the surface of the epitaxial layer. a step of ion-implanting an impurity to form a collector region of the opposite conductivity type in a portion where the substrate is formed; and heat treatment is applied to the entire substrate to diffuse the lower isolation region of the isolation region upward; forming an upper isolation region of the isolation region from the surface of the epitaxial layer, and connecting the lower isolation region to form first and second island regions; a step of forming a base region of one conductivity type on the surface of the second island region;
forming an emitter region of opposite conductivity type in the second island region and a diffusion region of opposite conductivity type forming a PN junction of a photodiode in the first island region. A method for manufacturing a semiconductor device. 5. The epitaxial layer has a specific resistance of 20
5. The method of manufacturing an optical semiconductor device according to claim 4, wherein the resistance is 0 to 1500 Ω·cm. 6. The method of manufacturing an optical semiconductor device according to claim 4, wherein the opposite conductivity type diffusion region of the first island region is formed by emitter diffusion of the second island region. 7. The method of manufacturing an optical semiconductor device according to claim 4, wherein the epitaxial layer is laminated without doping and is formed into a one-conductivity type semiconductor layer by autodoping from the substrate.