JPH04247400A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To find address access time by measuring an oscillation frequency by comprising one oscillation circuit by connecting odd number of RAMs circularly. CONSTITUTION:Addresses 111-115 are set at '1's and other at '0's and the values of lines 106-110 are set so as to be transmitted to lines 117-120 and a line 116. A control line 121 is set at '1'. When the output 101 of a RAM macro circuit 1 is set at '1', the address 117 goes to '0', and the output of a RAM macro circuit 2 to '0', and the address 118 of a RAM 8 to '1' at a RAM macro circuit 3, and the output 104 of a RAM 9 to '0', and the output of a RAM 10 to '1', and the line 110 to '0', and the value is propagated in a value opposite to the one when the line 121 is set at '0'. RAM macros circuits 1-5 form an oscillation circuit because such operation is repeated. The oscillation frequency can be decided by address access and the delay time of gates 16-20. When the addresses 111-115 are set at the least significant bit of bit address, access time in a bit direction can be found. A frequency can be measured from an observation line 122.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, it relates to a semiconductor integrated circuit used for measuring the performance of RAM.

0002

2. Description of the Related Art In recent years, as RAMs have become faster and more highly integrated, as shown in FIG. 2, a logic circuit 29 and a plurality of RAM macros 21 to 28 are mixed on the same memory element 30 to increase speed. It has memory. In order to measure the performance of a RAM macro in this type of memory, for example, as shown in FIG. 28, while read data 126 to 128 are collected in selector 32 and read out from line 129.

0003

[Problems to be Solved by the Invention] In this conventional memory, since RAM access is fast, measuring the access speed in the wafer state causes a large disturbance in the probed waveform, and it is difficult to perform memory tests even after packaging. The timing of the device had to be precisely adjusted, making it difficult to measure accurate access speeds.

An object of the present invention is to provide a semiconductor integrated circuit whose access speed can be accurately measured.

[0005]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention has a plurality of RAMs and an observation terminal for observing readout outputs of the RAMs. The read output of the first RAM is read out from the second RAM.
M is connected to the address input of the second RAM, the read output of the second RAM is connected to the address input of the third RAM, and similar connections are made for the odd number of RAMs such that the read output of the last RAM is connected to the address input of the first RAM. An oscillation circuit is constructed by connecting the address input of the oscillator.

The oscillation frequency is observed through an observation terminal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. RAM macro 1 to RAM macro 5 are composed of RAM circuits 6 to 10 and gates 11 to 15. Address 111 and line 110 are logically summed by gate circuit 11 and sent from line 116 to RAM circuit 6 as one of the addresses. Read data 101 from RAM circuit 6 is ANDed with control signal 121 in gate circuit 16 and sent out from line 106.

Address 112 and line 106 are gate circuit 1
2 is ANDed and sent to the RAM circuit 7 on line 117 as one of the addresses. The read data 102 from the RAM circuit 7 is ANDed with the control signal 121 by the gate circuit 17 and sent out from the line 107. address 1
13 and line 107 are logically ANDed by gate circuit 13 and sent from line 118 to RAM circuit 8 as one of the addresses.

Read data 103 from RAM circuit 8 is logically ANDed with control signal 121 in gate circuit 18 and sent out from line 108 . Address 114 and line 108 are logically ANDed by gate circuit 14 and sent to RAM circuit 9 from line 119 as one of the addresses.

Read data 104 from RAM circuit 9 is ANDed with control signal 121 in gate circuit 19 and sent out from line 109. Address 115 and line 109 are logically ANDed by gate circuit 15 and sent to RAM circuit 10 from line 120 as one of the addresses. Read data 105 from RAM circuit 10 is ANDed with control signal 121 in gate circuit 20 and sent out from line 110 and observation line 122.

In FIG. 1, address signals other than addresses 111 to 115 and read data other than read data 101 to 105 for RAM circuits 6 to 10 and write-related circuits are omitted because they are not directly related to the present invention.

[0012] This embodiment will be explained in more detail with the above configuration. Lines 111-115 are now set to the least significant bits of the word address. First, normal RAM
When functioning as a controller, the line 121 is set to the value "0". Then, the inverted outputs of the gate circuits 16 to 20 have the value “1”.
Therefore, RAM circuits 6 to 10 have address 111.
Values from 115 to 115 are directly input through gate circuits 11 to 15, and RAM macros 1 to 5 are each independently input from normal R.
Functions as an AM. During testing, first the control signal 12
1 as the value “0” and RAM macros 1 to 5 as normal RA
It operates as M, writes the value "0" into the memory cell corresponding to address 0, and writes the value "1" into the memory cell corresponding to addresses other than address 0.

Next, addresses 111 to 115 are set to the value "1".
” (generally in a memory like this configuration, R
AM and logic circuits are mixed, and the address is connected to the logic circuit section, but as shown in the conventional example, it is generally configured so that the address can be directly set for testing. ) The values of lines 106 to 110 are the same as lines 117 to 1.
20 and line 116. Also,
Addresses other than addresses 111 to 115 are fixed to the value 0, for example.

[0014] Here, if the control signal 121 is set to the value 1, then
For example, when the readout output 101 of the RAM circuit 1 has the value "1", this output passes through the gate 16 and the gate 106 and is sent to the address 117 of the RAM circuit 2 as the value "0". In RAM circuit 2, address 117 has the value '0'
Therefore, the value “0” is output from the output 102, and the RA
In the M macro 3, the address 118 of the RAM circuit 8 is set to the value "1". Similarly, the output 1 of the RAM circuit 8 is
03 is the value “1”, and the output 104 of the RAM circuit 9 is the value “0”
, the output 105 of the RAM circuit 10 sends out the value "1".

Since the output 105 has the value "1", the line 11
0 becomes the value “0”, so R in RAM macro 1
The AM circuit 6 now outputs the value “0” and similarly outputs the value “0” from the RAM.
The values "0" and "1" are propagated to macros 2 to 5 as opposite values.

Since the above operations are repeated, RAM macros 1 to 5 become one oscillation circuit. At this time, the oscillation frequency is determined by the address access of RAM macros 1 to 5 and the delay time of gate circuits 16 to 20.

For example, the address access time (in this embodiment, addresses 111 to 115 are word addresses, so the address access time in the word direction) is 1.9 ns, and the delay time of gates 16 to 20 is 0.9 ns. If it is 1ns, the oscillation frequency is (1.9ns+
0.1 ns) x 5 stages x 2 = 20 ns.

Therefore, by measuring the frequency from the observation line 122, the average address access time of RAM macros 1 to 5 can be determined. However, it is assumed that the delay time of the gate circuit is measured separately and is known (for example, by a ring oscillator).

In FIG. 1, addresses 111 to 11
By setting 5 to the least significant bit of the bit address, the access time in the bit direction can be determined.

[0020]

Effects of the Invention As explained above, the present invention provides
In a memory with M macros, by connecting the read data and address inputs of an odd number of RAM macros in a ring to configure one oscillation circuit, it is possible to determine the address access time by measuring the oscillation frequency. It has the effect of becoming.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

1 to 5 RAM macro 6-10 RAM circuit 11-20 Gate circuit 21-28 RAM macro 29 Logic circuit 30 Memory element 31-32 Selector

Claims (1)

[Claims] 1. A semiconductor integrated circuit characterized in that an odd number of RAMs each receiving an address signal and a signal corresponding to an output signal and a control signal from a previous stage are provided, and the odd number of RAMs are connected in a ring.