JPH04249373A - Electrostatic discharge protection device for semiconductor devices - Google Patents
Electrostatic discharge protection device for semiconductor devicesInfo
- Publication number
- JPH04249373A JPH04249373A JP3207933A JP20793391A JPH04249373A JP H04249373 A JPH04249373 A JP H04249373A JP 3207933 A JP3207933 A JP 3207933A JP 20793391 A JP20793391 A JP 20793391A JP H04249373 A JPH04249373 A JP H04249373A
- Authority
- JP
- Japan
- Prior art keywords
- voltage terminal
- conductivity type
- diffusion region
- power supply
- electrostatic discharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体素子の静電放電（
Ｅｌｅｃｔｒｏ − Ｓｔａｔｉｃ Ｄｉｓｃｈａｒｇ
ｅ ； ＥＳＤ）保護装置に関し、特にパツド−電源電
圧端子（ＶＣＣ），パツド−接地電圧端子（ＶＳＳ），
電源電圧端子−接地電圧端子間における静電放電現象を
防止する半導体素子の静電放電保護装置に関するもので
ある。[Industrial Application Field] The present invention relates to electrostatic discharge (electrostatic discharge) of semiconductor devices.
Electro-Static Discharg
e; Regarding ESD) protection devices, especially pad-supply voltage terminal (VCC), pad-ground voltage terminal (VSS),
The present invention relates to an electrostatic discharge protection device for semiconductor devices that prevents electrostatic discharge phenomena between a power supply voltage terminal and a ground voltage terminal.
【０００２】0002
【従来の技術】高集積のＭＯＳ集積回路は電気的な外乱
に対して敏感に反応し、それによつて内部チツプは悪影
響を受ける。特に、瞬間的な静電放電現象からチツプを
保護するために、すべての入出力パツドに保護回路を設
けている。このように入出力パツドに設けた保護回路の
存在は、種々の有益な効果を持つが、１μｍ以下のデザ
インルールにて設計される高集積回路においては、パワ
ーバス、即ち、電源電圧端子（ＶＣＣ）、あるいは接地
電圧端子（ＶＳＳ）で生起する静電放電を無視すること
はできない。BACKGROUND OF THE INVENTION Highly integrated MOS integrated circuits are sensitive to electrical disturbances, which adversely affect the internal chips. In particular, all input/output pads are equipped with protection circuits to protect the chip from momentary electrostatic discharge events. The presence of protection circuits installed on input/output pads in this way has various beneficial effects, but in highly integrated circuits designed with a design rule of 1 μm or less, the power bus, that is, the power supply voltage terminal (VCC ) or the electrostatic discharge that occurs at the ground voltage terminal (VSS) cannot be ignored.
【０００３】電源電圧端子と接地電圧端子との間で起こ
る静電放電に関する研究は、ＩＥＥＥの「ＴＲＡＮＳＡ
ＣＴＩＯＮＳ ＯＮ ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥ
Ｓ」誌上にて、“Ｉｎｔｅｒｎａｌ Ｃｈｉｐ ＥＳＤ
Ｐｈｅｎｏｍｅｎａ Ｂｅｙｏｎｄ ｔｈｅ Ｐｒｏ
ｔｅｃｔｉｏｎ Ｃｉｒｃｕｉｔ ”（ｖｏｌ．３５，
Ｎｏ．１２，ｐｐ ２１３３−２１３９， ＤＥＣ．
１９８８ ）として発表された。図１は、上記論文の内
容の一部で、通常のインバータの断面図を示す。図１Ａ
は、電源電圧端子（ＶＣＣ）から接地電圧端子（ＶＳＳ
）へ起こる静電放電現象を説明する図であり、図１Ｂは
、接地電圧端子（ＶＳＳ）から電源電圧端子（ＶＣＣ）
への静電放電現象を説明する図である。[0003] Research on electrostatic discharge that occurs between a power supply voltage terminal and a ground voltage terminal is based on IEEE's "TRANSA
CTIONS ON ELECTRON DEVICE
In the magazine “Internal Chip ESD
Phenomena Beyond the Pro
tection Circuit” (vol.35,
No. 12, pp 2133-2139, DEC.
1988). FIG. 1 is part of the content of the above paper and shows a cross-sectional view of a typical inverter. Figure 1A
is from the power supply voltage terminal (VCC) to the ground voltage terminal (VSS
), and FIG. 1B is a diagram illustrating the electrostatic discharge phenomenon that occurs from the ground voltage terminal (VSS) to the power supply voltage terminal (VCC).
FIG. 2 is a diagram illustrating an electrostatic discharge phenomenon.
【０００４】図１Ａによれば、ＰＭＯＳトランジスタの
ソース（３）に電源電圧ＶＣＣが連結され、ＮＭＯＳト
ランジスタのソース（５）に接地電圧ＶＳＳが連結され
ている。そこで、接地電圧端子（ＶＳＳ）に対して正（
ｐｏｓｉｔｉｖｅ）のストレスが電源電圧端子（ＶＣＣ
）に加えられると、ＰＭＯＳトランジスタのソース（３
）からＮＭＯＳトランジスタのソース（５）に渡つて存
在する寄生ｐ−ｎ−ｐ−ｎデバイスを通じてストレス電
流（７）が流れる。
これが素子の故障の原因となる。静電放電による電圧は
数ｋＶの値を持ち、上記のようなストレス電流が流れた
部分で故障が発生し、その結果、素子が不良となる。According to FIG. 1A, a source (3) of a PMOS transistor is connected to a power supply voltage VCC, and a source (5) of an NMOS transistor is connected to a ground voltage VSS. Therefore, positive (
The stress on the power supply voltage terminal (VCC
), the source of the PMOS transistor (3
) flows through a parasitic p-n-p-n device that is present across the source (5) of the NMOS transistor. This causes device failure. The voltage caused by electrostatic discharge has a value of several kV, and a failure occurs in the portion where the stress current as described above flows, resulting in a defective element.
【０００５】一方、図１Ｂにおいても、電源電圧端子Ｖ
ＣＣに対してポジテイブのストレスが接地電圧端子ＶＳ
Ｓに加えられると、ＮＭＯＳトランジスタのソース（５
）からＰＭＯＳトランジスタのソース（４）へのストレ
ス電流（８）が流れ、図１Ａの場合と同様な故障と不良
が発生する。このような静電放電によるストレス電流は
、別の通路を通じて流してやらなければならない。On the other hand, also in FIG. 1B, the power supply voltage terminal V
Positive stress with respect to CC is the ground voltage terminal VS
When added to S, the source of the NMOS transistor (5
) flows from the source (4) of the PMOS transistor to the source (4) of the PMOS transistor, causing failures and defects similar to those in FIG. 1A. Stress currents caused by such electrostatic discharge must be routed through separate paths.
【０００６】図２は、従来のパツドと接地電圧端子との
間の静電放電を緩和するための装置の平面構造図である
。同図に示すように、従来の装置では、パツド（２１）
とｎ＋ 拡散領域（２３）との間をメタル（２２）にて
連結し、接地電圧バス（２５）に接続されたｎ＋ 拡散
領域（２４）と、パツド（２１）に連結されたｎ＋ 拡
散領域（２３）との間にフイールド酸化膜（２６）を介
在させた形態をとる。このような構造により、パツドに
静電放電によるストレスが加えられたとき、パツド（２
１）に接続されたｎ＋ 拡散領域（２３）から接地電圧
バス（２５）に接続されたｎ＋拡散領域（２４）にパン
チスルー （ｐｕｎｃｈ−ｔｈｒｏｕｇｈ）が発生し、
ｐ型の基板を含んだ寄生ｎ−ｐ−ｎバイポーラトランジ
スタを通してストレス電流が流れることにより、静電放
電に対する保護の役割をする。FIG. 2 is a plan view of a conventional device for mitigating electrostatic discharge between a pad and a ground voltage terminal. As shown in the figure, in the conventional device, the pad (21)
and the n+ diffusion region (23) are connected by a metal (22), and the n+ diffusion region (24) is connected to the ground voltage bus (25) and the n+ diffusion region (24) is connected to the pad (21). 23), and a field oxide film (26) is interposed therebetween. With this structure, when stress is applied to the pad due to electrostatic discharge, the pad (2
1) punch-through occurs from the n+ diffusion region (23) connected to the ground voltage bus (25) to the n+ diffusion region (24) connected to the ground voltage bus (25).
A stress current flows through a parasitic n-p-n bipolar transistor containing a p-type substrate, thereby providing protection against electrostatic discharge.
【０００７】[0007]
【発明が解決しようとしている課題】しかしながら、上
記従来の装置では、パツドと電源電圧端子との間、また
は電源電圧端子と接地電圧端子との間における静電放電
に対する保護が成されないという問題がある。本発明は
かかる点に鑑みて成されたもので、その目的とするとこ
ろは、半導体素子において、パツドと接地電圧端子間の
みならず、パツドと電源電圧との間、または電源電圧端
子と接地電圧端子との間の静電放電に対しても保護をす
る装置を提供することである。[Problems to be Solved by the Invention] However, the conventional device described above has a problem in that it does not provide protection against electrostatic discharge between the pad and the power supply voltage terminal or between the power supply voltage terminal and the ground voltage terminal. . The present invention has been made in view of the above points, and its purpose is to provide a semiconductor device not only between a pad and a ground voltage terminal, but also between a pad and a power supply voltage, or between a power supply voltage terminal and a ground voltage terminal. It is an object of the present invention to provide a device that also protects against electrostatic discharge between terminals.
【０００８】[0008]
【課題を解決するための手段】上述の課題を解決するた
めに、請求項１に記載の発明は、入出力パツドと電源電
圧端子と接地電圧端子とを有する高集積半導体素子の静
電放電保護装置において、前記入出力パツドに接続され
た第１導電型の第１の拡散領域と、前記第１の拡散領域
とはフイールド酸化膜によつて所定距離離れ、前記電源
電圧端子あるいは前記接地電圧端子に接続された第１導
電型の第２の拡散領域と、前記第２の拡散領域とはフイ
ールド酸化膜によつて所定距離離れ、前記電源電圧端子
あるいは前記接地電圧端子に接続された第１導電型の第
３の拡散領域とを備え、前記第１、第２、及び第３の拡
散領域は第２導電型の半導体基板、あるいは第２導電型
のウエル内に形成されている。[Means for Solving the Problem] In order to solve the above-mentioned problem, the invention according to claim 1 provides electrostatic discharge protection for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal. In the device, a first diffusion region of a first conductivity type connected to the input/output pad and the first diffusion region are separated by a predetermined distance by a field oxide film, and the first diffusion region is connected to the power supply voltage terminal or the ground voltage terminal. A second diffusion region of a first conductivity type connected to the first conductivity type and the second diffusion region are separated by a predetermined distance by a field oxide film, and a first conductivity type connected to the power supply voltage terminal or the ground voltage terminal the first, second, and third diffusion regions are formed in a second conductivity type semiconductor substrate or a second conductivity type well.
【０００９】また、請求項３に記載の発明は、入出力パ
ツドと電源電圧端子と接地電圧端子とを有する高集積半
導体素子の静電放電保護装置において、前記電源電圧端
子あるいは前記接地電圧端子に接続された第１導電型の
第１の拡散領域と、前記第１の拡散領域とはフイールド
酸化膜によつて所定距離離れ、前記入出力パツドに接続
された第１導電型の第２の拡散領域と、前記第２の拡散
領域とはフイールド酸化膜によつて所定距離離れ、前記
接地電圧端子あるいは電源電圧端子に接続された第１導
電型の第３の拡散領域とを備え、前記第１、第２、及び
第３の拡散領域は第２導電型の半導体基板、あるいは第
２導電型のウエル内に形成されている。Further, the invention according to claim 3 provides an electrostatic discharge protection device for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal. The connected first diffusion region of the first conductivity type and the first diffusion region are separated by a predetermined distance by a field oxide film, and the second diffusion region of the first conductivity type connected to the input/output pad is separated from the first diffusion region by a field oxide film. and a third diffusion region of the first conductivity type, which is separated from the second diffusion region by a predetermined distance by a field oxide film and connected to the ground voltage terminal or the power supply voltage terminal; , the second and third diffusion regions are formed in a second conductivity type semiconductor substrate or a second conductivity type well.
【００１０】請求項４に記載の発明は、入出力パツドと
電源電圧端子と接地電圧端子とを有する高集積半導体素
子の静電放電保護装置において、前記入出力パツドに接
続された第１導電型の第１の拡散領域と、前記第１の拡
散領域とはフイールド酸化膜によつて所定距離離れ、前
記電源電圧端子あるいは接地電圧端子に接続された第１
導電型の第２の拡散領域と、前記第２の拡散領域とはフ
イールド酸化膜によつて所定距離離れ、前記接地電圧端
子あるいは電源電圧端子に接続された第１導電型の第３
の拡散領域と、前記第１、第２、及び第３の拡散領域の
各下部に形成され、相互に離隔された第１導電型の第１
、第２、及び第３ウエルとを備える。The invention according to claim 4 provides an electrostatic discharge protection device for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal. The first diffusion region is separated by a predetermined distance from the first diffusion region by a field oxide film, and the first diffusion region is connected to the power supply voltage terminal or the ground voltage terminal.
A second diffusion region of the conductivity type and the second diffusion region are separated by a predetermined distance by a field oxide film, and a third diffusion region of the first conductivity type is connected to the ground voltage terminal or the power supply voltage terminal.
a first diffusion region of a first conductivity type formed under each of the first, second, and third diffusion regions and spaced apart from each other.
, second, and third wells.
【００１１】さらに、請求項６に記載の発明は、入出力
パツドと電源電圧端子と接地電圧端子とを有する高集積
半導体素子の静電放電保護装置において、前記電源電圧
端子あるいは接地電圧端子に接続された第１導電型の第
１の拡散領域と、前記第１の拡散領域とはフイールド酸
化膜によつて所定距離離れ、前記入出力パツドに接続さ
れた第１導電型の第２の拡散領域と、前記第２の拡散領
域とはフイールド酸化膜によつて所定距離離れ、前記接
地電圧端子あるいは電圧電源端子に接続された第１導電
型の第３の拡散領域と、前記第１、第２、及び第３の拡
散領域の各下部に形成され、相互に隔離された第１導電
型の第１、第２、及び第３ウエルとを備える。Furthermore, the invention according to claim 6 provides an electrostatic discharge protection device for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal. A first diffusion region of a first conductivity type, which is separated by a predetermined distance from the first diffusion region by a field oxide film, and a second diffusion region of a first conductivity type connected to the input/output pad. and a third diffusion region of the first conductivity type which is separated from the second diffusion region by a predetermined distance by a field oxide film and connected to the ground voltage terminal or the voltage power supply terminal; , and first, second, and third wells of the first conductivity type formed under each of the third diffusion regions and isolated from each other.
【００１２】0012
【作用】以上の構成において、半導体素子のパツドと接
地電圧端子間のみならず、パツドと電源電圧との間、あ
るいは電源電圧端子と接地電圧端子との間の静電放電に
対しても素子を保護するよう機能する。[Operation] In the above configuration, the device is protected against electrostatic discharge not only between the pad of the semiconductor device and the ground voltage terminal, but also between the pad and the power supply voltage, or between the power supply voltage terminal and the ground voltage terminal. Functions to protect.
【００１３】[0013]
【実施例】以下、添付図面を参照して、本発明に係る好
適な実施例を詳細に説明する。図３Ａは、本発明の実施
例に係る静電放電保護装置の平面構造図であり、図３Ｂ
は、図３Ａにおける切断線Ｘ−Ｙに対する断面構造図で
ある。同図に示すように、本実施例の静電放電保護装置
では、パツド（３１）がメタル（３２）によつて半導体
基板（３０）に形成されたｎ＋ 拡散領域（３３）に接
続されており、電源電圧バス（３９）と接地電圧バス（
３８）は、その下部の半導体基板（３０）に形成された
ｎ＋ 拡散領域（３４）、及び（３５）に各々接続され
ている。電源電圧バス（３９）、及び接地電圧バス（３
８）は、共にメタルから成つており、上記ｎ＋ 拡散領
域（３３，３４，３５）の間にはフイールド酸化膜（４
０）が形成されている。このメタルと拡散領域との接触
は、上記フイールド酸化膜（４０）と拡散領域（３３，
３４，３５）が形成され、厚い層間絶縁膜（４１）にて
覆つた後に形成される接触孔（４２）を通じて成される
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 3A is a plan structural diagram of an electrostatic discharge protection device according to an embodiment of the present invention, and FIG. 3B
3A is a cross-sectional structural diagram taken along cutting line X-Y in FIG. 3A. As shown in the figure, in the electrostatic discharge protection device of this example, a pad (31) is connected to an n+ diffusion region (33) formed in a semiconductor substrate (30) by a metal (32). , the power supply voltage bus (39) and the ground voltage bus (
38) are respectively connected to n+ diffusion regions (34) and (35) formed in the semiconductor substrate (30) below. Power voltage bus (39), and ground voltage bus (3
8) are both made of metal, and there is a field oxide film (4) between the n+ diffusion regions (33, 34, 35).
0) is formed. The contact between this metal and the diffusion region is between the field oxide film (40) and the diffusion region (33,
34, 35) are formed and covered with a thick interlayer insulating film (41), and then through contact holes (42) formed.
【００１４】上記のような構造を採用すると、従来の装
置（図２）とは異なり、パツド（３１）と電源電圧端子
との間、あるいは電源電圧端子と接地電圧端子との間で
静電放電によるストレス電流が生成されても、ｎ＋ 拡
散領域（３３，３４，３５）間のパンチスルー現象によ
る電流通路が存在するので、従来に比べて保護の範囲が
拡大される。If the above structure is adopted, unlike the conventional device (FIG. 2), electrostatic discharge will occur between the pad (31) and the power supply voltage terminal, or between the power supply voltage terminal and the ground voltage terminal. Even if a stress current is generated by the n+ diffusion region (33, 34, 35), a current path exists due to the punch-through phenomenon between the n+ diffusion regions (33, 34, 35), so the range of protection is expanded compared to the conventional one.
【００１５】従つて、パツドと電源電圧端子との間の静
電放電の場合、３０００Ｖ以上の放電電圧に対しても保
護が成され、さらに電源電圧端子と接地電圧端子との間
での静電放電においても、３０００Ｖ以上の放電電圧に
対しても保護が機能する。上記半導体基板（３０）は、
拡散領域の導電タイプとは反対の導電タイプを有するウ
エルにて構成するようにしてもよいことは、当業者には
容易に理解できるところである。Therefore, in the case of electrostatic discharge between the pad and the power supply voltage terminal, protection is achieved even against a discharge voltage of 3000 V or more, and furthermore, in the case of electrostatic discharge between the power supply voltage terminal and the ground voltage terminal, During discharge, protection also functions against discharge voltages of 3000V or higher. The semiconductor substrate (30) is
Those skilled in the art will readily understand that the well may have a conductivity type opposite to that of the diffusion region.
【００１６】＜他の実施例＞図３Ｃは、本発明に係る他
の実施例を説明するための図であり、本他の実施例にお
ける装置は、上記図３Ｂにおいて、ｎ＋拡散領域（３３
，３４，３５）の深度が浅い場合に対して本発明を適用
したものである。ｎ＋ 拡散領域（３３，３４，３５）
が浅いとパンチスルー現象による電流が弱くなり、ｎ＋
拡散領域（３３，３４，３５）と基板（３０）との間
のｎ＋ −ｐ接合面に強電界がかかり、その結果、多量
の熱が発生する。このような現象を防止するために、図
３Ｃに示すように、深度の浅いｎ＋ 拡散領域（４２，
４３，４４）をそれぞれｎ型のウエル（４５，４６，４
７）内に形成する。<Other Embodiments> FIG. 3C is a diagram for explaining another embodiment according to the present invention.
, 34, 35) where the depth is shallow. n+ diffusion region (33, 34, 35)
If the current is shallow, the current due to the punch-through phenomenon becomes weak, and n+
A strong electric field is applied to the n+-p junction between the diffusion regions (33, 34, 35) and the substrate (30), resulting in the generation of a large amount of heat. In order to prevent this phenomenon, as shown in FIG. 3C, a shallow n+ diffusion region (42,
43, 44) into n-type wells (45, 46, 4), respectively.
7) Form within.
【００１７】このように、上記ｎ＋ 拡散領域より相対
的に濃度の低い接合面がｎ型ウエル（４５，４６，４７
）間に形成されるので、上記の電界の影響を軽減するこ
とができる。また、ｎ型ウエル（４５，４６，４７）が
あるので、ｎ＋ 拡散領域間のパンチスルー通路のみな
らず、ｎ型ウエル間のパンチスルー通路も形成されるた
め、さらに大きい電流を流すことができ、深度の浅いｎ
＋ 拡散領域の欠点を補完する。In this way, the junction surface, which has a relatively lower concentration than the n+ diffusion region, forms the n-type well (45, 46, 47).
), the influence of the electric field described above can be reduced. Furthermore, since there are n-type wells (45, 46, 47), not only punch-through paths between the n+ diffusion regions but also punch-through paths between the n-type wells are formed, allowing even larger current to flow. , shallow depth n
+ Compensate for the shortcomings of the diffusion area.
【００１８】[0018]
【発明の効果】以上説明したように、本発明によれば、
高集積半導体素子におけるパツド−接地電圧端子間のみ
ならず、パツド−電源電圧端子間，電源電圧端子−接地
電圧端子間の静電放電によるストレスを抑制することが
できるという効果がある。[Effects of the Invention] As explained above, according to the present invention,
This has the effect of suppressing stress due to electrostatic discharge not only between the pad and the ground voltage terminal in a highly integrated semiconductor device, but also between the pad and the power supply voltage terminal, and between the power supply voltage terminal and the ground voltage terminal.
【図１】半導体素子における静電放電現象を説明するた
めの図、FIG. 1 is a diagram for explaining the electrostatic discharge phenomenon in a semiconductor device,
【図２】従来のパツドと接地電圧端子との間の静電放電
を緩和するための装置の平面構造図、FIG. 2 is a plan view of a conventional device for mitigating electrostatic discharge between a pad and a ground voltage terminal;
【図３Ａ】本発明の実施例に係る静電放電保護装置の平
面構造図、FIG. 3A is a plan view of an electrostatic discharge protection device according to an embodiment of the present invention;
【図３Ｂ】図３Ａにおける切断線Ｘ−Ｙに対する断面構
造図、FIG. 3B is a cross-sectional structural diagram taken along cutting line X-Y in FIG. 3A;
【図３Ｃ】他の実施例に係る装置の断面構造図である。FIG. 3C is a cross-sectional structural diagram of a device according to another embodiment.
７，８ ストレス電流
２１，３１ パツド
３０ 半導体基板
３３〜３５，４２〜４４ ｎ＋ 拡散領域３８ 接
地電圧バス
３９ 電源電圧バス
４０ フイールド酸化膜
４１ 層間絶縁膜
４５〜４７ ｎ型ウエル7, 8 Stress current 21, 31 Pad 30 Semiconductor substrate 33-35, 42-44 n+ diffusion region 38 Ground voltage bus 39 Power supply voltage bus 40 Field oxide film 41 Interlayer insulating film 45-47 N-type well
Claims (7)
圧端子とを有する高集積半導体素子の静電放電保護装置
において、前記入出力パツドに接続された第１の導電型
の第１の拡散領域と、前記第１の拡散領域とはフイール
ド酸化膜によつて所定距離離れ、前記電源電圧端子ある
いは前記接地電圧端子に接続された第１の導電型の第２
の拡散領域と、前記第２の拡散領域とはフイールド酸化
膜によつて所定距離離れ、前記電源電圧端子あるいは前
記接地電圧端子に接続された第１の導電型の第３の拡散
領域とを備え、前記第１、第２、及び第３の拡散領域は
第２の導電型の半導体基板、あるいは第２の導電型のウ
エル内に形成されていることを特徴とする半導体素子の
静電放電保護装置。1. An electrostatic discharge protection device for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal, comprising: a first diffusion region of a first conductivity type connected to the input/output pad; The first diffusion region is separated by a predetermined distance by a field oxide film, and the second diffusion region is of the first conductivity type and is connected to the power supply voltage terminal or the ground voltage terminal.
and a third diffusion region of the first conductivity type, which is separated from the second diffusion region by a predetermined distance by a field oxide film and connected to the power supply voltage terminal or the ground voltage terminal. , wherein the first, second, and third diffusion regions are formed in a semiconductor substrate of a second conductivity type or a well of a second conductivity type. Device.
濃度の拡散領域であることを特徴とする請求項１に記載
の半導体素子の静電放電保護装置。2. The electrostatic discharge protection device for a semiconductor device according to claim 1, wherein the first, second, and third diffusion regions are high concentration diffusion regions.
圧端子とを有する高集積半導体素子の静電放電保護装置
において、前記電源電圧端子あるいは前記接地電圧端子
に接続された第１の導電型の第１の拡散領域と、前記第
１の拡散領域とはフイールド酸化膜によつて所定距離離
れ、前記入出力パツドに接続された第１の導電型の第２
の拡散領域と、前記第２の拡散領域とはフイールド酸化
膜によつて所定距離離れ、前記接地電圧端子あるいは電
源電圧端子に接続された第１の導電型の第３の拡散領域
とを備え、前記第１、第２、及び第３の拡散領域は第２
の導電型の半導体基板、あるいは第２の導電型のウエル
内に形成されていることを特徴とする半導体素子の静電
放電保護装置。3. An electrostatic discharge protection device for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal, wherein a first conductivity type electrostatic discharge protection device is provided that is connected to the power supply voltage terminal or the ground voltage terminal. A first diffusion region and a second diffusion region of a first conductivity type connected to the input/output pad are separated by a predetermined distance from each other by a field oxide film.
and a third diffusion region of the first conductivity type, which is separated from the second diffusion region by a predetermined distance by a field oxide film and connected to the ground voltage terminal or the power supply voltage terminal, The first, second, and third diffusion regions are
1. An electrostatic discharge protection device for a semiconductor device, characterized in that it is formed in a semiconductor substrate of a second conductivity type or a well of a second conductivity type.
圧端子とを有する高集積半導体素子の静電放電保護装置
において、前記入出力パツドに接続された第１の導電型
の第１の拡散領域と、前記第１の拡散領域とはフイール
ド酸化膜によつて所定距離離れ、前記電源電圧端子ある
いは接地電圧端子に接続された第１の導電型の第２の拡
散領域と、前記第２の拡散領域とはフイールド酸化膜に
よつて所定距離離れ、前記接地電圧端子あるいは電源電
圧端子に接続された第１の導電型の第３の拡散領域と、
前記第１、第２、及び第３の拡散領域の各下部に形成さ
れ、相互に離隔された第１の導電型の第１、第２、及び
第３のウエルとを備えることを特徴とする半導体素子の
静電放電保護装置。4. An electrostatic discharge protection device for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal, comprising: a first diffusion region of a first conductivity type connected to the input/output pad; The first diffusion region is separated by a predetermined distance by a field oxide film, and is connected to the power supply voltage terminal or the ground voltage terminal. The region is a third diffusion region of the first conductivity type separated by a predetermined distance by a field oxide film and connected to the ground voltage terminal or the power supply voltage terminal;
The method further comprises first, second, and third wells of a first conductivity type formed under each of the first, second, and third diffusion regions and spaced apart from each other. Electrostatic discharge protection device for semiconductor devices.
記第１、第２、及び第３の拡散領域より低濃度であるこ
とを特徴とする請求項４に記載の半導体素子の静電放電
保護装置。5. The semiconductor device according to claim 4, wherein the first, second, and third wells have a lower concentration than the first, second, and third diffusion regions. Electrostatic discharge protection device.
圧端子とを有する高集積半導体素子の静電放電保護装置
において、前記電源電圧端子あるいは接地電圧端子に接
続された第１の導電型の第１の拡散領域と、前記第１の
拡散領域とはフイールド酸化膜によつて所定距離離れ、
前記入出力パツドに接続された第１の導電型の第２の拡
散領域と、前記第２の拡散領域とはフイールド酸化膜に
よつて所定距離離れ、前記接地電圧端子あるいは電圧電
源端子に接続された第１の導電型の第３の拡散領域と、
前記第１、第２、及び第３の拡散領域の各下部に形成さ
れ、相互に隔離された第１の導電型の第１、第２、及び
第３のウエルとを備えることを特徴とする半導体素子の
静電放電保護装置。6. An electrostatic discharge protection device for a highly integrated semiconductor device having an input/output pad, a power supply voltage terminal, and a ground voltage terminal, wherein a first electrode of a first conductivity type connected to the power supply voltage terminal or the ground voltage terminal is provided. 1 and the first diffusion region are separated by a predetermined distance by a field oxide film,
A second diffusion region of the first conductivity type connected to the input/output pad and the second diffusion region are separated by a predetermined distance by a field oxide film, and are connected to the ground voltage terminal or the voltage power supply terminal. a third diffusion region of the first conductivity type;
It is characterized by comprising first, second, and third wells of a first conductivity type formed under each of the first, second, and third diffusion regions and isolated from each other. Electrostatic discharge protection device for semiconductor devices.
記第１、第２、及び第３の拡散領域より低濃度であるこ
とを特徴とする請求項６に記載の半導体素子の静電放電
保護装置。7. The semiconductor device according to claim 6, wherein the first, second, and third wells have a lower concentration than the first, second, and third diffusion regions. Electrostatic discharge protection device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1128/1991 | 1991-01-23 | ||
| KR1019910001128A KR920015549A (en) | 1991-01-23 | 1991-01-23 | Electrostatic Discharge Protection Device for Semiconductor Devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04249373A true JPH04249373A (en) | 1992-09-04 |
Family
ID=19310210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3207933A Pending JPH04249373A (en) | 1991-01-23 | 1991-08-20 | Electrostatic discharge protection device for semiconductor devices |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH04249373A (en) |
| KR (1) | KR920015549A (en) |
| DE (1) | DE4126047A1 (en) |
| FR (1) | FR2671911A1 (en) |
| GB (1) | GB2252200A (en) |
| IT (1) | IT1251010B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940009605B1 (en) * | 1991-09-16 | 1994-10-15 | 삼성전자 주식회사 | Electrostatic Discharge Protection Device for Semiconductor Memory |
| KR100494343B1 (en) * | 2000-12-27 | 2005-06-13 | 주식회사 하이닉스반도체 | Method of manufacturing a field transistor in a semiconductor memory device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1209271A (en) * | 1967-02-27 | 1970-10-21 | Hitachi Ltd | Improvements in semiconductor devices |
| JPS6134967A (en) * | 1984-05-03 | 1986-02-19 | デイジタル イクイプメント コ−ポレ−シヨン | Input protecting structure for vlsi integrated circuit device |
| JPS62285460A (en) * | 1986-06-03 | 1987-12-11 | Toshiba Corp | input protection circuit |
| US4825280A (en) * | 1986-10-01 | 1989-04-25 | Texas Instruments Incorporated | Electrostatic discharge protection for semiconductor devices |
| JPH061802B2 (en) * | 1989-03-14 | 1994-01-05 | 株式会社東芝 | Semiconductor device |
-
1991
- 1991-01-23 KR KR1019910001128A patent/KR920015549A/en not_active Abandoned
- 1991-07-15 FR FR9108874A patent/FR2671911A1/en not_active Withdrawn
- 1991-08-06 DE DE4126047A patent/DE4126047A1/en not_active Ceased
- 1991-08-13 IT ITMI912252A patent/IT1251010B/en active IP Right Grant
- 1991-08-16 GB GB9117736A patent/GB2252200A/en not_active Withdrawn
- 1991-08-20 JP JP3207933A patent/JPH04249373A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2671911A1 (en) | 1992-07-24 |
| KR920015549A (en) | 1992-08-27 |
| ITMI912252A0 (en) | 1991-08-13 |
| DE4126047A1 (en) | 1992-08-06 |
| GB2252200A (en) | 1992-07-29 |
| IT1251010B (en) | 1995-04-28 |
| ITMI912252A1 (en) | 1993-02-13 |
| GB9117736D0 (en) | 1991-10-02 |
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