JPH04264720A - Formation of wiring - Google Patents

Abstract

PURPOSE:To form a contact part of low resistance, and good barrier properties and step coating properties by burying an Al material uniformly in a connection hole having a barrier metal structure. CONSTITUTION:A TiSi2 layer 7a is formed on a surface of a source/drain region 5 of an MOS transistor, and an inner wall part of a contact hole 11 which is shaped facing the region is coated with a second Ti layer 12. The TiSi2 layer 7a is formed selfmatchingly by reacting the silicon substrate 11 with a first Ti layer (not illustrated) through a deliberately formed SiO2 layer (not illustrated) and shows low sheet resistance and good barrier properties. The second Ti layer 12 slows high wettability to an Al material and has a prevention effect of stress migration. The contact hole 11 can uniformly be buried without generating whiskers by an Al-1% Si layer 13.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method applied to the manufacture of semiconductor devices, and more particularly to a method of uniformly embedding an aluminum material layer in a contact portion having a barrier metal structure.

0002

[Background Art] As the design rules of semiconductor devices are highly reduced as seen in recent VLSI, ULSI, etc., openings are made in interlayer insulating films to connect lower layer wiring and upper layer wiring. The opening diameter of the connection hole has also become finer, and the aspect ratio has come to exceed 1. Upper layer wiring is generally made of aluminum (Al) by sputtering method.
However, it is difficult to achieve sufficient step coverage to fill a contact hole with such a high aspect ratio, and this can lead to wire breakage.

[0003] Therefore, as a measure to improve the lack of step coverage, a high temperature bias sputtering method has been proposed in recent years. This technology is described in, for example, Monthly Semiconductor World, December 1989 issue 186-188.
As introduced in Page (published by Press Journal), a method in which the wafer is heated to several hundred degrees Celsius via a heater block, etc., and sputtering is performed while applying an RF bias via the heater block. It is. According to this method, the step coverage is improved by the reflow effect of Al due to high temperature and the ion bombardment due to bias application, and an Al-based material layer having a flat surface can be formed. The above paper reports that when a Ti layer is provided as a base for an Al-based material layer, the Ti layer contributes to surface migration of Al atoms and achieves excellent step coverage. There is.

0004

By the way, it goes without saying that the Ti layer provided as a base for the Al-based material layer is expected to function as a barrier metal. However, although the Ti layer is an excellent contact material from the viewpoint of achieving a low-resistance ohmic contact, it cannot function as a barrier metal sufficiently by itself. Even if a single Ti layer is interposed between the silicon (Si) substrate and the Al-based material layer, the reaction between Si and Ti,
Since both the reactions of Ti and Al proceed, Si
This is because the occurrence of Al spikes on the substrate cannot be prevented. Therefore, a barrier metal with a two-layer structure (Ti/TiN system), in which a TiN layer is further laminated on the Ti layer, is usually used.
has been adopted. Furthermore, in recent years, a two-layer structure barrier metal (Ti/TiON type) has been proposed in which oxygen is introduced during the formation of the TiN layer to form a TiON layer. This is achieved by segregating oxygen at the grain boundaries of TiN.
This is intended to further enhance the effect of preventing grain boundary diffusion of Al.

However, Ti/Ti is added to the contact portion in advance.
When an ON-based barrier metal is formed and an Al-based material layer is deposited by high-temperature bias sputtering, a problem has arisen in that it becomes difficult to uniformly fill contact holes. For example, as shown in FIG. 7, a connection hole 24 facing the impurity diffusion region 22 is formed on a silicon substrate 21 on which an impurity diffusion region 22 has been formed in advance.
Consider a wafer in which an interlayer insulating film 23 is laminated, and a Ti layer 25 and a TiON layer 26 are sequentially laminated as barrier metals to cover at least the connection hole 24. Even if an attempt is made to deposit, for example, an Al-based material layer 27 on this wafer by high-temperature bias sputtering, the connection holes 24 cannot be uniformly filled, and holes 28 are likely to occur. This is because Al during the high temperature bias sputtering process is in a state intermediate between solid and liquid and is extremely sensitive to the underlying surface morphology. That is, the TiON layer 26 has a columnar crystal structure, and the longitudinal direction of the crystal is oriented almost perpendicular to the film surface, so the surface morphology is rough and the wettability and reactivity with Al-based materials are poor.

Therefore, the present inventors further laminated a Ti layer, which has already been demonstrated to have good wettability and reactivity with Al-based materials, on the TiON layer 26, and formed a barrier metal of Ti/TiON/Ti-based material. We also tried a three-layer structure. However, the surface morphology was not sufficiently improved by the newly laminated Ti layer, and the connection holes 24 were still not filled with the Al-based material uniformly and with good reproducibility.

[0007] As described above, with the conventional techniques, it is difficult to form a contact that can simultaneously satisfy low resistance, high barrier properties, and excellent step coverage. Therefore, the present invention
It is an object of the present invention to provide a wiring forming method that can simultaneously satisfy these requirements.

[0008]

[Means for Solving the Problems] A wiring forming method according to the present invention is proposed to achieve the above-mentioned object, and comprises forming a silicon compound layer and a first titanium-based material layer on a silicon-based substrate. A step of forming a titanium/silicide based material layer by performing heat treatment in an inert gas atmosphere on a base material on which are sequentially formed, and forming an interlayer insulating film on the base body to form a titanium/silicide based material layer a step of opening a connection hole facing the connection hole, a step of covering at least the bottom surface and side wall portion of the connection hole with a second titanium-based material layer, and a step of forming an aluminum-based material layer so as to fill at least the connection hole. It is characterized by having the following.

[0009]

[Operation] The present inventors believed that it would be difficult to uniformly fill the connection hole with an Al-based material layer as long as barrier properties were required for the TiON layer, and the applicant of the present application first published a document in Japanese Unexamined Patent Publication No. 2-2609
Ti formed by the method proposed in Publication No. 30
We focused on the Si2 layer. The method disclosed in the above publication is
Conventional general salicide (SALICIDE) formed for the purpose of reducing contact resistance, diffusion layer resistance, etc.
This is an improved process for forming self-aligned silicide. That is, instead of stacking a Ti layer directly on a silicon-based substrate and performing heat treatment as in the past, the natural oxide film on the silicon substrate is first removed, a silicon compound layer is formed again, and then a Ti layer is layered. After laminating the layers, silicidation is performed by heat treatment in an inert gas atmosphere. In particular, in the process of using a silicon oxide layer formed by thermal oxidation etc. as the silicon compound layer, the silicidation reaction is carried out through the oxide layer, so the applicant of the present application
proposed the name ``rough oxide''. The TiSi2 layer formed by this method does not creep up onto the field oxide film or onto the sidewalls formed on the sidewalls of the gate electrode to achieve an LDD structure in a MOS transistor, but selectively only in the element formation region. Therefore, there is no risk of leakage occurring between the source/drain region and the gate electrode. Furthermore, since the silicidation reaction rate during film formation is low, the film quality is extremely dense and uniform, exhibiting high barrier properties, and has the feature of maintaining low sheet resistance even after high-temperature annealing.

[0010] As is clear from the above explanation, TiSi2 formed by the above method has a sufficiently low sheet resistance and a dense and uniform film quality, so it exhibits excellent performance as a barrier metal. It is expected that it will be possible. Therefore, in the present invention, a titanium/silicide material layer formed by a silicidation reaction between the first titanium material layer and a silicon substrate is used as the barrier metal.

In the present invention, an interlayer insulating film is then formed on the surface of the substrate, and a connection hole is opened facing the titanium/silicide material layer. At this point, the titanium-silicide material layer is exposed at the bottom of the connection hole. However, since the titanium/silicide material layer has a large thermal stress, if the Al material layer is deposited as is, it will cause stress migration. Furthermore, the wettability between the inner wall of the connection hole and the Al-based material layer is also insufficient. Therefore, a second titanium-based material layer is formed to cover the bottom surface and inner wall of the connection hole. As a result, the wettability and reactivity of all the inner walls of the connection holes with the Al-based material layer are improved, and thermal stress is reduced. After that, if an Al-based material layer is applied to the entire surface of the substrate, the Al-based material will gradually penetrate into the connection hole while causing an interfacial reaction with the titanium-based material, filling it uniformly without creating a gap. .

0012

[Embodiments] Preferred embodiments of the present invention will be described below. This example is an example in which the present invention is applied to manufacturing a MOS transistor. This process will be explained with reference to FIGS. 1 to 6.

First, as shown in FIG. 1, a field oxide film 2 is formed on a silicon substrate 1 by, for example, the LOCOS method, and a gate oxide film made of silicon oxide or the like is formed in an element formation region defined by the field oxide film 2. A gate electrode 4 made of DOPOS or the like was formed through the film 3. Next, after performing a first ion implantation to form source/drain regions 5 using the gate electrode 4 as a mask, sidewalls 6 made of silicon oxide or the like are formed in a conventional manner by CVD, RIE, etc. did. Furthermore, after removing the natural oxide film existing on the surface of the element formation region with dilute hydrofluoric acid, a SiO2 film with a thickness of 50 Å is formed on the element formation region and the gate electrode 4 by, for example, thermal oxidation.
Layers 7 and 8 were formed. The reason why the natural oxide film is removed in advance is to make the thickness of the SiO2 layer 7 on the element formation region uniform. Furthermore, the SiO2 layers 7 and 8 are not formed by oxidizing the surface of the substrate as described above, but by, for example, depositing a polycrystalline silicon layer on the entire surface of the substrate and then thermally oxidizing it to form a thick SiO2 layer. , and then etching with dilute hydrofluoric acid to reduce the layer thickness to a desired thickness. Furthermore, using the gate electrode 4 and the sidewalls 6 as masks, a second ion implantation is performed on the SiO2 to increase the impurity concentration in a part of the source/drain region 5.
It went through layer 7. In this way, an LDD structure is achieved. At this time, the SiO2 layer 8 on the gate electrode 4 also functions as a layer to prevent channeling caused by the implanted ions.

Next, as an example, the argon flow rate is 100SC.
CM, gas pressure 0.47 Pa (3.5 mTorr), DC
Ti sputtering was performed under the conditions of sputtering power of 4 kW, substrate temperature of 300° C., and sputtering rate of 3500 Å/min to form a first Ti layer 9 with a thickness of about 300 Å on the entire surface of the substrate, as shown in FIG. did.

Next, lamp annealing is performed on the substrate shown in FIG. 2 at about 650° C. in an Ar atmosphere, and a part of the first Ti layer 9 and the silicon substrate 1 (more precisely, the source/drain region 5) and the gate electrode 4 through the SiO2 layers 7 and 8, respectively, to form Ti.
A Si layer (not shown) was formed. Subsequently, the unreacted portions of the first Ti layer 9 were selectively etched away using, for example, a mixed solution of ammonia and hydrogen peroxide. Further, lamp annealing is performed again at about 900° C. to further react the TiSi layer with the silicon substrate 1 and gate electrode 4, and as shown in FIG.
iSi2 layers 7a and 8a were formed. Here, the reason why the lamp annealing for silicidation is performed in two stages as described above is to form the TiSi2 layers 7a and 8a with good selectivity on the element formation region and the gate electrode. If silicidation is performed at around 900° C. from the beginning, TiSi2 layers 7a and 8a are formed extending over the field oxide film 2 and sidewalls 6, and the TiSi2 layers 7a and 8a are formed between the gate electrode 4 and the source/drain region 5. There is a large risk of increasing leakage current.

Next, as shown in FIG. 4, an interlayer insulating film 10 is formed by depositing silicon oxide or the like on the entire surface of the substrate by CVD, and then the interlayer insulating film 10 is patterned to form source/drain regions. TiSi2 on region 5
A contact hole 11 facing layer 7a was opened. Furthermore, by performing sputtering under the same conditions as when forming the first Ti layer 9, a second Ti layer 12 was formed to a thickness of about 500 Å covering the entire surface of the substrate. As a result, at least the bottom and sidewalls of the contact hole 11 are covered with the second Ti layer 12, and the Al-1%Si layer 13 (see FIG. 5) to be formed later.
The wettability and reactivity between the TiSi2 layer 7a and the TiSi2 layer 7a are improved, and the thermal stress between the TiSi2 layer 7a and the TiSi2 layer 7a is also alleviated.

Next, by two-step sputtering, Al
-1% Si layer 13 was formed. The sputtering atmosphere was Ar flow rate 100SCCM, gas pressure 0.47Pa (3
．． 5mTorr), and the DC sputtering power was 22.7 without substrate heating and bias application in the first stage.
Sputtering was performed at kW to form an Al-1%Si layer 13.
A film was formed to a thickness of about 1000 Å. Subsequently, in the second step, the substrate was heated to approximately 450° C. by bringing the back surface of the substrate into contact with high-temperature Ar gas, and high-temperature bias sputtering was performed while applying RF bias power of 300 V to form Al-1% A Si layer 13 was further formed to a thickness of 3000 Å. As a result, as shown in FIG. 5, an Al-1%Si layer 13 with a thickness of 4000 Å is finally formed on the entire surface of the substrate, and the contact hole 11 is filled uniformly without forming a hole. It was. In addition, Al-
The formation of the 1% Si layer 13 does not necessarily need to go through the two-step process as described above. However, if the substrate is heated to a high temperature from the early stage of film formation, the Al-1%Si layer 13 may grow in an island shape depending on the conditions, so in order to prevent this, the film formation process is divided into two stages. This is a low-temperature process. Thereby, the film quality of the Al-1% Si layer 13 can be further improved. Furthermore, Figure 6
As shown in FIG. 1, the Al-1%Si layer 13 and the second Ti layer 12 were patterned by dry etching using a chlorine gas or the like to form an Al-based electrode 13a having a Ti layer pattern 12a as a base.

In the MOS transistor manufactured in this example, the TiSi2 layers 7a and 8a form the source/
The sheet resistance of the drain region 5 and gate electrode 4 was reduced, and the junction leakage current was significantly reduced even after high-temperature annealing compared to a MOS transistor in which a silicide layer was formed by the conventional SALICIDE method. This is because in the MOS transistor of this example, Ti
This is related to the excellent film quality of the Si2 layers 7a and 8a. FIG. 8 is a graph showing the measurement results of junction leakage current when a voltage of -5.5V was applied to the gate electrode of a MOS transistor held at a predetermined annealing temperature for 30 minutes. The vertical axis represents the junction leakage current (A), and the horizontal axis represents the annealing temperature (°C). The plots of white circles (○) represent data for conventional MOS transistors, and the plots of black squares (■) represent data for the MOS transistor of this example. Represent each. In conventional MOS transistors, TiS is
In addition to agglomeration of i2 crystals and an increase in sheet resistance, resistance to Al spikes deteriorated when the substrate was heated to about 400° C., and junction leakage current sharply increased. However, in the MOS transistor manufactured in this example,
Since the TiSi2 layers 7a and 8a have large crystal grain sizes and dense grain boundaries, even after being heated to 500°C, the T
In addition to suppressing the diffusion of i and Si and keeping the sheet resistance low, the junction leakage current hardly changed and high resistance to Al spikes was maintained. This means that A
In the process of forming the l-1% Si layer 13, high temperature bias
This shows that even after sputtering, the MOS transistor of this example does not suffer any deterioration in characteristics.

It should be noted that the present invention is not limited to the above-described embodiments; for example, as the silicon compound layer, in addition to the above-mentioned SiO2 layer, a silicon nitride layer (Si3
N4) etc. can be used.

[0020]

[Effects of the Invention] As is clear from the above explanation, by applying the present invention, low resistance and high barrier properties are guaranteed by the TiSi2 layer, and excellent step coverage is guaranteed by the second Ti layer. Therefore, it becomes possible to fill the contact hole with high reliability using an Al-based material. therefore,
The present invention is extremely suitable for manufacturing semiconductor devices that require high integration and high performance based on fine design rules.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing an example in which the present invention is applied to manufacturing a MOS transistor having an LDD structure;
A state in which a SiO2 layer is formed on the element formation region and the gate electrode is shown.

2 is a schematic cross-sectional view showing a state in which a first Ti layer is formed on the entire surface of the substrate shown in FIG. 1. FIG.

FIG. 3 is a schematic cross-sectional view showing a state in which a TiSi2 layer is selectively formed on the source/drain region and the gate electrode by a silicidation reaction.

[Figure 4] By patterning the interlayer insulating film, TiSi
FIG. 2 is a schematic cross-sectional view showing a state in which a contact hole facing the 2 layer is opened and a second Ti layer is deposited on the entire surface of the substrate.

[Figure 5] Al-1%S is applied to the entire surface of the substrate shown in Figure 4.
FIG. 3 is a schematic cross-sectional view showing a state in which an i-layer is formed.

FIG. 6 is a schematic cross-sectional view showing a state in which an Al-based electrode is formed by patterning.

FIG. 7 is a schematic cross-sectional view showing a state in which Al-based material is not uniformly filled into a contact hole in a contact portion having a conventional barrier metal structure, resulting in a gap.

FIG. 8 is a characteristic diagram showing a comparison of the annealing temperature dependence of junction leakage current for a MOS transistor manufactured by applying the present invention and a conventional MOS transistor.

[Explanation of symbols]

1...Silicon substrate 4
...Gate electrode 5 ...Source/drain regions 7, 8
...SiO2 layers 7a, 8a...TiSi2 layer 9...first Ti layer 10
...Interlayer insulating film 11 ...Contact hole 12
... Second Ti layer 13 ... Al-1% Si layer 13a
...Al-based electrode

Claims (1)

[Claims] 1. A titanium/silicide based material layer is formed by heat-treating a base body in which a silicon compound layer and a first titanium based material layer are sequentially formed on a silicon based substrate in an inert gas atmosphere. forming an interlayer insulating film on the substrate and opening a connection hole facing the titanium-silicide material layer; and forming at least the bottom and sidewalls of the connection hole with a second titanium-based material layer. 1. A wiring forming method comprising the steps of: coating the contact hole with aluminum; and forming an aluminum-based material layer so as to fill at least the contact hole.