JPH04278481A - Programmable logic device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device (PLD), which is a semiconductor device whose logic operation can be programmed, and particularly to a test mechanism thereof.

0002

2. Description of the Related Art With the rapid progress of digital processing technology and semiconductor technology in recent years, digital processing has been adopted for various types of processing, and its logic circuits have come to be constructed using semiconductor devices. However, when using semiconductor devices, it is necessary to mass produce them in consideration of production efficiency, and it is important to make one device highly versatile. Therefore, according to user requirements,
Programmable logic devices (PLDs) whose operations can be configured have been proposed and are becoming widely used.

[0003] In this PLD, by initializing the same intermediate product (for example, processing such as burning a program), it is possible to set the logic in that product. In order to improve the versatility and design efficiency of such PLDs, a large number of unit cells with the same structure are provided, the logic within these unit cells is set, and the signals to each unit cell are set. Switches provided on the input/output paths of the PLD are set to predetermined values to achieve desired signal processing of the entire PLD.

[0004] Here, in such a PLD as well, as with ordinary semiconductor devices, tests must be performed to determine whether the product functions normally. And P.L.D.
As mentioned above, since various settings are made regarding logic operations, etc., when performing a test, it is necessary to set the logic circuit for testing. That is, P.L.
D has multiple configuration memories for setting wiring for signal transmission and setting logic circuits, and the overall operation can be controlled as desired by setting data in these configuration memories. There is. Therefore, when testing a PLD, test configurations are performed on all configuration memories before test patterns (input signals, control signals) are input. Then, inspection was performed based on the condition of the output signal line.

[0005]

[Problems to be Solved by the Invention] However, test configuration data consists of data set in a large number of configuration memories, and the amount of data is much larger than test pattern data. Therefore, if this test configuration data was stored in a ROM, read out one by one, and transmitted serially, there was a problem in that the test would take a long time. Another problem is that storing a large amount of configuration data increases the capacity of the ROM.

[0006] Particularly in the case of semiconductor devices, since the time required for testing directly affects the manufacturing cost, there is a strong demand for reducing this time.
In other words, it is very important to improve the ease of determination.

The present invention has been made in view of the above problems, and an object thereof is to provide a PLD that is easy to judge.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a plurality of unit cells each of which performs a predetermined unit logic operation, a signal transmission to each unit cell, and a logic system in each unit cell. A configuration memory for setting the contents of calculations, a storage means for storing the basic pattern of configuration memory setting data necessary for testing, and a unit for storing the basic pattern read from this storage means. A decoder that supplies information to a corresponding configuration memory based on cell arrangement pattern information.

[0009]

[Operation] As described above, in the present invention, configuration data for each basic cell type is stored in the ROM. Therefore, by reading the basic pattern configuration memory setting data stored in this ROM and configuring each type, the time required for test configuration can be shortened. .

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS A programmable logic device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration.
It consists of a wiring block 10 and a plurality of unit cells 12.

The wiring block 10 has a large number of switches 20 arranged at the intersections of each signal line, and by turning on/off the switches 20, the connection between the unit cell 12 and the signal line is established. , achieving programmable wiring. On the other hand, a predetermined combinational logic circuit is provided inside each unit cell 12, and the logic of this logic circuit can also be set.

[0013] These settings are made based on the storage state of the configuration memory. That is,
One configuration memory is provided for one setting target, and various settings (configurations) are performed by determining whether a switch is on or off depending on whether the configuration memory is 1 or 0.

Here, as shown in the figure, unit cell 1
2 and the switch that controls the input to it is 1.
It is considered that there are two functional blocks (basic cells 22). Then,
The storage contents of the configuration memory for each basic cell can be classified into predetermined types. Further, each configuration memory 30 can be randomly accessed, and as shown in FIG. 2, its address is specified by a word line and a bit line, respectively.

The configuration memory 30 for each basic cell has 8 bits, and in the basic cell A, the configuration data is "11100010".
”, and in basic cell B, it is “10110000”. In this case, in the present invention, these two types of configuration data are stored in the ROM as 8-bit data, and sequentially written into a predetermined configuration memory. Therefore, the configuration and operation for this purpose will be explained based on FIGS. 3 and 4. In this example, a tester 40 is installed outside the PLD.
The tester 40 instructs writing of configuration data, supplies test pattern data to the PLD after writing, and determines the test result based on the output result.

[0016] Inside the PLD, a clock generator 42 is provided which receives a signal from the tester 40 and outputs a clock signal clk of a predetermined period. The clock signal clk from this clock generator 42 is then supplied to a counter/decoder 44. This counter/decoder 44 receives the clock signal cl.
It consists of a counter that takes in the rising edge of k and sequentially counts up, and a decoder that outputs signals w0 to w5 based on this count value. This signal w0 ~w
5, signals w0 to w4 are addresses of word lines of the configuration memory. Therefore, the output of the counter/decoder 44 specifies the word line of the configuration memory to be accessed. Moreover, the signal w5 is set to H every period of the signals w0 to w4.
, L is repeated.

On the other hand, the clock signal clk from the clock generator 42 is also supplied to the we signal generator 46. This we signal generator 46 generates a pulse signal at a slightly delayed time interval from the rise of the clock signal, and generates 4 pulse signals for 5 clock signal inputs.
Outputs two outputs. That is, among the output signals w0 to w4 from the counter/decoder 44 mentioned above, w1 to w
4 is output, one pulse at a time is generated. And this we signal generator 46
The output signal we from the two AND gates 48a, 48
b. Therefore, this AND gate 48a, 4
8b is supplied with a signal w5 from the counter/decoder 44 and its inverted signal rw5. Therefore, from the AND gates 48a and 48b, w5
Alternatively, the AND gate 48 of the H side of rw5 outputs a pulse when the signal we is H.

The address generation signal from counter/decoder 44 is also supplied to ROM address generator 50. The signal supplied to this ROM address generator 50 is
This corresponds to the signal w0 mentioned above. Then, this ROM address generator 50 responds to this signal by a0
or a1 signals in sequence. And this R
Address a specified by OM address generator 50
The data stored in 0 and a1 is read from the ROM 52. That is, the first signal w of the clock pulse
0 is output, the data stored at address a0 is output, and when the second signal w0 is output, the data stored at address a1 is output.

Here, the data stored in the ROM 52 is configuration data to be written to the configuration memory, and this data is temporarily stored in the data latch section 54. Further, writing of data to the data latch section 54 is performed by a data strobe signal, and this data strobe signal is performed after reading from the ROM 52 is completed.

Therefore, data at ROM address a0 is output from data latch section 54 while signals w1 to w4 are output from counter/decoder 44, and data at ROM address a0 is output from data latch section 54.
While the signals w1 to w4 are being output, the data at address a1 is output.

On the other hand, as mentioned above, the AND gate 48a
The first four pulses of the signal we are output from the AND gate 48b, and the next four pulses of the signal we are output from the AND gate 48b. Since this pulse is supplied to the gates 56a and 56b, during the period when the pulse is supplied,
The data stored in the data latch section 54 is
Configuration memory 3 via 6a or 56b
It will be supplied to 0.

That is, during the period of the first signals w1 to w4, the bit line b0 and the word lines w1 to w4
For the configuration memory specified by R
The data written in address a0 of OM52 will be written, and in the next period of signals w1 to w4, bit line b1 and word lines w1 to w4 will be written.
For the configuration memory specified by R
The data stored in a1 in OM52 will be written.

[0023] When writing of data to the configuration memory is completed, the counter/decoder 44 outputs a carry signal. With this carry signal, the tester 40 knows that the data set for the configuration memory has ended, and performs an actual test.

That is, the tester 40 supplies test pattern data to the PLD, and outputs a signal regarding the result to the PLD.
Receive from LD. Then, in this tester, it is determined whether the resulting data is correct or not, and the PLD is tested.

[0025]

As described above, according to the programmable logic device according to the present invention, the configuration memory is divided into basic cells, and the configuration data for testing of each basic cell is divided according to its type. Since only the data for each type is stored in the ROM, the amount of data stored in the ROM can be reduced. Further, since data from the ROM is written to each configuration memory of the same type using a simple address generator, the overall configuration can be simplified and configuration can be performed efficiently.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an example of a programmable logic device according to the present invention.

FIG. 2 is a layout diagram of a configuration memory in the same embodiment.

FIG. 3 is a configuration diagram for writing data to a configuration memory.

FIG. 4 is a timing chart showing the timing of writing data to a configuration memory.

[Explanation of symbols]

30 Configuration memory 40 Tester 44 Counter/Decoder 52 ROM

Claims (1)

[Claims] 1. A plurality of unit cells each of which performs a predetermined unit logical operation, a configuration memory that transmits signals to each unit cell and sets the contents of the logical operation in each unit cell, and a configuration memory for performing a test. A storage means for storing a basic pattern of necessary configuration memory setting data, and supplying the basic pattern read from the storage means to a corresponding configuration memory based on unit cell arrangement pattern information. A programmable logic device comprising: a decoder;