JPH04287967A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To provide an STC type ultrahighly integrated memory having a small variation in a threshold value voltage of a transistor for a switch due to a misalignment, a dimensional shift at the time of processing. CONSTITUTION:An active region 1 is formed in a cranklike shape, i.e., in a bent shape in which a part crossing from a contact hole 5 for a memory section to a word line 4 is parallel to a bit line 2, and so bent toward a bit line contact hole as to be parallel to the line 4 and again so bent toward next contact hole 5 for the memory section as to be parallel to the line 2. An STC type ultrahighly integrated memory in which a variation in a threshold value voltage of a transistor for a switch due to a misalignment, a dimensional shift at the time of processing can be suppressed to a small value, and a stable operation is obtained, can be manufactured.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout of a stacked capacitive memory cell of a dynamic random access memory (DRAM) suitable for high integration.

0002

[Prior art] "DRAM (Dynamic Random)"
dom AccessMemory), 4 in 3 years
High integration is being realized at a double pace, and there are already 4
Mass production of megabit DRAM has begun. This high degree of integration has been achieved mainly by miniaturizing elements. but,
Due to the reduction in storage capacity associated with miniaturization, signal-to-noise (SN)
) ratio and signal inversion due to the incidence of alpha rays have become apparent, and ensuring reliability has become a major problem. Therefore, instead of the conventional planar cell that uses only the surface of the substrate as a storage capacitor, a part of the storage capacitance can be used as a switching transistor or an Stacked capacitor cell (STC) stacked on a membrane
is used. Then, as an STC structure to realize an even finer cell area,
There is something mentioned in No. 94. FIG. 2 shows its planar layout. 21 is an active region where the channel region and impurity diffusion layer of the switching transistor are formed; 2 is a bit line; 23 is a contact hole for contacting the bit line 2 with the diffusion layer of the substrate; 25 is the storage capacitor lower electrode and the diffusion layer A memory part contact hole 4 is used to connect the word line 4 to the gate electrode of the switching transistor. For simplicity, the memory part contact hole 25
The storage capacitor lower electrode and plate electrode disposed above are omitted. In this STC structure, since the bit line is formed before the storage electrode, there is no need to expose the bit line contact portion when forming the plate electrode, and the plate electrode only needs to cover the memory cell portion. therefore,
The area of the storage capacitor lower electrode is no longer limited by the processing of the plate electrode, and the area of the storage capacitor can be increased while reducing the memory cell area.

0003

However, even in this STC structure, it is very difficult to reduce the distance between bit lines, and there is a limit to the reduction in cell area. An STC structure that solves this problem is described in Japanese Patent Laid-Open No. 1-179449. FIG. 3 shows its planar layout.

31 is an active region where a channel region and an impurity diffusion layer of a switching transistor are formed; 4 is a word line serving as a gate electrode of the switching transistor;
3 is a contact hole for contacting the bit line 2 and the diffusion layer of the substrate; 35 is a memory part contact hole for connecting the storage capacitor lower electrode and the diffusion layer; 6 is a storage capacitor lower electrode;
7 is a plate electrode.

The feature of this structure is that the main part of the active region 1 is located at 4 points with respect to the word line 2 and the bit line 4, which are perpendicular to each other.
5 degrees, and only the part where the memory contact hole 35 opens is arranged parallel to the bit line, and the main part of one active area is parallel to the four nearest active areas. These points are orthogonal.

[0006] Such a shape and arrangement of the active region eliminates layout interference between bit lines, allowing the bit line pitch to be significantly reduced. Furthermore, the memory contact hole can be opened in a self-aligned manner.

However, in this structure, since the active region is inclined with respect to the word line, there is a problem that the threshold voltage of the switching transistor changes greatly due to misalignment or dimensional shift during processing. The reason why the threshold voltage changes due to misalignment is that the ratio of the oblique portion to the channel portion of the transistor changes due to misalignment. The reason why the threshold voltage changes due to dimension shift is that in diagonal transistors where the active area is tilted with respect to the word line, the effective channel width and channel length change depending on the ratio of the word line width L to the active area width W. This is to do so. In the switching transistor used in the memory cell, the word line width L and the active region width W are approximately equal, and both are about the minimum processing size. Extended Abstract of the
Twenty-First Conference on Solid State Devices and Materials, pages 101-104 (Extended Abst
racts of the 21st Conference
nce on Solid State Devices
and Materials, pp. 101-10
As described in 4), in the dimensional region where L and W are approximately equal, the change in threshold voltage due to dimensional change is larger in the diagonal transistor than in the normal transistor.

As memories become smaller and more highly integrated, it becomes increasingly difficult to improve alignment accuracy, and dimensional shifts during processing also tend to become relatively large.

An object of the present invention is to provide an STC type ultra-highly integrated memory in which the threshold voltage of the switching transistor changes little due to misalignment or dimensional shift during processing.

0010

[Means for Solving the Problems] FIG. 1 shows a plan layout diagram of a memory cell according to the present invention. According to the invention, the active area 1 has a crank-like shape. In other words, the part that crosses the word line 4 from the memory contact hole 5 is parallel to the bit line 2, and the part that crosses the word line 4 is parallel to the bit line contact hole 3.
It is bent so as to be parallel to the word line toward the next memory contact hole, and then bent again to be parallel to the bit line toward the next memory contact hole. Moreover, the active regions adjacent in the bit line direction are arranged in a folded manner around the bit line contact hole. Note that a memory array is constructed by using the plane layout diagram shown in FIG. 1 as a unit and repeatedly arranging it many times.

[0011]

[Operation] By configuring the shape and arrangement of the active region as described above, it is possible to suppress changes in the threshold voltage of the switching transistor due to misalignment and dimensional shifts, which are problems with the conventional structure shown in FIG. 3. can.

FIG. 4A shows a switching transistor used in the memory cell of the present invention. No current flows in the shaded part of the active region, and the switching transistor can be considered to be essentially the same as a normal transistor in which the active region and the gate electrode are perpendicular to each other. The change in the threshold voltage of the transistor is smaller than that of the diagonal transistor,
It can be suppressed to the same level as a normal transistor. Furthermore, even if the area of the active region indicated by diagonal lines in FIG. 4A changes due to misalignment, it hardly affects the threshold voltage of the transistor.

Due to the configuration of the memory cell described above, the minimum processing size is 0.4μ, which causes major problems such as misalignment and dimensional shift.
Changes in the threshold voltage of the switching transistor can be suppressed even in a memory cell with a micro area of less than m, and an ultra-highly integrated DRAM can be realized.

[0014]

[Example] FIG. 4C is a comparison of how much the threshold voltages of the switching transistor used in the layout of the present invention and the switching transistor used in the layout of FIG. 3 change due to misalignment. be. Regarding the transistors shown in FIGS. 4A and 4B, respectively,
It shows the threshold voltage when the gate electrode is shifted left and right. On the horizontal axis, a shift to the left is indicated by a minus sign, and a shift to the right is indicated by a plus sign. In the transistor of the conventional structure, the threshold voltage changes by about 0.3 V for an alignment deviation of ±0.1 μm, whereas in the transistor of the present invention, the threshold voltage hardly changes.

FIGS. 5 to 11 are cross-sectional views showing the steps of manufacturing the memory cell according to this embodiment. A cross section taken along the line AA' in FIG. 1 is shown.

First, as shown in FIG. 5, a switching transistor is formed using a conventional MOSFET forming process. Here, 51 is a p-type semiconductor substrate, 52 is an isolation insulating film, 53 is a gate oxide film, 4 is a word line serving as a gate electrode, 54 is an interlayer insulating film, and 55 and 56 are n-type impurity diffusion layers (phosphorus). It is. The entire surface was coated with 50 nm thick SiO2 57 and 400 nm thick Si using a known CVD method.
3N4 was deposited by the CVD method, and S
An insulating film 58 is buried between the word lines by etching i3N4.

Next, as shown in FIG. 6, a portion 55 where the bit line contacts the n-type diffusion layer on the substrate surface and a portion 56 where the storage electrode contacts the n-type diffusion layer on the substrate surface are formed using known photolithography. Openings are made using the method and dry etching method. After depositing polycrystalline silicon containing n-type impurities to a thickness of 400 nm using the CVD method, etching is performed for the film thickness to form polycrystalline silicon 61, Embed 62.

SiO2 71 with a thickness of 50 nm is deposited by CVD, and only the portion where the bit line contacts polycrystalline silicon 61 is opened using known photolithography and dry etching.

Next, bit lines 3 are formed. A laminated film of metal silicide and polycrystalline silicon or tungsten was used as the material for the bit line. On top of this, a thickness of 200n
m of SiO272 is deposited (FIG. 7). SiO272
The bit lines 3 and 3 are processed using known photolithography and dry etching methods to form the bit lines into a desired pattern. Next, SiO2 with a thickness of 150 nm is deposited by CVD and etched by dry etching to form SiO2 sidewall spacers 81 on the sidewalls of the bit lines to insulate the bit lines. Only the portion where the storage electrode contacts the polycrystalline silicon 62 is opened using known photolithography and dry etching methods (FIG. 8).

[0020] 50 nm thick Si3N491 and 3
00 nm of SiO2 92 is deposited by CVD (FIG. 9). After Si3N491 and SiO2 92 are anisotropically etched using a resist pattern not shown, polycrystalline silicon 101 containing n-type impurities and having a thickness of 50 nm is deposited by CVD. A resist 102 is embedded in the recess (FIG. 10).

Polycrystalline silicon 101 not covered with resist is etched anisotropically. Then resist 10
2 and further remove SiO2 on the memory cell area.
By removing 92, polycrystalline silicon 101 is used as a storage electrode. A capacitor insulating film 111 is formed by depositing Ta2O5 by CVD.

Next, tungsten is deposited to form the plate electrode 7. This plate electrode 7 can be made of polycrystalline silicon, a high melting point metal other than tungsten, high melting point metal silicide, or the like. Although not shown in the drawings, wiring metal is then further laminated on the plate electrode.

Through the steps described above, a memory cell as shown in FIG. 11 is completed.

FIG. 12 shows an improved layout of the plate electrode 7 shown in FIG. 1, and has a structure in which the plate electrode is separated in parallel with the word line. This structure in which the plate electrodes are separated is described in IEE International Solid State Circuit Conference, 1989, pp. 238-239 (
1989 IEEE International So
lid State Circuits Conference
ence, pp. 238-239), and has a structure that can realize a high S/N ratio.

FIG. 13 also shows an improved layout of the plate electrode 7 of FIG. 12. The layout of the plate electrodes is different from that in FIG. 12, and has a structure in which the plate electrodes are separated in parallel with the bit lines. The effect is the same as that of the embodiment shown in FIG. 7, and a high S/N ratio can be achieved.

[0026]

Effects of the Invention According to the present invention, changes in the threshold voltage of a switching transistor due to misalignment or dimensional shift during processing can be suppressed to a small level, and a stable operating S
It becomes possible to manufacture a TC type ultra-highly integrated memory.

The process of manufacturing the memory according to the present invention is no different from the conventional method, and only the planar layout needs to be changed. This change in planar layout does not impair the degree of integration.

Furthermore, according to the planar layout of the present invention,
Compared to conventional structures with diagonal active regions, this method also has the effect of making process control easier through cross-sectional observation.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a memory cell of the present invention.

FIG. 2 is a first plan view of a conventional STC cell.

FIG. 3 is a second plan view of a conventional STC cell.

FIG. 4A is a plan view of a main part of a switching transistor of a memory cell according to the present invention.

FIG. 4B is a plan view of a main part of a conventional STC cell switch transistor.

FIG. 4C is a diagram showing a change in threshold voltage due to misalignment between a switching transistor of a memory cell of the present invention and a switching transistor of a memory cell having a conventional structure.

FIG. 5 is a first cross-sectional view showing the steps of an embodiment of the present invention.

FIG. 6 is a second sectional view showing the steps of an embodiment of the present invention.

FIG. 7 is a third cross-sectional view showing the steps of an embodiment of the present invention.

FIG. 8 is a fourth sectional view showing the steps of an embodiment of the present invention.

FIG. 9 is a fifth sectional view showing the steps of an embodiment of the present invention.

FIG. 10 is a sixth sectional view showing the steps of an embodiment of the present invention.

FIG. 11 is a seventh cross-sectional view showing the steps of an embodiment of the present invention.

FIG. 12 is a plan view of a second embodiment of the invention.

FIG. 13 is a plan view of a third embodiment of the invention.

[Explanation of symbols]

1... Active area, 2... Bit line, 3, 23, 33...
Contact hole, 4... Word line, 5, 25, 35... Memory part contact hole, 6... Storage capacitor lower electrode, 7... Plate electrode, 51... P-type semiconductor substrate, 52... Element isolation oxide film, 53... Gate oxidation Film, 55, 56...n-type impurity diffusion layer, 54, 57, 71, 72, 81, 92... SiO2,
58, 91...Si3N4, 61, 62, 101...polycrystalline silicon, 102...resist, 111...capacitor insulating film.

Claims (1)

[Claims] 1. In a semiconductor memory device in which the minimum unit is one switching transistor and one charge storage capacitor, the shape of the active region of the switching transistor is such that a portion crossing a word line from a memory contact hole is a bit. It is characterized by being parallel to the bit line, bent to be parallel to the word line toward the bit line contact hole, and bent again to be parallel to the bit line toward the next memory contact hole. Semiconductor storage device.