JPH04299822A - Semiconductor wafer and manufacture thereof - Google Patents
Semiconductor wafer and manufacture thereofInfo
- Publication number
- JPH04299822A JPH04299822A JP8971391A JP8971391A JPH04299822A JP H04299822 A JPH04299822 A JP H04299822A JP 8971391 A JP8971391 A JP 8971391A JP 8971391 A JP8971391 A JP 8971391A JP H04299822 A JPH04299822 A JP H04299822A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- gaas
- thermal expansion
- coefficient
- substance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000000126 substance Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 22
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 70
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052681 coesite Inorganic materials 0.000 description 7
- 229910052906 cristobalite Inorganic materials 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 229910052682 stishovite Inorganic materials 0.000 description 7
- 229910052905 tridymite Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000007791 liquid phase Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、大口径のＧａＡｓウェ
ーハとその製造方法に係り、特に、エピタキシャル成長
後のそりを改善するウェーハおよびその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-diameter GaAs wafer and a method for manufacturing the same, and more particularly to a wafer and a method for manufacturing the same that improve warpage after epitaxial growth.
【０００２】0002
【従来の技術】ＧａＡｓ（ガリウム砒素）ウェーハの表
面に、ＧａＡｌＡｓ（ガリウムアルミニウム砒素）等の
単結晶膜をヘテロエピタキシャル成長させる技術は、現
在、ＬＥＤ（発光ダイオード）、ＬＤ（レーザーダイオ
ード）等の光デバイスの特性を左右する非常に重要な技
術となっている。[Prior Art] Technology for heteroepitaxially growing a single crystal film such as GaAlAs (gallium aluminum arsenide) on the surface of a GaAs (gallium arsenide) wafer is currently used in optical devices such as LEDs (light emitting diodes) and LDs (laser diodes). It is a very important technology that influences the characteristics of
【０００３】これらの光デバイスに用いられるＧａＡｓ
ウェーハには、これまで、砒素の蒸気圧を制御しながら
単結晶の成長を行うＨＢ法（水平ブリッジマン法）によ
り製造された直径２インチのものが主として用いられて
きた。GaAs used in these optical devices
Until now, wafers with a diameter of 2 inches have been mainly used, which are manufactured by the HB method (horizontal Bridgman method), which grows a single crystal while controlling the vapor pressure of arsenic.
【０００４】さらに今日では、３、４インチ等の大口径
のＧａＡｓウェーハを用いることにより、製造する光デ
バイスのコストダウンを図る試みもなされている。Furthermore, attempts are now being made to reduce the cost of manufactured optical devices by using GaAs wafers of large diameter, such as 3 or 4 inches.
【０００５】[0005]
【発明が解決しようとする課題】しかしながらＧａＡｓ
ウェーハの表面に、ＧａＡｌＡｓ等の単結晶膜を高温で
ヘテロエピタキシャル成長させると、熱膨張係数が異な
る異種物質をＧａＡｓウェーハの表面に密着させている
ため、室温に戻したときにウェーハと単結晶膜との収縮
量の差によってウェーハにそりを生じてしまうという問
題があった。[Problem to be solved by the invention] However, GaAs
When a single crystal film such as GaAlAs is grown heteroepitaxially on the surface of a wafer at high temperature, different materials with different coefficients of thermal expansion are brought into close contact with the surface of the GaAs wafer. There was a problem in that the wafer would warp due to the difference in the amount of shrinkage.
【０００６】このウェーハのそりはウェーハが大口径化
するほど大きくなるため、大口径のウェーハにおいては
、ヘテロエピタキシャル成長工程後のウェーハ加工工程
において、そりのために加工プロセスを通すことが不可
能になる場合があった。[0006] This wafer warpage increases as the diameter of the wafer increases, so in the case of large diameter wafers, it becomes impossible to pass through the processing process due to the warpage in the wafer processing step after the heteroepitaxial growth step. There was a case.
【０００７】本発明は前記事情に鑑みてなされたもので
、直径が４インチ等の大口径のものでもそりの量が少な
いウェーハおよびその製造方法を提供することを目的と
する。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wafer with a small amount of warpage even when the diameter is large, such as 4 inches, and a method for manufacturing the same.
【０００８】[0008]
【課題を解決するための手段】請求項１記載の半導体ウ
ェーハでは、ＧａＡｓウェーハの一方の面に、ＧａＡｓ
と異なる熱膨張係数を有する物質を常温より高温で被覆
させたことを課題解決の手段とした。Means for Solving the Problems In the semiconductor wafer according to claim 1, a GaAs wafer is formed on one surface of the GaAs wafer.
The solution was to coat the material with a material with a different coefficient of thermal expansion at a temperature higher than room temperature.
【０００９】請求項２記載の半導体ウェーハの製造方法
では、ＧａＡｓウェーハの一方の面に、ＧａＡｓより熱
膨張係数が小さい物質を常温より高温で被覆した後、上
記ＧａＡｓウェーハの他方の面に、ＧａＡｓより熱膨張
係数が小さい物質をエピタキシャル成長させたことを課
題解決の手段とした。In the method for manufacturing a semiconductor wafer according to claim 2, one surface of the GaAs wafer is coated with a material having a coefficient of thermal expansion smaller than GaAs at a temperature higher than normal temperature, and then the other surface of the GaAs wafer is coated with a material having a coefficient of thermal expansion smaller than that of GaAs. The solution was to epitaxially grow a material with a smaller coefficient of thermal expansion.
【００１０】請求項３記載の半導体ウェーハの製造方法
では、ＧａＡｓウェーハの一方の面に、ＧａＡｓより熱
膨張係数が大きい物質を常温より高温で被覆した後、上
記ＧａＡｓウェーハの他方の面に、ＧａＡｓより熱膨張
係数が大きい物質をエピタキシャル成長させたことを課
題解決の手段とした。In the method for manufacturing a semiconductor wafer according to claim 3, one surface of the GaAs wafer is coated with a material having a coefficient of thermal expansion larger than that of GaAs at a temperature higher than normal temperature, and then the other surface of the GaAs wafer is coated with a material having a coefficient of thermal expansion larger than that of GaAs. The solution was to epitaxially grow a material with a higher coefficient of thermal expansion.
【００１１】ＧａＡｓウェーハの一方の面に、ＧａＡｓ
と異なる熱膨張係数を有する物質を被覆させるには、ス
パッタリング、ＣＶＤ法（化学的気相成長法）、ＰＶＤ
（物理的蒸着法）、プラズマＣＶＤ法等の手法を用いて
ウェーハにコーティングする方法が好ましい。[0011] GaAs is deposited on one side of the GaAs wafer.
Sputtering, CVD (chemical vapor deposition), PVD can be used to coat materials with different thermal expansion coefficients.
A method of coating a wafer using a method such as a physical vapor deposition method or a plasma CVD method is preferable.
【００１２】また、ＧａＡｓウェーハの他方の面にエピ
タキシャル成長膜を形成する方法としては、ＭＯ−ＣＶ
Ｄ法やハイドライド法又はクロライド法のような気相を
利用したＶＰＥ法（気相エピタキシャル法）、液相を利
用したＬＰＥ法（液相エピタキシャル法）等が好適に用
いられる。[0012] Furthermore, as a method for forming an epitaxially grown film on the other surface of the GaAs wafer, MO-CV
A VPE method (vapor phase epitaxial method) using a gas phase such as the D method, a hydride method, or a chloride method, an LPE method (liquid phase epitaxial method) using a liquid phase, etc. are preferably used.
【００１３】なお、上記ウェーハの片面に、ＧａＡｌＡ
ｓをエピタキシャル成長させる場合には、上記ウェーハ
の他方の面に、ＧａＡｓと反応性が小さいＳｉＯ２，Ｓ
ｉ３Ｎ４等を被覆するのが望ましい。[0013] Note that on one side of the wafer, GaAlA
When epitaxially growing s, SiO2, S, which has low reactivity with GaAs, is grown on the other side of the wafer.
It is desirable to coat with i3N4 or the like.
【００１４】[0014]
【作用】ＧａＡｓウェーハの一方の面に、ＧａＡｓと異
なる熱膨張係数を有する物質を常温より高温で被覆させ
ると、室温に戻した時、熱膨張係数の差によりそりを生
じる。このそりは、ＧａＡｓより熱膨張係数が小さい物
質を被覆した場合、その物質が付着された面が凸となっ
ている。[Operation] When one surface of a GaAs wafer is coated with a substance having a coefficient of thermal expansion different from that of GaAs at a temperature higher than room temperature, warping occurs due to the difference in coefficient of thermal expansion when the temperature is returned to room temperature. When this warp is coated with a material having a coefficient of thermal expansion smaller than that of GaAs, the surface to which the material is attached becomes convex.
【００１５】次にウェーハの他方の面に、ＧａＡｓより
熱膨張係数が小さい物質をエピタキシャル成長させると
、エピタキシャル成長させた面が凸となってそりを生じ
ようとする。しかしながらウェーハの反対面には、Ｇａ
Ａｓより熱膨張係数が小さい物質が被覆してあり、その
物質が被覆された面が凸となってそりを生じているため
、エピタキシャル成長後の室温時のウェーハのそりは緩
和される。Next, when a material having a coefficient of thermal expansion smaller than GaAs is epitaxially grown on the other surface of the wafer, the epitaxially grown surface tends to become convex and warp. However, on the other side of the wafer, Ga
Since the wafer is coated with a material having a coefficient of thermal expansion smaller than As, and the surface covered with the material is convex and warps, the warpage of the wafer at room temperature after epitaxial growth is alleviated.
【００１６】一方、ＧａＡｓウェーハの一方の面に、Ｇ
ａＡｓより熱膨張係数が大きい物質を被覆した場合は、
その物質が付着された面が凹となってそりを生じる。On the other hand, on one side of the GaAs wafer, G
When coated with a material with a larger coefficient of thermal expansion than aAs,
The surface to which the substance is attached becomes concave and warps.
【００１７】次にウェーハの他方の面に、ＧａＡｓより
熱膨張係数が大きい物質をエピタキシャル成長させると
、エピタキシャル成長させた面が凹となってそりを生じ
ようとする。しかしながらウェーハの反対面には、Ｇａ
Ａｓより熱膨張係数が大きいい物質が被覆してあり、そ
の物質が被覆された面が凹となってそりを生じているた
め、エピタキシャル成長後の室温時のウェーハのそりは
緩和される。Next, when a material having a coefficient of thermal expansion larger than GaAs is epitaxially grown on the other surface of the wafer, the epitaxially grown surface tends to become concave and warp. However, on the other side of the wafer, Ga
Since the wafer is coated with a substance having a coefficient of thermal expansion larger than that of As, and the surface covered with the substance is concave and warps, the warpage of the wafer at room temperature after epitaxial growth is alleviated.
【００１８】[0018]
【実施例】以下、図面を参照して本発明の半導体ウェー
ハとその製造方法について詳しく説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor wafer of the present invention and its manufacturing method will be explained in detail below with reference to the drawings.
【００１９】（実施例１）図１ないし図３は、請求項２
の半導体ウェーハの製造方法の一実施例を説明するため
の工程図である。(Embodiment 1) FIGS. 1 to 3 are according to claim 2.
FIG. 3 is a process diagram for explaining an example of a method for manufacturing a semiconductor wafer.
【００２０】まず図１に示すように直径７６ｍｍ、厚さ
２５０μｍのＧａＡｓウェーハ１を用意した。First, as shown in FIG. 1, a GaAs wafer 1 having a diameter of 76 mm and a thickness of 250 μm was prepared.
【００２１】次いでＧａＡｓウェーハの片面に、プラズ
マＣＶＤ法により４００℃、１時間の条件で図２（ａ）
に示すようにＳｉＯ２膜２を約２μｍコーティングした
。Next, one side of the GaAs wafer was subjected to plasma CVD at 400° C. for 1 hour as shown in FIG. 2(a).
As shown in the figure, a SiO2 film 2 of about 2 μm was coated.
【００２２】得られたウェーハ１は、室温では図２（ｂ
）に示すようにＳｉＯ２膜２がコーティングされた面が
凸となって約３３０μｍそった。The obtained wafer 1 has the shape shown in FIG. 2(b) at room temperature.
), the surface coated with the SiO2 film 2 was convex and warped by about 330 μm.
【００２３】次に、このウェーハ１の他面に、ＬＰＥ法
（液相エピタキシャル法）によりＧａＡｌ０．５Ａｓ０
．５膜３を約１００μｍエピタキシャル成長させた。Next, GaAl0.5As0 is deposited on the other surface of the wafer 1 by the LPE method (liquid phase epitaxial method).
．． 5 film 3 was epitaxially grown to a thickness of about 100 μm.
【００２４】得られたウェーハは、図３に示すようにＧ
ａＡｌ０．５Ａｓ０．５膜３が成長した面が凸となって
約６５０μｍそった。The obtained wafer was subjected to G as shown in FIG.
The surface on which the aAl0.5As0.5 film 3 was grown was convex and warped by about 650 μm.
【００２５】また、比較例として、直径７６ｍｍ、厚さ
２５０μｍのＧａＡｓウェーハ１の片面にＧａＡｌ０．
５Ａｓ０．５膜３を実施例１と同様の条件で約１００μ
ｍエピタキシャル成長させた。As a comparative example, GaAl0.
A 5As0.5 film 3 of about 100μ was formed under the same conditions as in Example 1.
m epitaxially grown.
【００２６】得られたウェーハは、図４に示すようにＧ
ａＡｌ０．５Ａｓ０．５膜３が成長した面が凸となって
約１０００μｍそった。The obtained wafer was subjected to G as shown in FIG.
The surface on which the aAl0.5As0.5 film 3 was grown was convex and warped by about 1000 μm.
【００２７】以上の結果より、ＧａＡｓウェーハ１の片
面にＳｉＯ２膜２をコーティングすることにより、Ｇａ
Ａｌ０．５Ａｓ０．５膜３が成長したことによるウェー
ハ１のそりを低減できることが判明した。From the above results, by coating one side of the GaAs wafer 1 with the SiO2 film 2, Ga
It has been found that warping of the wafer 1 due to the growth of the Al0.5As0.5 film 3 can be reduced.
【００２８】（実施例２）直径７６ｍｍ、厚さ２５０μ
ｍのＧａＡｓウェーハ１の片面に、ＣＶＤ法により４５
０゜Ｃ、１．５時間の条件でＳｉＯ２膜２’を約４μｍ
コーティングした。(Example 2) Diameter 76mm, thickness 250μ
45 m by CVD method on one side of a GaAs wafer 1.
The SiO2 film 2' was heated to about 4 μm under the conditions of 0°C and 1.5 hours.
Coated.
【００２９】得られたウェーハは、図５に示すようにＳ
ｉＯ２膜２’がコーティングされた面が凸となって約６
６０μｍそった。The obtained wafer is S as shown in FIG.
The surface coated with the iO2 film 2' is convex and approximately 6
It was shaved by 60 μm.
【００３０】次に、このウェーハ１の他面に、ＬＰＥ（
液相エピタキシャル法）法により実施例１と同様の条件
でＧａＡｌ０．５Ａｓ０．５膜３’を約１００μｍエピ
タキシャル成長させた。Next, on the other side of this wafer 1, LPE (
A GaAl0.5As0.5 film 3' was epitaxially grown to a thickness of about 100 μm under the same conditions as in Example 1 using the liquid phase epitaxial method.
【００３１】得られたウェーハは、図６に示すようにＧ
ａＡｌ０．５Ａｓ０．５膜３’が成長した面が凸となっ
て約３３０μｍそった。The obtained wafer was subjected to G as shown in FIG.
The surface on which the aAl0.5As0.5 film 3' was grown was convex and warped by about 330 μm.
【００３２】この結果からも、ＧａＡｓウェーハ１の片
面にＳｉＯ２膜２’をコーティングすることにより、Ｇ
ａＡｌ０．５Ａｓ０．５膜３が成長したことによるウェ
ーハ１のそりを低減できることが判った。This result also shows that by coating one side of the GaAs wafer 1 with the SiO2 film 2', the G
It has been found that the warping of the wafer 1 due to the growth of the aAl0.5As0.5 film 3 can be reduced.
【００３３】[0033]
【発明の効果】以上説明したように本発明の半導体ウェ
ーハとその製造方法では、ＧａＡｓウェーハの一方の面
に、ＧａＡｓと異なる熱膨張係数を有する物質を常温よ
り高温で被覆させて常温においてそりを生じさせたもの
であるため、ウェーハの他方の面にＧａＡｓより熱膨張
係数が小さい物質をエピタキシャル成長させたい場合は
、予め上記ＧａＡｓウェーハの一方の面にＧａＡｓより
熱膨張係数が小さい物質を被覆して被覆面を凸としてお
き、ウェーハの他方の面にＧａＡｓより熱膨張係数が大
きい物質をエピタキシャル成長させたい場合は、予め上
記ＧａＡｓウェーハの一方の面にＧａＡｓより熱膨張係
数が大きい物質を被覆して被覆面を凹としておくことに
より、エピタキシャル成長膜形成後の常温でのウェーハ
のそりを緩和することができる。As explained above, in the semiconductor wafer and its manufacturing method of the present invention, one surface of the GaAs wafer is coated with a material having a coefficient of thermal expansion different from that of GaAs at a temperature higher than room temperature, thereby preventing warping at room temperature. Therefore, if you want to epitaxially grow a substance with a coefficient of thermal expansion smaller than GaAs on the other side of the wafer, coat one side of the GaAs wafer with a substance with a coefficient of thermal expansion smaller than GaAs in advance. If you want to epitaxially grow a material with a higher coefficient of thermal expansion than GaAs on the other surface of the wafer with the coated surface convex, coat one surface of the GaAs wafer with a material with a higher coefficient of thermal expansion than GaAs in advance. By making the surface concave, warping of the wafer at room temperature after epitaxial growth film formation can be alleviated.
【００３４】従って本発明の半導体ウェーハとその製造
方法によれば、直径が４インチ等の大口径のウェーハに
おいても、ヘテロエピタキシャル成長工程後のウェーハ
のそりが少ないため、引き続き行われる加工工程におい
て、不良を生じる確率が少ない。Therefore, according to the semiconductor wafer and its manufacturing method of the present invention, even in a large diameter wafer such as 4 inches, there is little warpage of the wafer after the heteroepitaxial growth process, so that defects can be avoided in the subsequent processing process. The probability of occurrence is low.
【図１】実施例１の半導体ウェーハの製造方法を説明す
るための工程図である。FIG. 1 is a process diagram for explaining a method for manufacturing a semiconductor wafer of Example 1.
【図２】実施例１の半導体ウェーハの製造方法を説明す
るための工程図である。FIG. 2 is a process diagram for explaining the method for manufacturing a semiconductor wafer of Example 1.
【図３】実施例１の半導体ウェーハの製造方法を説明す
るための工程図である。FIG. 3 is a process diagram for explaining the method for manufacturing a semiconductor wafer of Example 1.
【図４】比較例の半導体ウェーハを示す断面図である。FIG. 4 is a cross-sectional view showing a semiconductor wafer of a comparative example.
【図５】実施例２の半導体ウェーハの製造方法を説明す
るための工程図である。FIG. 5 is a process diagram for explaining a method for manufacturing a semiconductor wafer of Example 2.
【図６】実施例２の半導体ウェーハの製造方法を説明す
るための工程図である。FIG. 6 is a process diagram for explaining a method for manufacturing a semiconductor wafer of Example 2.
１ ＧａＡｓウェーハ ２ ＳｉＯ２膜 ３ ＧａＡｌ０．５Ａｓ０．５膜 1 GaAs wafer 2 SiO2 film 3 GaAl0.5As0.5 film
Claims (3)
Ａｓと異なる熱膨張係数を有する物質を常温より高温で
被覆してなることを特徴とする半導体ウェーハ。Claim 1: A GaAs wafer is coated with Ga on one side.
A semiconductor wafer characterized by being coated with a substance having a coefficient of thermal expansion different from As at a temperature higher than room temperature.
Ａｓより熱膨張係数が小さい物質を常温より高温で被覆
した後、上記ＧａＡｓウェーハの他方の面に、ＧａＡｓ
より熱膨張係数が小さい物質をエピタキシャル成長させ
ることを特徴とする半導体ウェーハの製造方法。2. On one side of the GaAs wafer, Ga
After coating a material with a thermal expansion coefficient smaller than As at a temperature higher than room temperature, the other surface of the GaAs wafer is coated with GaAs.
A method for manufacturing a semiconductor wafer, characterized by epitaxially growing a substance with a smaller coefficient of thermal expansion.
Ａｓより熱膨張係数が大きい物質を常温より高温で被覆
した後、上記ＧａＡｓウェーハの他方の面に、ＧａＡｓ
より熱膨張係数が大きい物質をエピタキシャル成長させ
ることを特徴とする半導体ウェーハの製造方法。3. On one side of the GaAs wafer, Ga
After coating a material with a higher coefficient of thermal expansion than As at a temperature higher than room temperature, the other surface of the GaAs wafer is coated with GaAs.
A method for manufacturing a semiconductor wafer, characterized by epitaxially growing a substance with a larger coefficient of thermal expansion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8971391A JPH04299822A (en) | 1991-03-28 | 1991-03-28 | Semiconductor wafer and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8971391A JPH04299822A (en) | 1991-03-28 | 1991-03-28 | Semiconductor wafer and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04299822A true JPH04299822A (en) | 1992-10-23 |
Family
ID=13978416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8971391A Withdrawn JPH04299822A (en) | 1991-03-28 | 1991-03-28 | Semiconductor wafer and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04299822A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19848298A1 (en) * | 1998-10-12 | 2000-04-13 | Inst Halbleiterphysik Gmbh | Large diameter, high temperature stable, single crystal semiconductor substrate wafer, for IC production, has an anti-stress layer outside the active region to counteract gravity-induced forces |
| US6599760B2 (en) * | 2001-02-06 | 2003-07-29 | Sumitomo Mitsubishi Silicon Corporation | Epitaxial semiconductor wafer manufacturing method |
-
1991
- 1991-03-28 JP JP8971391A patent/JPH04299822A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19848298A1 (en) * | 1998-10-12 | 2000-04-13 | Inst Halbleiterphysik Gmbh | Large diameter, high temperature stable, single crystal semiconductor substrate wafer, for IC production, has an anti-stress layer outside the active region to counteract gravity-induced forces |
| DE19848298B4 (en) * | 1998-10-12 | 2008-08-07 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | High temperature stable large diameter semiconductor substrate wafer and method of making same |
| US6599760B2 (en) * | 2001-02-06 | 2003-07-29 | Sumitomo Mitsubishi Silicon Corporation | Epitaxial semiconductor wafer manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6290774B1 (en) | Sequential hydride vapor phase epitaxy | |
| US3963538A (en) | Two stage heteroepitaxial deposition process for GaP/Si | |
| US5019529A (en) | Heteroepitaxial growth method | |
| US6566256B1 (en) | Dual process semiconductor heterostructures and methods | |
| US3963539A (en) | Two stage heteroepitaxial deposition process for GaAsP/Si LED's | |
| US11916111B2 (en) | Single crystal semiconductor structure and method of fabricating the same | |
| JPH04198095A (en) | Method for growing thin film of compound semiconductor | |
| US7348278B2 (en) | Method of making nitride-based compound semiconductor crystal and substrate | |
| JPH0692278B2 (en) | Epitaxial growth method | |
| JPH04299822A (en) | Semiconductor wafer and manufacture thereof | |
| JP2005203418A (en) | Nitride-based compound semiconductor substrate and method for manufacturing the same | |
| KR100447855B1 (en) | A method for fabricating a iii-v nitride film and an apparatus for fabricating the same | |
| JPH10284425A (en) | Manufacture of semiconductor device | |
| KR20050058954A (en) | A method of manfacturing gan epitaxial layer using zno buffer layer | |
| JP3127616B2 (en) | Epitaxial wafer and manufacturing method thereof | |
| JP2807750B2 (en) | Vapor growth method | |
| JPS62132312A (en) | Manufacture of semiconductor thin film | |
| JPS63194322A (en) | compound semiconductor substrate | |
| JPH06112135A (en) | Thin film forming apparatus and thin film growth method | |
| JPS62219614A (en) | Method for growth of compound semiconductor | |
| JPH09162122A (en) | III-V group compound semiconductor wafer and method of manufacturing the same | |
| JPH07321374A (en) | Method for growing compound semiconductor thin film | |
| JPS6377112A (en) | Vapor growth method | |
| JPH0267723A (en) | Method for manufacturing compound semiconductor thin film | |
| JPH02254715A (en) | Method for manufacturing compound semiconductor crystal layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980514 |