JPH04304547A - Data transfer method - Google Patents

Abstract

PURPOSE:To reduce the load of a processor operating a transfer control, to shorten a processing time, and to miniaturize a system scale by exclusively using a hardware part for a data transfer. CONSTITUTION:A ROM control circuit 2a sets a reading address, and outputs a control command indicating a transfer start and data read from a data storing ROM group 4 to a bus exclusive for the data transfer, from a starting indication from a processor 1. Then, a RAM control circuit 5 which receives the pertinent control command, starts the setting of a writing address, and successively writes the data received through the above mentioned bus in a data conversion RAM group 7. Thus, the data transfer can be operated independently to the control of the above mentioned processor 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for a data converter that transfers and controls data between a plurality of storage elements.

0002

2. Description of the Related Art FIG. 5 is a block diagram showing the configuration of a data conversion device that implements a conventional data transfer method. In the figure, 1 is a processor that performs data transfer, control, etc.; A plurality of data storage ROMs 4 forming a data storage ROM group 4 according to addresses
a ROM control circuit for selecting one of the ROMs a and 4b; 3 a data storage ROM selection signal output from the ROM control circuit 2; 4 a data storage ROM group consisting of a plurality of data storage ROMs 4a and 4b; 5; 6 is a RAM control circuit that selects one of a plurality of data conversion RAMs 7a and 7b constituting the data conversion RAM group 7 according to the address output from the front processor 1, and 6 is the data output from the RAM control circuit 5. A conversion RAM selection signal 7 is a data conversion R composed of a plurality of data conversion RAMs 7a and 7b.
The AM groups 7 and 8 are switching buffers that temporarily hold the data transferred from the respective data storage ROMs 4a and 4b and write them to the respective data conversion RAMs 7a and 7b via the transfer dedicated bus.

Next, the operation will be explained using the flowchart shown in FIG. Here, a case will be described in which conversion data is transferred from the data ROM 4a of the data storage ROM group 4 to the data conversion RAM 7a of the data conversion RAM group 7.

First, when the conversion data transfer process is started, the processor 1 outputs an address signal to the ROM control circuit 2, and in response to the address, the ROM control circuit 2 outputs a data storage ROM selection signal 3a. to make the desired data storage ROM 4a accessible (step ST1). Then, the processor 1 sets a read address for starting transfer (step ST2), and reads the corresponding data from the data storage ROM 4a (step ST2).
3).

On the other hand, this processor 1 outputs an address signal to the RAM control circuit 5, and according to the address, the RAM control circuit 5 outputs a data conversion RAM selection signal 6a, and selects a desired data conversion RAM 7a. It is made accessible (step ST4). Then, the once read conversion data is written to the data conversion RAM 7a via the switching buffer and using the transfer dedicated bus (step ST5).
), and thereafter, while updating the forwarding address (step ST
6) Repeat steps ST1 to ST5 until all conversion data is transferred (step ST7)
.

[0006]

[Problems to be Solved by the Invention] Since the conventional data transfer system is configured as described above, the processor that controls the transfer must exclusively use the address bus, the data bus, and the dedicated transfer bus, and the There were problems such as an increase in the load and a large number of address lines and data lines dedicated to transfer, resulting in an increase in system scale.

[0007] This invention was made to solve the above problems, and by dedicating the hardware part for data transfer, it reduces the load on the processor that controls the transfer and shortens the processing time. The purpose of this invention is to obtain a data transfer method that enables the reduction of system scale.

[0008]

[Means for Solving the Problem] The data transfer method according to the invention of claim (1) stores data in a ROM control circuit in response to a startup instruction from a processor together with a control command that sets a read address and instructs to start transfer. R.O.
The data read from the M group is output to the transfer-only bus, and the RAM control circuit that receives the control command starts setting a write address, and the data received via the transfer-only bus is sequentially transferred to the data conversion RAM group. By writing, data transfer is performed independently of the control of the processor.

[0009] Furthermore, the data transfer method according to the invention of claim (2) is such that a data conversion device for realizing the data transfer method according to the invention of claim (1) is provided with a plurality of the RAM control circuits. , each RAM control circuit is provided with its own circuit selection circuit, and each RAM control circuit determines the transfer destination of the ROM control circuit.

[0010] Furthermore, the data transfer method according to the invention of claim (3) is a data conversion device for realizing the data transfer method according to the invention of claim (2), in which the ROM control circuit and a plurality of RAM control circuits are provided. The ROM control circuit is provided with a parallel/serial conversion circuit, and each RAM control circuit is provided with a serial/parallel conversion circuit.

[0011]

[Operation] The data transfer method in the invention of claims (1) to (3) dedicates a hardware part for data transfer by controlling the RAM control circuit from the ROM control circuit using control commands. Therefore, the processor that was controlling the transfer can perform other processing during the data transfer, and since the data transfer is performed by the hardware itself, the speed can be increased.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data conversion device that realizes a data transfer method according to an embodiment of the invention as claimed in claim (1), and is the same or has the same parts as the conventional data conversion device (FIG. 5). Reference numerals are given and explanations are omitted.

In FIG. 1, 2a is a ROM control circuit, and as shown in FIG. A data transmission control circuit 17 that controls the sequence, a ROM address creation circuit 18 that creates a read address for the data storage ROM group 4, and access to the data storage ROM group 4 is enabled under the control of the data transmission control circuit 17 (data storage ROM data for selecting the control command from the ROM/CS creation circuit 19 (output of selection signal), the data transmission control circuit 17 and the data read from the data storage ROM group 4 under the control of the data transmission control circuit 17; /command selector 20.

Further, in FIG. 1, 5a is a RAM control circuit, and this configuration, as shown in FIG. 2, receives conversion data or control commands from the ROM control circuit 2a and controls writing of the conversion data. A data reception control circuit 21 , a RAM address creation circuit 22 that creates an address of the data conversion RAM group 7 in which the converted data is written under the control of the data reception control circuit 21 , and a It consists of a RAM/WE creation circuit 23 that enables access to the conversion RAM group 7 (outputs a data conversion RAM selection signal).

Next, the operation of the invention according to claim (1) will be explained. Here, from the data storage ROM 4a of the data storage ROM group 4 to the data conversion RA of the data conversion RAM group 7,
A case in which converted data is transferred to M7a will be described.

First, when data transfer processing is started, the processor decoder 16, which receives the address signal output from the processor 1, outputs a start signal to the data transmission control circuit 17. The data transmission control circuit 17 outputs a control command to start the transfer process, and also sets the address value output from the ROM address generation circuit 18 as a start value.

On the other hand, the ROM/CS creation circuit 19 accesses the data storage ROM 4a using the address output from the ROM address creation circuit 18 and the control signal from the data transmission control circuit 17. The accessed data is then input to the decoder/command selector 20 via the ROM data bus, and selectively output under the control of the data transmission control circuit 17. At this time, the data transmission control circuit 17 outputs a timing signal to notify the RAM control circuit 5a that the data has been output.

Next, in the RAM control circuit 5a, the ROM
The data reception control circuit 21 selectively receives the data transmitted from the control circuit 2a and sends an address creation instruction to the RAM.
It is output to the address generation circuit 22. And RAM・W
The E generation circuit 23 converts data RA corresponding to the address value based on the address value output from the RAM address generation circuit 22 and the control signal from the data reception control circuit 21.
Access M7a and write the data received via the RAM data bus.

Next, a data transfer system according to the invention of claim (2) will be explained. In the above-mentioned invention of claim (1), one-to-one data transfer is performed between the ROM control circuit 2a and the RAM control circuit 5a via the transfer-dedicated bus, but as shown in FIG. ROM control circuit 2a to N
Data may be transferred to (≧2) RAM control circuits 5a.

In this case, each RAM control circuit 5a is provided with its own circuit selection circuit 24, and this own circuit selection circuit 24 receives the control command and timing signal that are the outputs of the data transmission control circuit 17 in the ROM control circuit 2a. By enabling the operation of the corresponding RAM control circuit 5a by the control command output from the data transmission control circuit 17, data can be sent to the data conversion RAM of the plurality of RAM control circuits 5a using only the transfer dedicated bus. enable transfer.

Next, a data transfer system according to the invention of claim (3) will be explained. In FIG. 4, the ROM control circuit 2
A parallel/serial conversion circuit 25 is provided at the output stage of the data transmission circuit 5a, and a serial/parallel conversion circuit 26 is provided at the input stage of each RAM control circuit 5a. This makes it possible to reduce the transfer-only bus (previously multiple buses used to transfer data) to a single serial line, thereby simplifying the transmission system.

[0022]

Effects of the Invention As described above, claims (1) to (
According to the invention of 3), separately from the control of the processor, the ROM control circuit receives an address signal from the processor as an instruction to start data transfer, and reads data read from the data storage ROM together with a control command instructing the start of transfer. RAM that outputs to the transfer dedicated bus and receives the control command
The control circuit is configured to dedicate a hardware section for data transfer by writing the data received via the transfer-dedicated bus to the data conversion RAM group, so that the processor is configured to dedicate the hardware portion for data transfer. In addition to being able to perform other processing at the same time, the speed can be increased due to the dedicated circuit. Furthermore, since the number of signal lines is reduced, the overall system scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data conversion device that implements a data transfer method according to an embodiment of the invention as claimed in claim (1).

FIG. 2 is a block diagram showing the configuration of a ROM control circuit and a RAM control circuit in the data conversion device of FIG. 1;

FIG. 3 is a block diagram showing the configuration of a ROM control circuit and a RAM control circuit in a data conversion device that implements a data transfer method according to an embodiment of the invention as claimed in claim (2).

FIG. 4 is a block diagram showing the configuration of a ROM control circuit and a RAM control circuit in a data conversion device that implements a data transfer method according to an embodiment of the invention as claimed in claim (3).

FIG. 5 is a block diagram showing the configuration of a data conversion device that implements a conventional data transfer method.

FIG. 6 is a flowchart illustrating the operation of a conventional data transfer method.

[Explanation of symbols]

1 Processor 2a ROM control circuit 4 Data storage ROM group 5a RAM control circuit 7 Data conversion RAM group

Claims (3)

[Claims] Claim 1: Data stored in a predetermined ROM of the data storage ROM group is transferred to a predetermined R of the data conversion RAM group.
a ROM control circuit that selects the ROM in accordance with an address output from a processor that controls transfer to the AM; and a ROM control circuit that selects the ROM in accordance with an address output from the processor;
In the data conversion device, the ROM control circuit sets a start value of a read address in response to a startup instruction from the processor, and controls the data storage ROM along with a control command instructing to start transfer. The RAM control circuit receives a control command from the ROM control circuit and starts setting a write address, and also outputs the read data by accessing the ROM control circuit to a bus dedicated to data transfer. 1. A data transfer method characterized in that data transfer is performed independently of control of the processor by sequentially writing data. 2. Data stored in a predetermined ROM of the data storage ROM group is transferred to a predetermined R of the data conversion RAM group.
a ROM control circuit that selects the ROM in accordance with an address output from a processor that controls transfer to the AM; and a ROM control circuit that selects the ROM in accordance with an address output from the processor;
In a data conversion device including a plurality of RAM control circuits that select AM, the ROM control circuit sets a start value of a read address in response to a startup instruction from the processor, and transmits the data along with a control command instructing to start transfer. Data read out by accessing the storage ROM group is output to a bus dedicated for data transfer, and the plurality of RAM control circuits determine whether the transfer destination of the control command output from the ROM control circuit is the own circuit. Each of the RAM control circuits is provided with its own circuit selection circuit, and the RAM control circuit that is determined to be its own circuit by the own circuit selection circuit starts setting a write address upon receiving a control command from the ROM control circuit, and also starts setting a write address via the bus. A data transfer method characterized in that the data transfer is performed independently of the control of the processor by sequentially writing data received by the processor. 3. Data stored in a predetermined ROM of the data storage ROM group is transferred to a predetermined R of the data conversion RAM group.
a ROM control circuit that selects the ROM in accordance with an address output from a processor that controls transfer to the AM; and a ROM control circuit that selects the ROM in accordance with an address output from the processor;
In a data conversion device comprising a plurality of RAM control circuits that select AM, the ROM control circuit and a plurality of RAM
A bus dedicated to data transfer between the M control circuits is a serial line, and the ROM control circuit is equipped with a parallel/serial conversion circuit for outputting to this serial line, and converts the start value of the read address in response to a startup instruction from the processor. The plurality of RAM control circuits output the read data by accessing the data storage ROM group as serial data to a bus dedicated for data transfer together with a control command instructing to set and start transfer, and the plurality of RAM control circuits Each includes a serial/parallel conversion circuit for receiving the control command and a own circuit selection circuit for determining whether or not the transfer destination of the control command output from the ROM control circuit is the own circuit. The RAM control circuit that has determined that there is a write address starts setting a write address upon receiving the control command from the ROM control circuit, and controls the processor by sequentially writing the data received via the bus. A data transfer method characterized by performing data transfer independently of the .