JPH04307765A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density semiconductor memory device.

0002

2. Description of the Related Art In recent years, the density of semiconductor memory devices has increased, and the dimensions of transistors, wiring, capacitors, etc. used therein have become extremely small. On the other hand, there is a requirement that the voltages of externally applied power supplies and input/output signals should not be lowered too much. In order to satisfy this requirement, a high electric field is applied to the element, but such a situation causes deterioration of the life of the element. Recent device manufacturing technology has focused on making the electric field within the device as uniform as possible and lowering the maximum electric field that defines the lifetime. Another challenge is to lower the maximum voltage applied to the capacitive insulating film of DRAM.

[0003] Further, in order to obtain large capacitance with a small surface area, the development of films with high dielectric constants is progressing, but there is no film with excellent heat resistance, and plate electrodes that can be formed at low temperatures must be used. I don't get it. Since the storage electrode is required to be made of a material with good heat resistance, these electrodes are made of different materials. Conventionally, there was no need to use such a high dielectric constant film, so N-type silicon or polysilicon was used for both electrodes. In such a case, the maximum voltage applied to the capacitive insulating film can be minimized by applying a voltage that is one-half of the power supply voltage to the plate.

An example of a conventional method for alleviating the maximum electric field applied to the capacitive insulating film will be described below with reference to the drawings.

FIG. 6 shows a method for minimizing the maximum electric field applied to a capacitor insulating film in a conventional DRAM cell. In FIG. 6, 1 is a word line, 2 is a bit line, 3 is a transfer gate, 4 is a charge storage electrode, 5 is a plate electrode,
6 is a capacitive insulating film, 7 is a voltage applied to the plate electrode 6 (V
PL), and the unit cell is configured as described above.

Conventionally, charge storage electrode 4 has been made of N-type silicon or polysilicon, plate electrode 5 has been made of N-type polysilicon, and VPL has been given one-half of the power supply voltage. The reason for this is that cell writing is performed with two values, 0 volts and the power supply voltage (VCC), and the Fermi level of the charge storage electrode 4 and the plate electrode 5 are the same, so the potential of the plate electrode 5 is This is because by keeping the voltage at one-half of the power supply voltage, the maximum voltage applied to the capacitive insulating film 6 can be suppressed to one-half of the power supply voltage. The above is
The maximum voltage applied across the insulating film is VPL and VCC-V.
This is easily understood considering that it is the larger of PL.

[0007]

[Problem to be Solved by the Invention] However, in the above configuration, in the case of a capacitor consisting of two electrodes with different Fermi levels, the voltage applied to both ends of the insulating film is determined by the potential difference between the two materials, which is applied to both electrodes. There was a problem in that the maximum voltage did not become the minimum due to the deviation by the Fermi level difference.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a semiconductor memory device that minimizes the maximum voltage applied across an insulating film in the case of a capacitor consisting of two electrodes with different Fermi levels.

[0009]

[Means for Solving the Problems] In the semiconductor memory device of the present invention, the voltage applied to the plate electrode is changed from half of the power supply voltage to the Fermi level of the charge storage electrode material to the Fermi level of the plate electrode material. The structure is such that the voltage is increased by the amount minus the voltage.

0010

[Operation] According to the above-described structure of the present invention, when the power supply voltage level (VCC) is written to the charge storage electrode, half of VCC is drawn from VCC between the two electrodes, and further, a voltage of half of VCC is drawn from the Fermi level of the charge storage material. The voltage minus the Fermi level of the electrode material is applied. At this time, a voltage obtained by adding a Fermi level difference voltage to the above voltage, that is, a voltage half of VCC is applied to the capacitive insulating film. Further, when 0 volt is written to the charge storage electrode, a voltage equal to half of VCC plus a voltage obtained by subtracting the Fermi level of the plate electrode material from the Fermi level of the charge storage material is applied between the two electrodes. At this time, a voltage obtained by subtracting the voltage of the Fermi level difference from the above voltage, that is, a voltage of one-half of VCC is applied to the capacitive insulating film. As described above, according to the configuration of the present invention, it is possible to suppress the maximum voltage applied to the capacitor insulating film to one-half of VCC, that is, to the minimum, even for capacitor electrodes made of different materials.

[0011]

[Example] (Example 1) The following is an example of the present invention.
This will be explained with reference to the drawings.

FIG. 1 shows the structure of a memory cell in a first embodiment of the present invention, and is a sectional view perpendicular to a word line of a so-called stacked DRAM cell.

In FIG. 1, a word line 1, a bit line 2, an S/D diffusion layer 13, a transfer gate 3, a LOCOS isolation film 12, and a charge storage electrode 8 made of N+ polysilicon are disposed on a silicon substrate 11. , a capacitor insulating film 6 made of tantalum oxide, a plate electrode 9 made of tungsten, and an interlayer insulating film 14. Since the plate electrode 9 uses the capacitive insulating film 6 of tantalum oxide, which is susceptible to high-temperature heat treatment, tungsten, which can be formed at low temperatures, must be used. For such a structure, play
The voltage VPL10 applied to the plate electrode 9 is made higher than one half of the power supply voltage VCC by a voltage obtained by subtracting the Fermi level of the plate electrode material from the Fermi level of the charge storage electrode material.

Regarding the memory cell configured as described above, the effects of the present invention will be explained through a comparison between the conventional structure and the structure of the present invention.

FIG. 2 shows a band diagram of the charge storage electrode 4, the capacitor insulating film 6, and the plate electrode 5 in a conventional structure, that is, when the same material is used for the two electrodes. The voltage (VPL) 7 applied to the plate is fixed at half the power supply voltage (VCC), and the write voltage 15 is set between 0 volts and V
Caught by CC. First, when the voltages applied to the two electrodes are equal (FIG. 2(b)), no voltage is applied to the capacitive insulating film 6 because the electrode materials are the same. When data is written, the write voltage 15 becomes 0 volts or VCC, but in either case, a voltage half of VCC is applied to the capacitor insulating film 6 (FIGS. 2(a) and 2(c)). In this way, the maximum voltage applied to the insulating film becomes half of VCC, which is suppressed to a minimum.

FIG. 3 shows the structure of the present invention, that is, a band diagram of the charge storage electrode 8, the capacitor insulating film 6, and the plate electrode 9 in the case of FIG. Voltage applied to the plate VP
L10 is set higher than one half of VCC by a voltage equal to the Fermi level of the charge storage electrode material minus the Fermi level of the plate electrode material. When the two electrode materials that are the subject of the present invention are different, only by setting VPL in this manner will a voltage half of VCC be applied to the insulating film 6 both when writing is 0 volts and when it is VCC. . In this way, the maximum voltage applied to the insulating film becomes half of VCC, which is suppressed to the minimum (Figs. 3(a), (b), (c)
)).

As described above, in this embodiment, in a DRAM in which the charge storage electrode 8 and the plate electrode 9 are made of different materials, the voltage applied to the plate electrode 9 is lower than half of the power supply voltage. By increasing the voltage by the Fermi level of the material of the electrode 8 minus the Fermi level of the material of the plate electrode 9, the maximum voltage applied to both ends of the capacitive insulating film 6 can be minimized.

In this embodiment, the charge storage electrode 8 made of N+ polysilicon and the plate electrode 9 made of tungsten were used; A plate electrode made of polysilicon with P-type impurities diffused therein may be used, and a voltage approximately 1.1 V higher than one-half of the power supply voltage may be applied to the plate electrode. Furthermore, using a charge storage electrode made of silicon or polysilicon in which P-type impurities are diffused and a plate electrode made of polysilicon in which N-type impurities are diffused, A voltage that is approximately 1.1 V lower than one-half of the power supply voltage may be applied.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a cross-sectional view perpendicular to the word line of a cell structure of a ferroelectric memory according to a second embodiment of the present invention. That is, a ferroelectric memory cell includes a word line 1, a bit line 2, a diffusion layer 17, a write electrode 23 made of a diffusion layer, a ferroelectric film 19, a plate electrode 20, and a LOC.
It consists of an OS isolation film 22 and an interlayer insulating film 21. Ferroelectrics lose their polarization when subjected to high-temperature heat treatment, so it is necessary to avoid high temperatures after formation. Therefore, the plate electrode 21 must be formed at a low temperature, and is made of aluminum, tungsten, or the like, and is made of a different material from the write electrode 23.

FIG. 5 shows a circuit diagram of FIG. 4, and the operation will be explained using this circuit diagram. The circuit is the same as the DRAM cell shown in FIG. The difference is that the insulating film of the capacitance consisting of the write electrode 23 and the plate electrode 20 is made of ferroelectric material 19, and that the value of the low level write voltage subtracted from the high level write voltage applied to the plate electrode 20 is A voltage higher than the low-level write voltage is applied by a voltage equal to the sum of one half and the voltage obtained by subtracting the Fermi level of the plate electrode 20 material from the Fermi level of the write electrode 23 material.

The operation is such that a data level is applied to the bit line 2, the word line 1 opens the transfer gate 3, and the data level is applied to the bit line 2.
The data level is applied to the write electrode 23. The electric field generated at this time and applied to the ferroelectric changes the polarization of the ferroelectric, and this polarized state remains as a memory state. In general, the polarization characteristics of a ferroelectric material are nearly symmetrical in both directions, from the write electrode 23 toward the plate electrode 20, and in the opposite direction. Therefore, the minimum value of the strength (absolute value) of the electric field that reverses a certain polarization state may be the same regardless of the original polarization direction.

As described above, in this embodiment, the plate voltage 20 is set to one-half of the value obtained by subtracting the low level write voltage from the high level write voltage, and the value of the plate electrode 20 is set to 1/2 of the value obtained by subtracting the low level write voltage from the high level write voltage, and from the Fermi level of the write electrode 23 material. By applying a voltage higher than the low-level write voltage by a voltage equal to the voltage obtained by subtracting the Fermi level of the 20 material, equal positive and negative electric fields are applied to the ferroelectric material 19, and the most efficient writing can be achieved.

[0024]

As described above, the present invention provides a DRAM in which the charge storage electrode and the plate electrode are made of different materials.
By increasing the voltage applied to the plate electrode by a voltage equal to the Fermi level of the charge storage electrode material minus the Fermi level of the plate electrode material than half of the power supply voltage, the voltage applied to both ends of the capacitive insulating film is increased. This maximum voltage can be minimized and long-term reliability can be ensured.

[Brief explanation of drawings]

FIG. 1: A workpiece of a DRAM in a first embodiment of the present invention.
FIG.

FIG. 2 is a band diagram of a capacitive structure in a conventional method.

FIG. 3 is a band diagram of the capacitive structure in the first embodiment of the present invention.

FIG. 4 is a sectional view perpendicular to a word line of a ferroelectric memory illustrating a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a ferroelectric memory cell in a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a DRAM cell for explaining the operation of a conventional method.

[Explanation of symbols]

1 Bit line 2 Word line 3 Transfer gate 6 Capacitor electrode 7 Voltage applied to plate electrode (VPL) 8 Charge storage electrode (P+polysilicon) 9 Plate electrode (N
+Polysilicon) 10 VPL 15 Write voltage 19 Ferroelectric 23 Write electrode

Claims (4)

[Claims] Claim 1: One transistor and one capacitor form a unit memory cell, and the capacitor is composed of a charge storage electrode, a plate electrode, and an insulating film sandwiched between them, and the charge storage electrode DR whose plate electrode and plate electrode are made of different materials.
AM, characterized in that the voltage applied to the plate electrode is higher than one-half of the power supply voltage by the voltage obtained by subtracting the Fermi level of the plate electrode material from the Fermi level of the charge storage electrode material. Semiconductor storage device. 2. One transistor and one capacitor form a unit memory cell, and the capacitor is composed of a write electrode, a plate electrode, and a ferroelectric film sandwiched between them,
The write electrode and the plate electrode are made of different materials, and the voltage applied to the plate electrode is one half of the value obtained by subtracting the low level write voltage from the high level write voltage, A semiconductor memory device characterized in that the voltage is higher than the low level write voltage by the sum of the voltage obtained by subtracting the Fermi level of the plate electrode material from the Fermi level of the write electrode material. 3. A DRAM in which one transistor and one capacitor form a unit memory cell, and the capacitor has a charge storage electrode made of silicon or polysilicon doped with N-type impurities and a charge storage electrode made of silicon or polysilicon doped with N-type impurities. It consists of a counter electrode made of diffused polysilicon and an insulating film sandwiched between them, and a voltage approximately 1.1V higher than one-half of the power supply voltage is applied to the counter electrode. Characteristic semiconductor memory device. 4. A DRAM in which one transistor and one capacitor form a unit memory cell, and the capacitance includes a charge storage electrode made of silicon or polysilicon doped with P-type impurities, and a charge storage electrode made of silicon or polysilicon doped with P-type impurities. It consists of a counter electrode made of diffused polysilicon and an insulating film sandwiched between them, and a voltage approximately 1.1V lower than half of the power supply voltage is applied to the counter electrode. Characteristic semiconductor memory device.