JPH04310698A - memory IC - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to memory ICs such as flash EEPROMs (batch erasable PROMs) used in card ICs, etc., and particularly to memory ICs that can prevent data writing and erasing due to malfunction of control signals. It is related to IC.

0002

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional memory IC, such as a flash EEPROM. In the figure,
1 is chip enable signal CE, output enable signal O
2 is a data bus 11, and an address bus 1 is a CPU that outputs control signals such as E and write enable signal WE.
2 and a flash EEPROM coupled to the CPU 1 via a control bus 13.

[0003] The data bus 11 is a flash EEPROM.
Address bus 12 transmits read data from CPU 2 and write data from CPU 1, and address bus 12 transmits read data from CPU 1 to flash E
The control bus 13 transmits an address signal to the EPROM 2, and the control bus 13 is used to connect the CPU 1 to the flash EEPROM 2.
Control signals CE, OE, and WE are transmitted to the terminal. Usually, each control signal CE,
Since OE and WE are active at L level, each is marked with a "bar" indicating inversion as shown.

Next, the operation of the conventional memory IC shown in FIG. 2 will be explained. CPU1 is control bus 1
3, control signals CE, OE, and WE are selectively output, and an address signal via the address bus 12 specifies an address position in the flash EEPROM 2, and a predetermined address position is output via the data bus 11. Writing and erasing data (hereinafter simply referred to as writing, including erasing) or reading data.

For example, in the case of data reading, an IC chip is specified using a chip enable signal CE, and data is read from a specified address using an output enable signal OE. In the case of data writing, the IC chip is specified by the chip enable signal CE, and writing is performed to the specified address by the write enable signal WE. In this way, from CPU1 to flash EEPROM
2, data is read and written by inputting various commands via the buses 11 to 13.

[0006]

[Problems to be Solved by the Invention] As described above, the conventional memory IC receives each control signal CE from the CPU 1,
Since data writing is performed using the OE, WE, and data signals, there is a problem in that if the CPU 1 malfunctions, the control signal malfunctions and erroneous data is written (erroneously erased).

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a memory IC that can prevent data writing due to malfunction of a control signal.

[0008]

[Means for solving the problems] Memory I according to the present invention
C is provided with a write protection circuit that invalidates the control signal in response to an error signal indicating malfunction of the control signal.

[0009]

In the present invention, the control signal (write enable signal) is disabled to prevent data writing due to malfunction.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, in which 1A corresponds to CPU 1, 2, 11 and 12.
is the same as above. In this case, CPU1A is
It outputs an error signal ER indicating a malfunction of the control signal (write enable signal) CE due to its own malfunction.

A write prevention signal control circuit 5 outputs a write prevention signal WP and a reset signal RST at H level when the error signal ER becomes H level (active). The reset signal RST is connected to the reset input terminal R of the CPU1A.
It is applied to ESET and returns the error signal ER to L level.

A write protection circuit 20 disables the write enable signal WE in response to the write prevention signal WP, and is included in the flash EEPROM 2 integrally with the flash EEPROM 2. The write protection circuit 20 is
A trigger generator 21 that generates an H-level trigger signal A in response to the write prevention signal WP, a latch circuit 22 that latches the trigger signal A, and a latch signal from the latch circuit 22 and a write enable signal WE. It is composed of an OR circuit 23 which calculates a logical sum and outputs a final write enable signal WE for the flash EEPROM 2.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be explained. Normally, the CPU 1A is healthy and the error signal ER is at L level, so the write prevention signal WP is not active and the trigger signal A, that is, the latch signal is at L level. Therefore, the write enable signal WE from the CPU 1A is transmitted via the OR circuit 23 to
A write enable signal is applied to the input terminal of the flash EEPROM 2, and predetermined data is written.

On the other hand, if a failure occurs in the CPU 1A,
The CPU 1A outputs an H level error signal ER from the error signal output terminal ERROR. This error signal ER
As a result, the write protection signal control circuit 5 is controlled by the write protection circuit 20.
The write prevention signal WP at H level is output to the trigger generator 21 in the CPU 1A, and the reset signal input terminal R of the CPU 1A is
Outputs an H level reset signal RST to ESET.

When the write prevention signal WP at the H level is input to the A input, the trigger generator 21 outputs a trigger signal A consisting of an H level pulse to the A input of the latch circuit 22 . Thereby, the latch circuit 22 continues to apply the H level latch signal to one input terminal of the OR circuit 23, and holds the output signal of the OR circuit 23 at the H level.

At this time, an L level active write enable signal WE is applied from the CPU 1A to the other input terminal of the OR circuit 23, but the output signal of the OR circuit 23 becomes H.
Since it continues to maintain the level status, the flash EEPRO
M2 does not enter the write state.

Further, the CPU 1A is reset from the failure state by the reset signal RST from the write prevention signal control circuit 5 and returns to the normal state. As a result, the error signal E
R returns to the L level, the write prevention signal WP goes to the L level, and the trigger signal A of the trigger generator 21 goes to the L level, so the latch circuit 22 applies an L level latch signal to the OR circuit 23. , the write enable signal WE from the CPU 1A is allowed to pass through the OR circuit 23.

As described above, when the write enable signal WE from the CPU 1A indicates a failure, the write protection signal WP is set to H level (active) based on the error signal ER, and the write protection circuit 20 prevents writing. Enable signal WE can be disabled. Therefore, flash EEPR
OM2 does not enter the write state, and data writing (erroneous erasing) due to malfunction can be prevented.

In the above embodiment, the case where the memory IC is a flash EEPROM 2 has been described, but it goes without saying that the same effect can be obtained even if the present invention is applied to other memory ICs.

[0020]

[Effects of the Invention] As described above, according to the present invention, a write protection circuit is provided to invalidate the control signal in response to an error signal indicating malfunction of the control signal, and the control signal is invalidated. This has the effect of providing a memory IC that can prevent data writing and erasing due to malfunction of control signals.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional memory IC.

[Explanation of symbols]

1A CPU 2 Flash EEPROM (memory IC) 5
Write protection signal control circuit 11 Data bus 20 Write protection circuit 21 Trigger generator 22 Latch circuit 23 OR circuit WE Write enable signal (control signal)
ER Error signal WP Write protection signal

Claims (1)

[Claims] 1. A memory IC in which data is written in response to a control signal is provided with a write protection circuit for disabling the control signal in response to an error signal indicating a malfunction of the control signal. Memory I characterized by preventing data writing based on
C.