JPH04312927A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To realize a higher speed operation and a larger scale integration by reducing the base resistance of a bipolar transistor using a narrow band gap base. CONSTITUTION:An n<+> type buried collector layer 2 of a high impurity concentration is formed on a p-type silicon substrate 1, an embedded collector layer 2 is formed, and an recessed portion 15 is selectively provided on the surface of an n-type collector epitaxial growth layer 3 by silicon on the embedded collector layer 2. And a p-type intrinsic base region 16 is formed by Si1-xGex containing r-type impurities embedded in the recessed portion 15. Then, high impurity concentration p<+> type external base region 17 is selectively formed in contact with the intrinsic base region 16 on the collector epitaxial growth layer 3. By doing this, the element configuration itself can be made smaller and the device can be highly integrated very easily.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device based on a narrow bandgap base (Narrow Bandgap B).
silicon hetero bipolar transistor (Silicon Hetero Bipola) using
rTransistor. (hereinafter referred to as Si-HBT) and its manufacturing method.

0002

[Prior Art] The general structure of this type of Si-HBT according to a conventional example is schematically shown in FIG.
The main manufacturing steps are sequentially schematically shown in FIGS. 8 to 14.

First of all, the conventional Si-H shown in FIG.
The configuration of BT will be described.

That is, in the device configuration shown in FIG. 7, reference numeral 1 is a P-type silicon substrate, 2 is an N+ type buried collector layer selectively embedded in the silicon substrate 1, and 3 is a P-type buried collector layer. An N-type collector epitaxial growth layer (hereinafter referred to as collector epitaxial layer) selectively epitaxially grown on the buried collector layer 2 is shown, 4 is an oxide film for isolation between elements, and 14 is an oxide film for isolation between elements. A P+ type diffusion layer for channel stop is selectively formed directly under 4, and 5 is an oxide film for intra-element isolation.

Further, 6 is a P type intrinsic base region formed on the N type collector epitaxial layer 3, and 7 is a P+ type external base region selectively diffused into the intrinsic base region 6. 8 is an interlayer insulating film such as an oxide film.

Further, reference numeral 9 denotes an N+ type collector diffusion layer selectively diffused in the collector epitaxial layer 3;
11, 12, and 13 are N+ type emitter silicon layers selectively formed on the intrinsic base region 6;
are a base electrode, an emitter electrode, and a collector electrode formed respectively corresponding to the corresponding layer.

Next, a conventional Si-HBT manufacturing process shown in FIGS. 8 to 14 corresponding to the configuration shown in FIG. 7 will be described.

[0008] The conventional Si-
In the case of HBT, in the first step (FIG. 8), first,
An N-type impurity such as arsenic is introduced into the P-type silicon substrate 1 at a high concentration by ion implantation or the like, and heat treatment is performed to form an N+-type buried collector layer 2, and then the N+-type buried collector layer 2 is formed. Silicon (Si) is grown epitaxially on the layer 2 by epitaxial growth to form an N-type collector epitaxial layer 3.

In the second step (FIG. 9), the N
After selectively digging a trench groove to a depth exceeding the N+ type buried collector layer 2 by anisotropic etching using an oxide film or the like as a mask on the corresponding both sides of the type collector epitaxial layer 3, , P-type impurities such as boron are introduced at a high concentration into the bottom of each of the trenches by ion implantation, etc., and heat-treated to form P-type impurities in each trench.
After forming the + type channel stop diffusion layer 14, the inside of each trench groove is filled with a CVD oxide film or the like, and an oxide film 4 for element isolation is formed in each trench groove.

In the third step (FIG. 10), the
An oxide film 5 for internal isolation is selectively formed on the corresponding region on the N-type collector epitaxial layer 3 by the LOCOS method using a nitride film or the like as a mask.
For the corresponding one side portion on the mold collector epitaxial layer 3,
N-type impurities such as phosphorus are introduced at a high concentration by ion implantation using a resist as a mask, and then heat treated.
An N+ type collector diffusion layer 9 is selectively formed.

In the fourth step (FIG. 11), an MBE film is formed on the N-type collector epitaxial layer 3 separated by the intra-element isolation oxide film 5 using a resist as a mask.
silicon germanium (Si1-XGeX) doped with P-type impurities such as boron by
) is deposited to form a P-type intrinsic base region 6.

In the fifth step (FIG. 12), the
P-type impurities such as boron are introduced at a high concentration into a predetermined region within the P-type intrinsic base region 6 by ion implantation using a resist or the like as a mask, and then heat-treated.
After selectively forming the P+ type external base region 7, CVD
An interlayer insulating film 8 such as an oxide film is formed on the entire surface of these by a method or the like.

In the sixth step (FIG. 13), a predetermined portion of the interlayer insulating film 8 corresponding to the emitter silicon layer is etched by etching using a resist or the like as a mask, and a through hole is opened in the corresponding portion. Then, polycrystalline silicon or the like is deposited on the entire surface by the CVD method, and N-type impurities such as arsenic are introduced at a high concentration into the deposited polycrystalline silicon by ion implantation or the like. After patterning the corresponding portion of the polycrystalline silicon into which the N-type impurity has been introduced by etching using a resist or the like as a mask, this is heat-treated.
An N+ type emitter silicon layer 10 is selectively formed, and then predetermined portions of the interlayer insulating film 8 corresponding to the P+ type external base region 7 and the N+ type collector diffusion layer 9 are coated with a resist. Using etching as a mask, through holes are opened in each of the corresponding parts.

In the seventh step (FIG. 14), the N
After forming a film of aluminum (Al) as an electrode material on the entire surface of each part including the +-type emitter silicon layer 10 and each through hole by sputtering or the like, the formed aluminum film is Patterning is performed by etching using a resist or the like as a mask, and each electrode is formed for each corresponding region and each corresponding layer, that is, in this case, each base electrode 11 and the above N+ type emitter silicon layer 1
0, an emitter electrode 12 and a collector electrode 13 are selectively formed for the N+ type collector diffusion layer 9, respectively.

That is, in this way, the conventional Si-HBT structure shown in FIG. 7 is manufactured as expected.

[0016]

[Problem to be Solved by the Invention] However, in the conventional Si-HBT configured as described above, N
On the type collector epitaxial layer 3, Si1-XGeX doped with P-type impurities is deposited to form a P-type intrinsic base region 6, and within the P-type intrinsic base region 6, P-type impurities are added.
Since the P+ type external base region 7 is formed by introducing type impurities at a high concentration and performing heat treatment, not only does the base resistance increase, making it impossible to increase the speed of the bipolar transistor, but it also causes problems with the device configuration itself. There are problems in that it is difficult to downsize and hinders high integration.

The present invention was made to improve these conventional problems, and its purpose is to reduce the base resistance of a bipolar transistor using a narrow bandgap base, thereby increasing high speed. This type of semiconductor device has enabled high integration as well as
An object of the present invention is to provide a Si-HBT and a method for manufacturing the same.

[0018]

[Means for Solving the Problems] In order to achieve the above object, a semiconductor device according to the present invention and a method for manufacturing the same are provided in which, in a Si-HBT, a highly concentrated silicon substrate of a second conductivity type is formed on a silicon substrate of a first conductivity type. forming a buried collector layer of
In addition, a concave portion is selectively provided on the surface of the collector epitaxial growth layer made of silicon (Si) on the buried collector layer, and silicon germanium (Si1-XGe) containing impurities of the first conductivity type is embedded in the concave portion.
X) forms an intrinsic base region of the first conductivity type, and selectively forms a highly concentrated extrinsic base region of the first conductivity type in contact with the intrinsic base region on the collector epitaxial growth layer. be.

That is, the present invention includes a highly doped buried collector layer of a second conductivity type formed on a silicon substrate of a first conductivity type, and a silicon (S) layer formed on the buried collector layer.
a collector epitaxial growth layer of a second conductivity type formed by selectively epitaxially growing i) and diffusing impurities of a second conductivity type; and a concave portion selectively provided on the surface of the collector epitaxial growth layer. Silicon germanium (Si1-) containing impurities of 1 conductivity type
a first conductivity type intrinsic base region formed by embedding XGeX); a highly doped first conductivity type external base region selectively formed in contact with the intrinsic base region on the collector epitaxial growth layer; and the intrinsic base region. It is characterized by comprising at least a highly doped emitter silicon layer of the second conductivity type selectively formed on the buried collector layer and a collector diffusion layer of the highly doped second conductivity type selectively formed on the buried collector layer. This is a semiconductor device.

[0020] Furthermore, the method of the present invention includes forming a highly doped buried collector layer of a second conductivity type on a silicon substrate of a first conductivity type, and depositing silicon (Si) on the buried collector layer.
a first step of selectively epitaxially growing and diffusing a second conductivity type impurity to form a second conductivity type collector epitaxial growth layer; a second step of selectively forming a highly concentrated collector diffusion layer of the second conductivity type in a corresponding region on the buried collector layer; , silicon germanium (Si1-XGeX) containing impurities of the first conductivity type is buried to form an intrinsic base region of the first conductivity type, and a highly concentrated extrinsic base region of the first conductivity type is formed in contact with the intrinsic base region. A third step of selectively forming the interlayer insulating film on their surfaces, and selectively opening the interlayer insulating film with respect to the intrinsic base region, and then forming the interlayer insulating film through the opening. a fourth step of selectively forming a highly doped second conductivity type emitter silicon layer on the intrinsic base region; and a fourth step of selectively opening the interlayer insulating film to the extrinsic base region and the collector diffusion layer. 5. A method of manufacturing a semiconductor device is characterized in that it includes at least the steps of step 5.

[0021]

[Operation] Therefore, in the semiconductor device and the manufacturing method thereof according to the present invention, in the Si-HBT, a concave portion is provided on the surface of the collector epitaxial growth layer made of silicon (Si) on the buried collector layer, and a concave portion is provided in the concave portion. Embedded silicon germanium (Si1-XGeX)
), and the extrinsic base region is formed in the collector epitaxial growth layer, that is, in silicon (Si) so as to be in contact with the intrinsic base region, so that the extrinsic base resistance can be reduced. ,
Furthermore, since each of the intrinsic base region and the extrinsic base region is formed within the collector epitaxial growth layer, it is possible to miniaturize the element structure and, by extension, to increase the integration of the device.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to FIGS. 1 to 6.

FIG. 1 is a sectional view schematically showing the general structure of a semiconductor device to which an embodiment of the present invention is applied, in this case a Si-HBT.
1A and 1B are cross-sectional views sequentially schematically showing the main manufacturing steps of the HBT.

First, the Si-HBT according to the embodiment of FIG.
We will describe the configuration of

That is, the Si-
In the configuration of the HBT, 1 is a P-type silicon substrate, 2 is an N+ type buried collector layer selectively buried in the silicon substrate 1, and 3 is a silicon ( This figure shows an N-type collector epitaxial layer formed by selectively epitaxially growing Si) and diffusing N-type impurities, where 4 is an oxide film for isolation between elements, and 14 is directly under the oxide film 4 for isolation between elements. P+ type diffusion layer for channel stop selectively formed in 8
is an interlayer insulating film such as an oxide film.

Further, reference numeral 16 denotes a silicon germanium (Si1
-XGeX), and 17 is a P+ type external base region that is selectively diffused and formed in contact with both sides of the intrinsic base region 16 on the collector epitaxial layer 3. It is.

Further, 9 is an N+ type collector diffusion layer selectively diffused in the N+ type buried collector layer 2, and 10 is an N+ type emitter silicon selectively formed on the intrinsic base region 16. layers, 11, 12,
and 13 are a base electrode, an emitter electrode, and a collector electrode formed respectively corresponding to the corresponding layers.

Next, the manufacturing process of the Si-HBT in the embodiment shown in FIGS. 2 to 6, which corresponds to the structure shown in FIG. 1, will be described.

Also in the case of the Si-HBT of this embodiment having the configuration shown in FIG. 1, in the first step (FIG. 2), the inside of the P-type silicon substrate 1 is first implanted by ion implantation or the like. After introducing N type impurities such as arsenic at a high concentration and performing heat treatment to form an N+ type buried collector layer 2, silicon (Si) is grown epitaxially on the N+ type buried collector layer 2. At the same time, an N-type impurity such as arsenic is introduced and heat treated to form an N-type collector epitaxial layer 3, and then an oxide film is formed on the corresponding both sides of the N-type collector epitaxial layer 3. After selectively digging trenches in each of them to a depth exceeding the N+ type buried collector layer 2 by anisotropic etching using a mask such as P-type impurities are introduced at a high concentration and heat treated to form a P+ type diffusion layer 14 for channel stop.Furthermore, the inside of the trench is filled with a CVD oxide film or the like to form an oxide layer for isolation between elements. A film 4 is formed.

In the second step (FIG. 3), the N
The corresponding region on the mold collector epitaxial layer 3 is selectively oxidized by the LOCOS method using a nitride film as a mask to form an oxide film portion, and the nitride film used as the mask as well as the selected The oxidized oxide film portion is removed by chemical etching or the like to form a concave portion 15 for forming an intrinsic base region corresponding to the oxide film portion, and the corresponding portion on the buried collector layer 2 is removed. N type impurities such as phosphorus are introduced into the region at a high concentration by ion implantation using a resist as a mask, and heat treatment is performed to selectively form an N+ type collector diffusion layer 9.

In the third step (FIG. 4), the N
M with a resist as a mask on the mold collector epitaxial layer 3
Silicon germanium (Si1-XG) doped with P-type impurities such as boron by BE method, CVD method, etc.
eX) is deposited, and then the deposited silicon/germanium is selectively removed by etching using a resist or the like as a mask, except for the inside of the recessed part 15. Only then can the same silicone
A P-type intrinsic base region 16 made of germanium (Si1-XGeX) is formed, and each region in contact with both sides of the P-type intrinsic base region 16 in silicon (Si) of the N-type collector epitaxial layer 3 is formed. For the area part,
P-type impurities such as boron are introduced at a high concentration by ion implantation using a resist as a mask, and heat treatment is performed to selectively form each P+ type external base region 17.

In the fourth step (FIG. 5), the N+
The entire surface including the type collector diffusion layer 9, the P type intrinsic base region 16, and each P+ type extrinsic base region 17 is
After depositing an interlayer insulating film 8 such as an oxide film by a VD method or the like, a P-type intrinsic base region 1 is formed in the interlayer insulating film 8.
A predetermined portion corresponding to 6 is etched by etching using a resist or the like as a mask, a through hole is opened in the corresponding portion, and polycrystalline silicon or the like is deposited on the entire surface by CVD method, and the deposited portion is N-type impurities such as arsenic are introduced into the polycrystalline silicon at a high concentration by ion implantation, etc., and the polycrystalline silicon into which the N-type impurities are introduced corresponds to the P-type intrinsic base region 16. After patterning by etching using a resist or other mask so as to leave a predetermined portion,
This is heat treated to selectively form an N+ type emitter silicon layer 10.

In the fifth step (FIG. 6), each predetermined portion of the interlayer insulating film 8 corresponding to the P+ type external base region 17 and the N+ type collector diffusion layer 9 is
Etched by etching using resist etc. as a mask,
After opening through holes in each of the corresponding parts, a film of aluminum (Al) or the like as an electrode material is formed on the entire surface including each part by sputtering or the like,
and patterning the formed aluminum film by etching using a resist or the like as a mask,
For each applicable region and each applicable layer, each electrode,
That is, in this case, for each P+ type external base region 17, each base electrode 11, for the N+ type emitter silicon layer 10, an emitter electrode 12, and for the N+ type collector diffusion layer 9. is the collector electrode 13
Let each of us choose and form them.

That is, in this way, the structure of the Si-HBT in the embodiment shown in FIG. 1 can be manufactured as expected.

Therefore, in this embodiment, N
A recessed part 15 is provided on the surface of the N-type collector epitaxial layer 3 made of silicon (Si) on the +-type buried collector layer 2, and silicon germanium (Si1-) containing P-type impurities is embedded in the recessed part 15. Since the P type intrinsic base region 16 is formed by XGeX) and the P+ type external base region 17 is formed in the collector epitaxial layer 3 in contact with the intrinsic base region 16, the external base resistance is reduced. In addition, these intrinsic base regions 16 and extrinsic base regions 17 can be
Since it is formed within the epitaxial layer 3, the device structure can be miniaturized.

In the configuration of the above embodiment, the concave portion 15 on the surface of the N-type collector epitaxial layer 3 for burying the P-type intrinsic base region 16 is formed by forming an oxide film by the LOCOS method and removing the oxide film. In the above description, the N-type collector epitaxial layer 3 may be formed by directly processing the N-type collector epitaxial layer 3 by dry etching using a resist or the like as a mask. - Although the Si-HBT using a bandgap base has been described, a PNP type may also be used, and similar actions and effects can be obtained.

[0037]

[Effects of the invention] As described above in detail through the examples,
According to the semiconductor device and the manufacturing method thereof according to the present invention, in a Si-HBT, a highly concentrated buried collector layer of a second conductivity type is formed on a silicon substrate of a first conductivity type, and silicon (Si)
A concave portion is selectively provided on the surface of the collector epitaxial growth layer of the second conductivity type, and silicon germanium (silicon germanium) containing impurities of the first conductivity type is embedded in the concave portion.
An intrinsic base region of the first conductivity type is formed using Si1-XGeX), and a highly concentrated extrinsic base region of the first conductivity type is selectively formed in contact with the intrinsic base region on the collector epitaxial growth layer. Therefore, the external base resistance in the device configuration can be effectively reduced, and each base region of the first conductivity type intrinsic base region and the highly concentrated first conductivity type extrinsic base region is Since it is formed in the collector epitaxial growth layer of the second conductivity type, it exhibits excellent features such as making it easier to miniaturize the element structure itself and, in turn, easily achieve higher integration of the device. It's something you get.

[Brief explanation of the drawing]

FIG. 1 is a silicon-hetero bipolar transistor (Si-H
FIG. 2 is a cross-sectional view schematically showing the outline of the main part configuration in BT.

FIG. 2 is a schematic cross-sectional view showing an outline of a first step in manufacturing a Si-HBT according to the embodiment configuration of FIG. 1;

FIG. 3 is a schematic cross-sectional view showing an outline of the second step of the same as above.

FIG. 4 is a schematic cross-sectional view showing an outline of the third step of the same.

FIG. 5 is a schematic cross-sectional view showing an outline of the fourth step of the same.

FIG. 6 is a schematic cross-sectional view showing an outline of the fifth step of the same.

FIG. 7 is a cross-sectional view schematically showing an outline of the main part configuration of a conventional Si-HBT.

8 is a schematic cross-sectional view showing an outline of the first step in manufacturing the Si-HBT according to the conventional structure shown in FIG. 7; FIG.

FIG. 9 is a schematic cross-sectional view showing an outline of the second step of the same.

FIG. 10 is a schematic cross-sectional view showing an outline of the third step of the same.

FIG. 11 is a schematic cross-sectional view showing an overview of the fourth step of the same.

FIG. 12 is a schematic cross-sectional view showing an outline of the fifth step of the same.

FIG. 13 is a schematic cross-sectional view showing an outline of the sixth step of the same.

FIG. 14 is a schematic cross-sectional view showing an outline of the seventh step of the same.

[Explanation of symbols]

1 P-type silicon substrate 2 N+-type buried layer 3 N-type collector epitaxial growth layer (collector epitaxial layer) 4 Inter-element isolation oxide film 8 Interlayer insulating film 9 N+-type collector diffusion layer 10 N+-type emitter silicon layer 11 Base electrode 12 Emitter Electrode 13 Collector electrode 14 P+ type channel stop diffusion layer 15 Concave portion 16 P type intrinsic base region 17 P+ type external base region

Claims (2)

[Claims] 1. A highly concentrated buried collector layer of a second conductivity type formed on a silicon substrate of a first conductivity type; silicon (Si) selectively grown epitaxially on the buried collector layer; A collector epitaxial growth layer of a second conductivity type is formed by diffusing impurities of a type, and silicon germanium (Si1- a first conductivity type intrinsic base region formed by embedding XGeX); a highly doped first conductivity type external base region selectively formed in contact with the intrinsic base region on the collector epitaxial growth layer; and the intrinsic base region. It is characterized by comprising at least a highly doped emitter silicon layer of the second conductivity type selectively formed on the buried collector layer and a collector diffusion layer of the highly doped second conductivity type selectively formed on the buried collector layer. semiconductor devices. 2. A highly concentrated buried collector layer of a second conductivity type is formed on a silicon substrate of a first conductivity type, and silicon (Si) is selectively epitaxially grown on the buried collector layer, and a silicon substrate of a second conductivity type is formed. a first step of diffusing impurities to form a collector epitaxial growth layer of a second conductivity type; and selectively forming a concave portion in a predetermined region on the surface of the collector epitaxial growth layer;
A high concentration second layer is formed in the corresponding region on the buried collector layer.
a second step of selectively forming a collector diffusion layer of a conductivity type; and a second step of burying silicon germanium (Si1-XGeX) containing impurities of a first conductivity type into the concave portion on the surface of the collector epitaxial growth layer. A third step of forming an intrinsic base region of conductivity type and selectively forming a highly concentrated extrinsic base region of first conductivity type in contact with the intrinsic base region, and covering the surfaces thereof with an interlayer insulating film. and selectively opening the interlayer insulating film with respect to the intrinsic base region, and selectively forming a highly concentrated emitter silicon layer of the second conductivity type on the intrinsic base region through the opening. A method of manufacturing a semiconductor device, comprising at least the steps of step 4 and a fifth step of selectively opening the interlayer insulating film to the external base region and the collector diffusion layer.