JPH04369927A - PLL oscillator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase-locked loop) oscillator, and more particularly to an effective technique used in a PLL oscillator used in a mobile communication system such as a mobile phone.

0002

2. Description of the Related Art PLL oscillators are used as local oscillators in radio equipment, etc. For example, in wireless devices such as mobile phones that have strict limits on power consumption, a method is often used to reduce power consumption by operating the transmitting and receiving sections only when necessary and stopping them at other times. . A PLL oscillator for a wireless device using such a system is required to have an output oscillation frequency that reaches a specified center frequency immediately after power is turned on.

As shown in the block diagram of FIG. 6, a conventional PLL oscillator includes a voltage-controlled oscillator that outputs an oscillation signal with a frequency that corresponds to a control voltage, and a voltage-controlled oscillator that outputs an oscillation signal with a frequency that corresponds to a control voltage. It consists of a phase comparator that outputs a voltage that is output from the phase comparator, and a high frequency removal means (hereinafter referred to as LPF) that removes high frequency components of the output signal of the phase comparator and outputs a control voltage for controlling the voltage controlled oscillator. A feedback loop was constructed in which the output signal of the controlled oscillator was synchronized with the input signal.

0004

[Problem to be Solved by the Invention] The above-mentioned prior art is based on the LP
When the passband of F is lowered, that is, when the time constant of LPF is set to be large, there is a problem in that the time required to synchronize with the input signal after power-on or after synchronization is lost becomes longer. For example, in a PLL oscillator in a transmitting section of an NTACS mobile phone, a signal obtained by adding a 50 Hz data signal to a reference signal is transmitted through a loop, so the frequency characteristic of the feedback loop must be at least 20 Hz or less. The time constant of the LPF that achieves this has a very large value of 30 seconds or more, making it difficult to synchronize instantly when the power is turned on or after synchronization is lost.

[0005] An object of the present invention is to reduce the time required for synchronization with an input signal after turning on the power or losing synchronization.
The object of the present invention is to provide a LL oscillator.

[0006]

[Means for Solving the Problems] The above object is to store the control voltage of the voltage controlled oscillator in a memory at any time during synchronization, and to apply the most recent control voltage stored in the memory to the control terminal of the voltage controlled oscillator during non-synchronization. This is achieved by controlling the

[0007]

[Operation] The control voltage of the voltage controlled oscillator is stored in the memory at any time during synchronization, and the most recent control voltage stored in the memory is applied to the control terminal of the voltage controlled oscillator during non-synchronization. When the PLL oscillator is turned on or unlocked, the PLL oscillator instantly changes from an asynchronous state to a retractable state, and the time required to synchronize can be significantly shortened. Furthermore, by rewriting the control voltage value stored in the memory as needed, stable operation can be achieved even with aging.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. This figure shows a PLL oscillator as an embodiment of the present invention that oscillates in synchronization with a reference signal, where 1 is a reference signal input terminal, 2 is an oscillation output terminal, 3 is a phase comparator, and 4 is a high-frequency component. 5 is a voltage controlled oscillator, 6 is a voltage generating means, 7 is a control means, 8 is a memory, 9 is a lock detector, and 13 is a switch.

The operation of the PLL oscillator shown in FIG. 1 will be explained. Voltage controlled oscillator 5 outputs an oscillation signal to oscillation output terminal 2. The phase comparator 3 inputs the reference signal and the oscillation signal of the voltage controlled oscillator 5, and outputs a control voltage according to the phase difference between the two signals to the high frequency component removing means 4. The high frequency component removing means 4 removes the high frequency component of the control voltage and outputs it to the control terminal of the voltage controlled oscillator 5. The memory 8 stores an initial value of a control voltage that causes the voltage controlled oscillator 5 to oscillate at a specified center frequency. The control means 7 controls the switch 13 so that the PLL becomes a closed loop when the lock detector 9 detects the synchronization state, and changes the initial value stored in the memory 8 and the control voltage of the voltage controlled oscillator 5. Memory 8 uses the difference as a correction value
The data is controlled to be stored at any time. When the lock detector 9 detects an asynchronous state, the switch 13 is controlled so that the PLL becomes open loop, and the initial value stored in the memory 8 and the correction value are added and applied to the control terminal of the voltage controlled oscillator 5. control to do so. The voltage controlled oscillator 5 to which the voltage stored in the memory 8 is applied oscillates in the vicinity of the synchronous frequency, and the PL
The L oscillator instantly becomes retractable. When the PLL oscillator becomes retractable, the lock detector 9 detects the synchronization condition and switches the switch 1 so that the PLL is closed loop again.
3 and stores the correction value in the memory 8. Note that the cycle and timing for storing the correction value in the memory 8 are arbitrary. Further, a D/A converter may be used as means for generating the voltage stored in the memory 8. At this time, the precision of the control voltage of the voltage controlled oscillator 5 needs to be about 16 bits, but by storing the upper 8 bits as the initial value and the lower 8 bits as the correction value, it is possible to use a D/A converter with low precision. Can be done.

FIG. 14 shows a PLL oscillator according to the present invention and a conventional PL oscillator.
An example of the transient response characteristics when the power of the L oscillator is turned on is shown. In this figure, the vertical axis represents the control voltage V of the voltage controlled oscillator 5, and the horizontal axis represents the elapsed time T from power-on. From this figure, it can be seen that the time t1 until synchronization of the PLL oscillator of the present invention is much shorter than that of the conventional PLL oscillator t2.

According to this embodiment, the initial value of the control voltage of the voltage controlled oscillator 5 is stored in the memory 8, and the memory 8 is stored at the time of synchronization.
The difference between the initial value stored in the memory 8 and the control voltage of the voltage controlled oscillator 5 is stored as a correction value in the memory 8 at any time. By applying the voltage to the control terminal, the PLL oscillator becomes instantly ready for retraction, and the time required for synchronization can be significantly shortened. Furthermore, by updating the correction value as needed, stable operation can be obtained even against changes over time.

FIG. 2 is a block diagram showing a second embodiment of the invention. This embodiment differs from the first embodiment in that it includes an environmental state detector 14 that detects at least the ambient temperature. The operation of the PLL oscillator shown in FIG. 2 will be explained below. The memory 8 stores initial values of control voltages that cause the voltage controlled oscillator 5 to oscillate at a specified center frequency as an array corresponding to environmental conditions. The control means 7 controls the switch 13 so that the PLL becomes a closed loop when the lock detector 9 detects the synchronization state, and controls the initial value corresponding to the environmental state detected by the environmental state detector 14 and the voltage controlled oscillator. The difference between the control voltages 5 and 5 is controlled to be stored in the memory 8 as a correction value at any time. When the lock detector 9 detects an asynchronous state, the switch 1 is set so that the PLL becomes open loop.
3, the voltage controlled oscillator 5 adds the initial value and correction value corresponding to the environmental state detected by the environmental state detector 14.
Control the voltage to be applied to the control terminal of Here, the method of storing data in the memory 8 is, for example, from -20 to +80°C.
It is also possible to allocate addresses corresponding to temperature ranges in steps of 0° C. and store the control voltages in each temperature range in the corresponding addresses. The voltage controlled oscillator 5 to which the voltage stored in the memory 8 is applied oscillates in the vicinity of the synchronous frequency,
The PLL oscillator instantly becomes retractable. When the PLL oscillator becomes retractable, the lock detector 9 detects the synchronized state, controls the switch 13 so that the PLL becomes closed loop again, and stores the correction value in the memory 8.

According to this embodiment, the initial values of the control voltages that cause the voltage controlled oscillator 5 to oscillate at a specified center frequency are stored in the memory 8 as an array corresponding to the environmental conditions, and the initial values stored in the memory 8 at the time of synchronization are The difference between the control voltage of the voltage controlled oscillator 5 and the control voltage of the voltage controlled oscillator 5 is stored in the memory 8 at any time as a correction value, and the initial value stored in the memory 8 and the correction value are added at the time of non-synchronization, and the difference is applied to the control terminal of the voltage controlled oscillator 5. By applying
The PLL oscillator becomes ready to pull in instantly, and the time required to synchronize can be significantly shortened. Furthermore, by selecting a correction value that corresponds to the environmental condition, stable operation can be obtained even with temperature changes.

FIG. 3 is a block diagram showing a third embodiment of the present invention. The operation of the PLL oscillator shown in FIG. 3 will be explained below. The memory 8 stores an initial value of a control voltage that causes the voltage controlled oscillator 5 to oscillate at a specified center frequency. This initial value can be determined, for example, by measuring a control voltage that makes the output of the voltage controlled oscillator a specified center frequency during adjustment at the time of shipment, and storing this in the memory 8. The control means 7 controls the switch 13 so that the PLL becomes a closed loop when the lock detector 9 detects the synchronized state,
When the lock detector 9 detects an asynchronous state, the switch 13 is controlled so that the PLL becomes open loop, and the initial value stored in the memory 8 is controlled to be applied to the control terminal of the voltage controlled oscillator 5. The voltage controlled oscillator 5, to which the voltage stored in the memory 8 is applied, oscillates at a frequency very close to the synchronous frequency, and the PLL oscillator instantly becomes capable of being pulled in. PLL
When the oscillator is enabled to retract, the lock detector 9 detects the synchronization condition and controls the switch 13 so that the PLL is closed loop again.

According to this embodiment, the initial value of the control voltage of the voltage controlled oscillator 5 is stored in the memory 8, and the initial value stored in the memory 8 is applied to the control terminal of the voltage controlled oscillator 5 at the time of non-synchronization. As a result, the PLL oscillator becomes instantly ready for retraction, and the time required for synchronization can be significantly shortened.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention. This embodiment includes an environmental state detector 14 that detects at least the ambient temperature. The operation of the PLL oscillator shown in FIG. 4 will be explained below. The memory 8 stores initial values of control voltages that cause the voltage controlled oscillator 5 to oscillate at a specified center frequency as an array corresponding to environmental conditions. The control means 7 controls the switch 13 so that the PLL becomes a closed loop when the lock detector 9 detects a synchronous state, and so that the PLL becomes an open loop when the lock detector 9 detects an asynchronous state. The switch 13 is controlled to apply an initial value corresponding to the environmental state detected by the environmental state detector 14 to the control terminal of the voltage controlled oscillator 5 . Here, the method of storing data in the memory 8 may be, for example, assigning addresses corresponding to temperature ranges from -20 to +80 degrees Celsius in steps of 10 degrees Celsius, and storing the control voltages in each temperature range in the corresponding addresses. The voltage controlled oscillator 5, to which the voltage stored in the memory 8 is applied, oscillates at a frequency very close to the synchronous frequency, and the PLL oscillator instantly becomes capable of being pulled in. When the PLL oscillator becomes retractable, the lock detector 9 detects the synchronization state and the PLL oscillator is activated again.
The switch 13 is controlled so that the loop is closed.

According to this embodiment, the initial values of the control voltages that cause the voltage controlled oscillator 5 to oscillate at a specified center frequency are stored in the memory 8 as an array corresponding to the environmental conditions, and are stored in the memory 8 during asynchronous times. By applying the initial value to the control terminal of the voltage controlled oscillator 5, the PLL oscillator becomes instantly ready for retraction, and the time required for synchronization can be significantly shortened. Furthermore, by selecting the initial value of the control voltage that corresponds to the environmental condition, stable operation can be obtained even with temperature changes.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention. The operation of the PLL oscillator shown in FIG. 4 will be explained below. The high frequency component removing means 4 is a lag lead filter consisting of resistors 10 and 11 and a capacitor 12. The memory 8 stores the initial value of the charging voltage of the capacitor 12 when the voltage controlled oscillator 5 oscillates at a specified center frequency. When the lock detector 9 detects the synchronization state, the control means 7 controls the switch 13 so that the PLL becomes a closed loop, and calculates the difference between the initial value stored in the memory 8 and the charging voltage of the capacitor 12. Memory 8 as correction value
control so that it is memorized at any time. When the lock detector 9 detects an asynchronous state, the switch 13 is controlled so that the PLL becomes open loop, and the initial value and the correction value stored in the memory 8 are added and the capacitor 12 is charged. . The capacitor 12 to which the voltage stored in the memory 8 is applied is instantly charged. Generally, a high resistance is selected for the resistor 10 in order to stabilize the loop, so that the charging voltage of the capacitor 12 is applied almost as is to the control terminal of the voltage controlled oscillator 5. As a result, the voltage controlled oscillator 5 oscillates very close to the synchronous frequency, and the PLL oscillator instantaneously enters a state in which it can be pulled in. When the PLL oscillator becomes retractable, the lock detector 9 detects the synchronized state, controls the switch 13 so that the PLL becomes closed loop again, and stores the correction value in the memory 8.

According to this embodiment, the initial value of the charging voltage of the capacitor 12 when the voltage controlled oscillator 5 oscillates at a specified center frequency is stored in the memory 8, and the initial value stored in the memory 8 and the capacitor 12 are stored at the time of synchronization. The difference between the charging voltage of
By charging the PLL oscillator to 2, the PLL oscillator becomes instantly ready for retraction, and the time required for synchronization can be significantly shortened. Furthermore, by updating the correction value as needed, stable operation can be obtained even against changes over time.

[0021]

[Effects of the Invention] According to the present invention, by setting the control voltage of the voltage controlled oscillator to a voltage that makes the specified center frequency when the power is turned on or when synchronization is lost, the PLL oscillator can instantly change from an asynchronous state to a state in which it can be pulled in. , the time it takes to synchronize can be significantly reduced. Furthermore, by rewriting the voltage values stored in the memory as needed, stable operation can be achieved even with aging. Furthermore, by providing an environmental state detector and making corrections corresponding to changes in the surrounding environment such as temperature, stable operation can be achieved even in the face of environmental changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;

FIG. 2 is a block diagram showing a second embodiment of the present invention;

[Figure 3]
A block diagram showing a third embodiment of the present invention,

FIG. 4 is a block diagram showing a fourth embodiment of the present invention;

FIG. 5 is a block diagram showing a fifth embodiment of the present invention;

[Figure 6] Conventional PLL
Block diagram showing the configuration of the oscillator,

[Figure 7] PLL of the present invention
2 is a graph showing an example of transient response characteristics of an oscillator and a conventional PLL oscillator when power is turned on.

[Explanation of symbols]

1...Input terminal, 2...Output terminal, 3...phase comparator, 4...High frequency component removal means, 5...voltage controlled oscillator, 7...control means, 8...Memory, 9...Lock detector, 13...Switch, 15...Subtractor, 16... Adder.

Claims (9)

[Claims] 1. A voltage controlled oscillator that outputs an oscillation signal with a frequency that corresponds to a control voltage; a phase comparator that outputs a voltage that corresponds to a phase difference between an output signal of the voltage controlled oscillator and a reference signal; In a PLL oscillator provided with a high-frequency component removing means for removing a high-frequency component of an output signal of a comparator and outputting a control voltage of the voltage controlled oscillator, a control means, a memory, and the PLL oscillator are in an asynchronous state or a synchronized state. A lock detector is provided for determining whether the voltage controlled oscillator is in a state and outputting a signal corresponding to the state, the memory stores an initial value of a control voltage for causing the voltage controlled oscillator to oscillate at a specified center frequency, and the control means When the lock detector detects the synchronization state,
The difference between the initial value stored in the memory and the control voltage of the voltage controlled oscillator is stored as a correction value in the memory at any time, and when the lock detector detects an asynchronous state, the difference is stored in the memory as a correction value. A PLL oscillator characterized in that the PLL oscillator is controlled so that an initial value and a correction value are added and applied to a control terminal of the voltage controlled oscillator. 2. According to claim 1, an environmental condition detector for detecting at least an ambient temperature is provided, and the memory is configured to set an initial value of a control voltage for causing the voltage controlled oscillator to oscillate at a specified center frequency in accordance with an environmental condition. The control means detects an environmental state from the environmental state detector when the lock detector detects a synchronized state, and stores an initial value corresponding to the environmental state and the voltage controlled oscillator. The difference in control voltage is stored as a correction value in the memory at any time, and when the lock detector detects an asynchronous state, the environmental state is detected by the environmental state detector, and an initial value corresponding to the environmental state is set. A PLL oscillator that is controlled to add a correction value and apply the added value to a control terminal of the voltage controlled oscillator. 3. A voltage controlled oscillator that outputs an oscillation signal with a frequency that corresponds to a control voltage; a phase comparator that outputs a voltage that corresponds to a phase difference between an output signal of the voltage controlled oscillator and a reference signal; In a PLL oscillator provided with a high-frequency component removing means for removing a high-frequency component of an output signal of a comparator and outputting a control voltage of the voltage controlled oscillator, the control means, the memory, and the PLL oscillator are in an asynchronous state or a synchronous state. A lock detector is installed that determines whether the
The memory stores an initial value of a control voltage that causes the voltage controlled oscillator to oscillate at a specified center frequency, and the control means stores the initial value stored in the memory when the lock detector detects an asynchronous state. is applied to the control terminal of the voltage controlled oscillator.
LL oscillator. 4. According to claim 3, an environmental condition detector for detecting ambient temperature is provided, and the memory is configured to arrange an initial value of a control voltage that causes the voltage controlled oscillator to oscillate at a specified center frequency in a manner corresponding to the environmental condition. When the lock detector detects an asynchronous state, the control means detects the environmental state from the environmental state detector and applies an initial value corresponding to the environmental state to the control terminal of the voltage controlled oscillator. A PLL oscillator that controls the 5. The PLL oscillator according to claim 1,
The high frequency component removing means is a filter provided with a capacitor, the memory stores an initial value of the charging voltage of the capacitor when the voltage controlled oscillator oscillates at a specified center frequency, and the control means is a filter provided with a capacitor. When the lock detector detects a synchronized state, the difference between the initial value stored in the memory and the voltage charged in the capacitor is stored in the memory as a correction value at any time, and the lock detector A PLL oscillator that controls the capacitor to be charged by adding an initial value and a correction value stored in the memory when the device detects an asynchronous state. 6. In claim 2, the high-frequency component removing means is a filter including a capacitor, and the memory is configured to set an initial value of a control voltage for causing the voltage controlled oscillator to oscillate at a specified center frequency in accordance with an environmental state. When the lock detector detects a synchronized state, the control means detects an environmental state from the environmental state detector, and stores the initial value corresponding to the environmental state and the charge of the capacitor. The voltage difference is stored in the memory as a correction value at any time,
When the lock detector detects an asynchronous state, the PLL oscillator controls to detect an environmental state from the environmental state detector, add an initial value and a correction value corresponding to the environmental state, and charge the capacitor. 7. In claim 2, the high frequency component removing means is a filter including a capacitor, and the memory stores an initial value of the charging voltage of the capacitor when the voltage controlled oscillator oscillates at a specified center frequency. and the control means charges the capacitor with an initial value stored in the memory when the lock detector detects an asynchronous state. 8. In claim 2, the high-frequency component removing means is a filter including a capacitor, and the memory stores an initial value of the charging voltage of the capacitor when the voltage controlled oscillator oscillates at a specified center frequency. When the lock detector detects an asynchronous state, the control means detects the environmental state from the environmental state detector and sets an initial value corresponding to the environmental state to the capacitor. A PLL oscillator that controls charging. 9. A mobile communication device using the PLL oscillator according to claim 1, 2, 3, 4, 5, 6, 7, or 8.