JPH04372778A - Soft judging and decoding circuit - Google Patents

Abstract

PURPOSE:To simplify a processing, to reduce a memory capacity, and to improve an error rate by a simple constitution by using one likelihood at every one bite at the time of an error correction. CONSTITUTION:An input data signal is viterbi-decoded by a viterbi decoder 12, and transmitted through a bite synchronizing processing circuit 15 to an error correcting circuit 17. The likelihood at every bit is detected by a bit likelihood detecting circuit 13 at the time of the viterbi-decoding, the likelihood being the central value at every bite, for example, the minimum likelihood is searched by a bite likelihood calculating circuit 16, and transmitted to the error correcting circuit 17. Then, the soft judging and decoding processing is operated based on the bite data and the likelihood being the central value at every bite by the error correcting circuit 17.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a soft-decision decoding circuit that performs soft-decision decoding based on likelihoods determined by a Viterbi decoder.

0002

2. Description of the Related Art Digital recording and reproducing apparatuses such as digital VTRs have the advantage of extremely little signal deterioration even after repeated dubbing, copying, etc., but the amount of data recorded and reproduced is enormous. For example, in the so-called D-1 (or 4:2:2) format, which is the standard for component color digital VTRs for broadcast stations and professional use, recording is performed at a rate of approximately 225.2 Mbps, and video tapes with a tape width of 19 mm are recorded. is stored in a cassette and used. This cassette size is S.
, M, and L are defined.

[0003] When considering digital VTRs for general home use (so-called consumer use), if we try to use the D-1 format, the S size of the tape cassette will only be able to record about ten minutes. zu, large L
Even in size, it can record for about an hour and a half,
It is extremely unsuitable for home use. Note that in the so-called D-2 format, which is a standard for composite color digital VTRs, the recording time is longer even if the same cassette is used, but it is still unsuitable for home use.

[0004] Therefore, the present applicant compressed the amount of recorded information in a manner that reduces reproduction distortion and increased the recording density, thereby allowing long-term recording using a small cassette with a tape width of, for example, about 8 mm. Digital V capable of
We are proposing TR.

FIG. 4 is a block circuit diagram showing a schematic configuration on the playback side of an example of such a digital VTR. In FIG. 4, a digital video signal is magnetically recorded on a magnetic tape (videotape) 30 using a so-called partial response class IV method. The magnetic signal recorded on this tape 30 is transmitted to the playback head 3
After the signal is converted into an electrical signal by the head amplifier 32, the signal is amplified by the head amplifier 32. The output signal from the head amplifier 32 is sent to an equalizer circuit (equalizer) 34 and an ATF (automatic track following) processing circuit 35. The output signal from the equalizer circuit 34 has a detection characteristic (1+
D). This detection characteristic (1+D) is partial response class IV.
(1/(1-D2)), which is the precoding characteristic when precoding processing is performed on the recording side to apply the method, and the electromagnetic conversion characteristic (1-D2) when magnetic recording and reproducing on the tape 30 are performed.
This is for restoring the original signal by canceling out the effects of D). In other words, combining these characteristics, (1/(1-D2)) x (1-D) x (1+D) = 1
Therefore, transmission with transfer function=1 is performed. Note that the output signal from the equalizer circuit 34 is sent to a PLL circuit 37 for clock extraction, and the clock component in the reproduced signal is extracted.

The output signal from the encoder 36 is subjected to maximum likelihood decoding processing in a Viterbi decoding circuit 38 and sent to a time base correction (so-called TBC, time base collector) circuit 37. The Viterbi decoding circuit 38 utilizes the fact that the electromagnetic conversion system of the signal has a differential characteristic to perform decoding with fewer errors than when performing bit-by-bit decoding, thereby obtaining a digital signal with a sequence of 1's and 0's. The TBC circuit 37 removes jitter in the recording/reproduction system, detects synchronization patterns, and converts symbols (for example, 8 bits =
1 byte) and then restores the synchronized block. The output signal from this TBC circuit 37 is sent to an error correction circuit 40, and error correction processing is performed using an error correction code (parity) added on the recording side. The output signal from the error correction circuit 40 is sent to a video signal processing circuit 41 consisting of, for example, a DSP (digital signal processor), and is used to decompress, for example, if bandwidth compression has been applied on the recording side. Expansion processing etc. are performed.

[0007]

[Problems to be Solved by the Invention] Incidentally, in digital magnetic recording systems that require high-density recording as described above, it is desirable to strengthen error correction in order to improve the quality of reproduced signals. However, if you increase the parity to improve the correction ability, the redundancy will increase and the amount of data will increase. Therefore, the soft decision method is considered to be a promising method for increasing error correction capability without increasing redundancy.

However, the above-mentioned soft decision method generally has the disadvantage that the circuit scale increases. In addition, the above error correction is usually performed using a fixed number of bits (e.g. 8 bits = 1 byte).
A soft decision method suitable for such error correction is desired.

The present invention has been made in view of the above circumstances, and aims to provide a soft-decision decoding circuit that can realize soft-decision error correction with a simple configuration and improve the error rate.

0010

[Means for Solving the Problems] A soft decision decoding circuit according to the present invention includes Viterbi decoding means for Viterbi decoding an input signal;
a symbol-by-symbol likelihood detection means for summarizing the bit-by-bit likelihood obtained by the Viterbi decoding means for each symbol of a certain number of bits and outputting the likelihood for each symbol; and an output signal from the Viterbi decoding means. The above-mentioned problem is solved by having an error correction means for performing error correction on a symbol-by-symbol basis based on the likelihood from the symbol-by-symbol likelihood detection means.

[0011] Here, for example, one symbol is 8.
The bit (1 byte) is used as the unit, and the likelihood for each symbol is the minimum (worst) of the likelihoods for each bit of one symbol of data, or the likelihood of each bit is used as the likelihood for each symbol. An average value can be used.

0012

[Operation] Soft-decision error correction can be realized using one likelihood per symbol consisting of a plurality of bits, and the error rate can be improved with a simple configuration.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block circuit diagram showing a schematic configuration of a soft decision decoding circuit according to an embodiment of the present invention. This figure 1
, the input terminal 11 is supplied with a data signal such as the output from the (1+D) detection characteristic circuit 36 of the digital VTR shown in FIG. It is being

The Viterbi decoder 12 utilizes the fact that the electromagnetic conversion system of the signal has differential characteristics to perform decoding with fewer errors than when decoding is performed bit by bit. At this time,
The bit likelihood detection circuit 13 calculates the likelihood for each bit. The likelihood is a value representing the degree of reliability or certainty of how accurate the decoded data is. Here, when considering, for example, a waveform as shown in FIG. 2 as an input signal to the Viterbi decoder 12, the likelihood CV is as follows.
The square of the error between the sample value and the threshold value Δth can be used. That is, in FIG. 2, the optimal input signal level that can be achieved when there is no noise or distortion in the transmission path is A,
0, A', and each sampling time point t1, t2, t
The sample values at 3,... are x1 and x2, respectively.
, x3, ..., CVi = |Δth-xi |2
It is expressed as i=1, 2, 3, . From this, the likelihood CV is the maximum (most likely) value Δ when the input signal level is the above optimal level A, 0, A'.
th2, and when it is above the threshold Δth level, the minimum (
(least reliable) value 0.

The Viterbi decoder 12 and bit likelihood detection circuit 13 add the above-mentioned likelihood information together with the 1 and 0 signals of the decoded data and send them to the TBC (time base correction) circuit 14 at the subsequent stage. The byte synchronization processing circuit 15 in the TBC circuit 14 performs the same operation as the TBC circuit 39 in FIG. 1
(byte) and performs an operation to form a synchronized block. Furthermore, in the embodiment of the present invention, a byte likelihood calculation circuit 16 is provided to calculate the likelihood for each symbol (for example, for each byte), and also regarding the likelihood information for each bit from the bit likelihood detection circuit 13. The above-mentioned symbols (bytes) are grouped together. Byte synchronization processing circuit 15
The data in symbol (byte) units is sent to the error correction circuit 17, and soft-decision error correction processing is performed using the likelihood in symbol (byte) units from the byte likelihood calculation circuit 16. be.

The operation of the byte likelihood calculation circuit 16 will now be described with reference to FIG. 3. In FIG. 3, a series of bit strings {bi} is a judgment value of the Viterbi decoding, and takes a value of 1 or 0. The likelihood CVi is calculated for each of these bits bi, and this likelihood CVi
is data of one word bit length indicating how correct the corresponding bit bi is. In the byte synchronization processing circuit 15, the bit string {bi} is synchronized and grouped in symbol units (byte units), and for example, 8 bits bk, bk+1, . . . , bk+7 form one symbol (one byte). This is the data. In the byte likelihood calculation circuit 16, each of these bits bk, bk+
1 , ..., bk+7 respectively, the eight likelihoods CVk , CVk+1 , ..., CVk+7 are set to 1.
The likelihoods are summarized into the likelihoods representing the symbol (byte). Specifically, eight likelihoods CVk, CVk
The minimum (worst) likelihood CVmin of +1, . Instead of this minimum likelihood CVmin, 8 likelihoods CV
The average value CVmean of each value of k, CVk+1, . . . , CVk+7 may be used as the representative value of the symbol (byte).

The error correction circuit (decoder) 17 uses the likelihood of each symbol (byte) from the byte likelihood calculation circuit 16 to soften the data compiled in symbol units (for example, byte units). Performs judgment error correction processing. Although various methods can be considered for this soft-decision error correction, one specific example of an adjacent symbol decoder will be described below. This method focuses on the fact that a symbol using a Reed-Solomon (RS) code is composed of multiple bits (for example, 8 bits), and takes advantage of the fact that the probability that one of the constituent bits will be incorrect is maximum. It is used to decode the data. The above likelihood is used to search for this one bit that is likely to be an error.

In an example of this adjacent symbol decoder, first consider an RS (Reed-Solomon) code on a Galois field GF(28). At this time, one symbol (one byte) of the code word is represented using 8 bits of elements on the Galois field GF(2), that is, 0 and 1. That is, αi
For ∈GF(28), αi = (b7 , b6 , b5 , b4 ,
b3 , b2 , b1 , b0 )...It can be expressed in vector expression as shown in (1). In this equation (1), bi represents each bit, and bi ∈{0,1}=
GF(2), and this selection method is based on the Galois field GF(2
8) depends on the primitive polynomial p(x). Specifically, for example, p(x)=x8 +x4 +x3 +x2
+1...(
2) is selected. At this time, for example, α10=(0,1
, 1, 1, 0, 1, 0, 0).

Now, in digital magnetic recording, etc.,
Basically, since processing is performed using binary data, elements on GF(28) are expressed as 8-bit vectors as described above, and recording and reproduction are performed, for example. That is, as reproduced data, this 8-bit vector representation is obtained continuously on the time axis. At this time, if the bit error rate on the input side of the error correction decoder is Pe, then
The probability of 1 bit error out of 8 bits Pr(8→1) is
Pr(8→1) = 8C1 Pe(1-Pe
)7
...(3), the probability that n bits out of 8 bits are wrong Pr(
8→n) is Pr(8→n) = 8Cn Pen
(1-Pe)8-n
...It is expressed as (4). At this time, Pe ≒10-5
Then, for n>2, Pr(8→1) ≫ Pr(8→n)

...(5) holds true. That is, under this level of error rate, errors of 2 bits or more can be ignored.

Therefore, in the following, we will consider the case where 1 bit out of 8 bits becomes an error. Now, let CVj be the likelihood for each bit bj of the symbol (byte) αi input to the error correction circuit (decoder) 17. Among these eight likelihoods, the minimum likelihood is defined as CVmin as shown in FIG. 3 above. Assuming that the bit with the minimum likelihood is bm, when a symbol causes an error, bit bm has the highest probability of being an error among the 8 bits. Therefore, when the above-mentioned symbol αi becomes an error, the probability that the correct symbol is the inverted bit bm is the highest, so the next candidate symbol β to be used instead of the above-mentioned symbol αi is
For i, βi = (b7,...
,xbm,...,b0)
...It can be expressed as (6). x in this formula (6)
bm is xbm =1
if bm =0
=0 if bm =1
...This is an inverter represented by (7).

In this way, the symbol α of the original input data
i and the second candidate symbol βi adjacent to it
By performing error correction using , it is possible to improve the decoding ability of error correction.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but for example, one unit of error correction processing.
A symbol is not limited to one byte (8 bits), and one symbol can be any number of bits such as 4 bits, 12 bits, 16 bits, etc. Also, byte (symbol)
The likelihood calculation circuit 16 outputs, for example, the minimum value likelihood data representing the one byte (symbol), as well as the position information of the bit corresponding to the representative likelihood, and sends it to the error correction processing circuit 17. You may also send it.

[0023]

[Effects of the Invention] As is clear from the above explanation, the soft decision decoding circuit according to the present invention calculates the likelihood for each bit obtained by Viterbi decoding the input signal for each symbol of a certain number of bits. In summary, since error correction is performed on a symbol-by-symbol basis based on the likelihood on a symbol-by-symbol basis and the Viterbi-decoded output signal, a soft decision is made using only one likelihood per symbol consisting of multiple bits. Since error correction can be realized and the amount of data handled in the event of a soft decision error is small, the error rate can be improved with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a schematic configuration of an embodiment of a soft decision decoding circuit according to the present invention.

FIG. 2 is a schematic diagram for explaining the likelihood detection operation of the embodiment.

FIG. 3 is a schematic diagram for explaining a likelihood calculation operation on a symbol-by-symbol basis.

FIG. 4 is a block circuit diagram showing a schematic configuration on the playback side of an example of a digital VTR.

[Explanation of symbols]

11... Data signal input terminal 12... Viterbi decoder 13... Bit likelihood detection circuit 14... TBC (time base correction) circuit 15...
・Byte (symbol) synchronization processing circuit 16...Byte (symbol) likelihood calculation circuit 17...Error correction processing circuit 18...Data signal output terminal

Claims (1)

[Claims] Claim 1: Viterbi decoding means for Viterbi-decoding an input signal, and the likelihood of each bit obtained by the Viterbi decoding means being summarized for each symbol of a certain number of bits, and one representative value for each symbol. a symbol-by-symbol likelihood detection means for outputting a likelihood of A soft decision decoding circuit comprising: