JPH0444342A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an erroneous operation of an element due to a crosstalk by providing a wiring member held at a predetermined constant potential between wiring conductors. CONSTITUTION:A wiring member such as a shield wiring conductor 103 is disposed in parallel along wiring conductors between the conductors 101 and 102 disposed in parallel with one another. If the potential of the conductor 101 (or 102) is varied, a parasitic capacitance C13 (or C23) is charged and discharged. However, the conductor 103 is held, for example, at a predetermined value through an outer VSS line, and a wiring resistance R3 has a small value. Accordingly, the charging/discharging are momentarily conducted. Thus, it does not affect the conductor 102 (or 101). For example, a VSS line is wired at the long side direction of a chip corresponding to a 1MDRAM chip of 10mm of its long side with 50mum of wiring width, and design rule S = 0.5mum is set. In this case, the resistance R3 becomes about 6OMEGA, and its parasitic capacitor C13 becomes 0.346pF. Accordingly, when the capacitance C13 is charged/ discharged, its constant becomes about 2psec, which is extremely short.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to the structure of a semiconductor device, and particularly relates to a wiring structure that reduces the influence of parasitic capacitance.

(Prior Art) Nowadays, more than ever before, there is a demand for semiconductor devices that simultaneously satisfy high integration and high-speed operation. With advances in microfabrication technology, mass production of products with a degree of integration of 0.8 μm rule began in 1989.

FIG. 3 shows a wiring diagram of wiring conductors in a conventional semiconductor device. In the figure, 401 and 402 are wiring conductors, H is the wiring film thickness, L is the wiring width, and S is the wiring conductors 401 and 4.
This is the wiring interval with 02.

Wiring conductors 401 and 402 are arranged parallel to each other.

In the semiconductor device having the above structure, the wiring conductor 401
A parasitic capacitance C12 exists between and 402. Further, there is a junction capacitance between the wiring conductors 401 and 402 and a semiconductor substrate (not shown), and these are connected to C1 and C1, respectively.
Set it to 2. FIG. 4 shows an equivalent circuit of the above wiring conductor. In the same figure, Nl, N2. N20 and N22 are nodes on the wiring conductor, and R2 and R20 are wiring resistances.

FIG. 5 is a diagram showing changes in potential at nodes N1 and N2. The vertical axis represents potential and the horizontal axis represents elapsed time. Parasitic capacitance C12, node N, and potentials v1 and v2 of N2
The relationship can be expressed by the following equation.

△V2-Ce ΔVI (+) However, Ce = CI2 / (C2+ CI2) This coupling ratio (Coupling Ratlo
) Ce is mainly determined by the wiring film thickness H and the wiring width S. Here, it is assumed that the wiring width and the wiring interval S have the same value. This length is determined by the design rule (De
slgn Rule ) and is represented by the wiring interval S. Here, we will look at changes in the potential of node N2 due to changes in the potential of node N1. For example, the potential of node N1 is vI+
When it changes to △■1, the potential of node N2 becomes parasitic capacitance CI2
Due to the presence of , it changes to v2 + Δv2. Since this ΔV2 attenuates after a predetermined period of time, the potential of the node N2 returns to V2. This return rate, that is, the circuit time constant, is the wiring resistance R2
0.

It is determined by R2, junction melting amount C2, and parasitic capacitance CI2 value. FIG. 6 is a diagram showing the relationship between the coupling ratio Cc and the design rule S.

In the figure, it can be seen that as the design rule S becomes narrower, the coupling ratio Cc tends to take a larger value.

Also, as the value of junction capacitance C2 becomes smaller, coupling
The ratio Cc tends to take a large value. Particularly when the circuit time constant is large or when ΔV2 is large, there is a problem in that it takes too much time to recover to the original potential and the element connected to node N22 malfunctions. Recently, there is a strong tendency for the interconnect spacing S to be reduced due to higher integration, and as a result, the parasitic capacitance CI2 tends to further increase. For this reason, the influence was particularly large when elements that perform high-speed switching operations were incorporated. As described above, conventional semiconductor devices have a problem in that crosstalk (mutual interference) occurs between adjacent wiring conductors, resulting in malfunctions.

By the way, if the wiring film thickness H is made smaller in order to reduce the parasitic capacitance CI2, the wiring resistance R12 will increase and the circuit time constant will increase, and if the wiring conductor is made of aluminum or the like, there will be problems such as a decrease in step coverage. Not very practical.

(Problems to be Solved by the Invention) As explained above, there has been a tendency for semiconductor devices to become highly integrated and operate at high speed.

Along with this, the wiring spacing has become narrower while the parasitic capacitance has tended to increase. Therefore, there is a problem in that crosstalk occurs between adjacent wiring conductors and the device malfunctions.

Therefore, the present invention was made in view of the above-mentioned problems.
It is an object of the present invention to provide a highly reliable semiconductor device having a structure in which the influence of parasitic capacitance between wiring conductors is suppressed to prevent crosstalk from occurring and elements do not malfunction.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device of the present invention includes a plurality of wiring conductors formed at predetermined intervals, and a plurality of wiring conductors formed along the length direction of a predetermined wiring conductor in the plurality of wiring conductors. 2. The semiconductor device according to claim 2, further comprising a wiring member formed adjacent to the wiring member at a predetermined interval therebetween, and wherein the wiring member is maintained at a predetermined constant potential. The semiconductor device according to claim (1) is characterized in that the wiring member is maintained at the same potential as a power supply potential or a ground potential, and the semiconductor device according to claim (3) is characterized in that the semiconductor device according to claim (1) )
The semiconductor device described above is characterized in that the wiring member and the plurality of wiring conductors are formed of the same material.

(Function) In the present invention, a wiring member is provided along between adjacent wiring conductors, and when the potential of one wiring conductor changes, which maintains the wiring member at a predetermined constant potential, the parasitic capacitance between the wiring conductor and the wiring member is filled. Discharged. However, this charging and discharging is instantaneously performed via the wiring member. Therefore, it is possible to obtain a highly reliable semiconductor device without crosstalk occurring between adjacent wiring conductors and malfunctioning of elements. (Embodiment) An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a wiring diagram within the semiconductor device of this embodiment. In the figure, the same components as in the conventional example are given the same reference numerals, and their explanations will be omitted. In the same figure, wiring conductor 1
01 and 102 are arranged parallel to each other. A wiring member, for example a shield wiring conductor 103, is arranged between these wiring conductors 101 and 102 in parallel along these wiring conductors. CI3 is the parasitic capacitance between the wiring conductor 101 and the shield wiring conductor 103, and C23 is the parasitic capacitance between the wiring conductor 102 and the shield wiring conductor 103. R3 is the wiring resistance between the shield wiring conductor 103 and the semiconductor substrate (not shown).

The shield wiring conductor 103 has a predetermined potential (for example, V5g,
Vcc, etc.).

The operation of the semiconductor device of this example having the above configuration will be explained. When the potential of the wiring conductor 101 changes, the parasitic capacitance CI3 is charged and discharged. However, since the shield wiring conductor 103 is maintained at a predetermined voltage via, for example, an external Vss line, and the wiring resistance R3 has a small value, this charging and discharging occurs instantaneously. Therefore, the wiring conductor 102 is not affected. Further, even if the potential of the wiring conductor 102 changes, it can be considered in the same manner as above, and therefore the wiring conductor 101 will not be affected.

For example, an IMDR with a wiring width of 50 μm and a long side of 10-1
Consider the case where a Vss line is wired in the long side direction of an AM-sized chip and connected to a shield wiring conductor. At this time, these wiring conductors are formed of aluminum, and the design rule is set to S-0 at 5μ intervals. In this case, wiring resistance R3
is approximately 6Ω, and the parasitic capacitance CI3 is 0.3469F. Therefore, the time constant for charging and discharging the parasitic capacitance CI3 is approximately 2 psec, which is an extremely short time. This is 1/2000 of the case without the shield wiring 503.
corresponds to the time of Therefore, the use of the wiring structure shown in this embodiment in a semiconductor device having an element requiring high-speed switching operation is sufficiently effective.

2, in this embodiment, the shield wiring conductor 103 is provided between the wiring conductors 101 and 102, so that crosstalk caused by the influence of parasitic capacitance and malfunction of the element as in the conventional case is almost eliminated.

By the way, when the shield wiring conductor 103 is removed and the wiring spacing S is made three times the wiring width (the wiring spacing is three times as large as that of the conventional example. S-3L), the parasitic capacitance is the same as that of the conventional example. It is one third of CI2, and the coupling ratio Cc is also about one third. However, the effect of parasitic capacitance is smaller when the shield wiring 103 is installed than when the wiring spacing S is maintained at the above-mentioned interval.

Note that the shield wiring conductor may be made of the same material as the wiring conductor. Further, the shield wiring conductor does not necessarily need to be provided between the wiring conductors, and may be provided only adjacent to the wiring conductor connected to the element whose occurrence of malfunction is to be prevented.

[Effects of the Invention] As explained above, the semiconductor device of the present invention has a structure in which a wiring member maintained at a predetermined constant potential is provided between wiring conductors. Therefore, even if the potential of the wiring conductor changes and crosstalk occurs, the potential of the adjacent wiring conductor will not change and the device will not malfunction. Therefore, a highly reliable semiconductor device can be provided. It is particularly effective for semiconductor devices with high integration and high speed operation.

[Brief explanation of drawings]

Figure 1 is a wiring diagram of the semiconductor device of this example, and Figure 2 is the wiring diagram of the semiconductor device of this embodiment.
3 is a wiring diagram of a conventional semiconductor device, FIG. 4 is an equivalent circuit diagram of the semiconductor device shown in FIG. 3,
FIG. 5 is a diagram showing changes in the potentials of nodes N and N2, and FIG. 6 is a diagram showing the relationship between coupling ratio and design rule. 101.102... Wiring conductor 103... Shield wiring conductor c,, c2... Junction capacitance C10, C23... Parasitic capacitance L... Wiring width N, N2, N2 (,, N2...・Node R
3 R2o...Wiring resistance S...Wiring spacing

Claims (3)

[Claims] (1) A plurality of wiring conductors formed at predetermined intervals, and a wiring member formed adjacent to a predetermined wiring conductor in the length direction of the plurality of wiring conductors and at a predetermined interval therefrom. A semiconductor device comprising: the wiring member being maintained at a predetermined constant potential. (2) The semiconductor device according to claim (1), wherein the wiring member is maintained at the same potential as a power supply potential or a ground potential. (3) The semiconductor device according to claim (1), wherein the wiring member and the plurality of wiring conductors are made of the same material.