JPH044630B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data flow processing device, and more particularly, to a data flow processing device for preventing overflow of a queue memory by controlling reading from the queue memory according to the amount of data stored in the queue memory. The present invention relates to a queue memory device having a queue memory control device.

Conventionally, in a data flow processing device, when a queue memory for queuing data overflows, this overflow is detected and processed as an error, and no means have been taken to prevent this overflow. This overflow error is a fatal error, and even if the process is re-executed, the overflow error will occur again, making it impossible to eliminate the error unless the data flow is changed. It is generally difficult to think about the data flow in advance to avoid overflow errors, and if you run it once and get an error, you have to change the data flow and try again. It was necessary to repeat it. Such work places a heavy burden on users, and a means to prevent hardware overflow has been required.

Furthermore, when control is performed using control data to control the data flow, the number of control data becomes so large that it cannot be ignored compared to the processing data, leading to a decrease in the performance of the entire data flow processing device. .

An object of the present invention is to constantly monitor the amount of data stored in the queue memory, and when the sum of this data amount and the amount of data generated at one time exceeds the capacity of the queue memory, the queue memory is temporarily stored. An object of the present invention is to provide a queue memory device having a queue memory control device that prevents overflow by prohibiting reading from the queue memory or changing the priority order of reading from the queue memory.

The present invention is characterized in that overflow of the queue memory is prevented by constantly monitoring the amount of data stored in the queue memory and controlling reading from the queue memory according to the amount of data. The queue memory (QM) is composed of a data queue (DQ), a generator queue (GQ), and an output queue (OQ).

The queue memory device of the present invention includes a counter that counts the amount of data stored in these queue memories, and a value of the counter that is equal to [(size of queue memory) - (number of data generated at one time by the generator)]. (maximum value)], and a control circuit that controls reading from the cue memory based on the output of the magnitude comparator.

Next, the present invention will be explained with reference to the drawings.
FIG. 1 is a block diagram of a data flow processing device. Before giving a specific explanation of the queue memory device of the present invention, the data flow processing device including its periphery will be explained. In Figure 1, 1 is a bus interface (BI), 2 is a transfer table memory (TT), 3 is a parameter table memory (PT), 4 is a data memory (DM), 5 is a queue memory device (QM), 6 is the processor unit (PU). Transfer table memory 2,
This is a block diagram showing an example in which the parameter table memory 3, data memory, queue memory device 5, and processor unit 6 are connected in this order in a ring shape by a pipeline bus as shown in FIG. Transfer table memory 2 stores data destination addresses. The parameter table memory 3 is accessed using the address of the transfer table memory 2 and stores instructions. The data memory 4 temporarily stores input data for one side of the binary operation. The queue memory device 5 queues data from the data memory 4. The processor unit 6 performs a binary operation (operation performed on two types of input data) or a unary operation (operation performed on one type of input data) on the output of the queue memory device 5.

The bus interface 1 performs data input/output transfer between the pipeline bus and an external bus.

In addition to the above-mentioned functions, the parameter table memory 3 also performs data generation, disappearance, diversion, arrival count, binary control, and address generation for the data memory 4. Input/output data with external circuits includes module number set data, template set data, template read data, data memory set data, data memory read data, reset data invalid data, passing data, execution data,
Contains error status data and processing data.

The module number set data is composed of only the module number, and is data for setting the module number in the module number register inside the bus interface 1 at the time of reset. Once set at reset, the contents of the module number register cannot be changed unless the reset signal becomes active next time. The contents of the module number register are used for comparison with the module number of data taken into the data flow processing device after reset.

The template set data is composed of a module number, an address of the transfer table memory 2, a data value written to the transfer table memory 2, an address of the parameter table memory 3, and a data value written to the parameter table memory 3. The template set data sets template data in the transfer table memory 2 and parameter table memory 3. Template data is data that indicates the content and procedure of processing, and is normally transferred from an external host processor to the inside of the data flow processing device, that is, the transfer table memory 2 and parameter table memory 3 as described above, at the start of a series of processing.
will be forwarded to. The template read data consists of a module number, a transfer table memory 2 address, and a parameter table memory 3 address. The template read data is for reading the template data set in the transfer table memory 2 and the parameter table memory 3, and the module number of the module from which the template data is to be read is entered in the module number of the data. Further, the template read data can be used to check the contents of the template data when an error occurs. After reading the template data, the template read data outputs the read data value to an external circuit, but the module number at this time is replaced with a specific module number (for example, 1) to distinguish it from other data.

Data memory set data is module number,
Consists of data values. Data memory set data is for writing data values into the data memory 4. Addresses used when writing to the data memory 4 are those generated sequentially from 0 to 1 within the parameter table memory 3. The data memory read data consists of a module number and an address of the data memory 4. Data memory read data accesses the data memory 4 using the address of the data memory 4 contained in the data, and outputs the read data value to an external circuit. The reset data consists only of a module number, and is data for canceling an error state after an error state occurs inside the data flow processing device. The error state includes a queue memory 5 overflow error. When this error occurs, the data input to the bus interface 1 is not taken into the data flow processing device but disappears. However, when reset data is input to the bus interface 1, the error condition is canceled and normal processing is performed from then on. In addition to resetting the error state, the reset data has a function of initializing the inside of the data flow processing device, and clears the internal counter and memory. The reset data is bus interface 1
disappears inside. Invalid data consists only of a specific module number (for example, 0), and even if this data is input into the data flow processing device,
It disappears inside the bus interface 1. Passing data is data whose module number does not match the contents of the module number register set at reset, is not invalid data, is not module number set data, and is input from an external circuit. The data passes through the bus interface 1 as is and is output to an external circuit. The execution data consists of a module number, an address of the transfer table memory 2, a control bit, a sign bit, and a data value. The control bit is set when the calculation result in processor unit 6 matches a specified condition. Data with a control bit set is processed by the processor unit 6, and when a branching command is specified, the address of the transfer table memory 2 is changed, and processing different from that of data with a control bit set is executed. . Since no change in processing occurs if a diversion instruction is not specified, control bits are usually used in pairs with a diversion instruction. The branch command is used when it is desired to change the flow of processing depending on the calculation result.

The error status data consists of a module number and an error status. The error status data is stored inside the data flow processing device.
When an overflow error occurs in the queue memory device 5, this data is used to notify an external circuit that an error has occurred. The module number included in the error data is the read content of the module number register set inside the module in which the error occurred.

The processing data consists of a module number, an address of the transfer table memory 2, a control bit, a sign bit, and a data value.

The processing data refers to the transfer table memory 2 and parameter table memory 3, and when the result is an output command, the module number and the address of the transfer table memory 2 are attached by referring to the transfer table memory 2 and parameter table memory 3. Output to external circuit.

The data flow in the pipeline bus will be described in detail below. The execution data consists of a module number, the address of the transfer table memory 2, a control bit, a sign bit, and a data value, and is taken from the external circuit through the bus interface 1 into the pipelined ring-shaped bus, and then transferred. It is sent to table memory 2. In order to enable input from the external circuit to the data flow processing device, the processor unit 6 must not be outputting data, and the number of data stored in the queue memory device 5 must be less than a certain amount (for example, 16 data). Therefore, it is necessary that the module number included in the input data matches the contents of the module number register loaded at the time of reset. Data input from an external circuit to the bus interface 1 is added with a use bit inside the bus interface 1 and sent to the transfer table memory 2. Transfer table memory 2 receives data from bus interface 1 or processor unit 6. The data input to the transfer table memory 2 is composed of a data value, an address of the transfer table memory 2, a use flag, and a template flag.
The use flag is a flag indicating whether data is valid or invalid, and in the transfer table memory 2, the use flags of the output data from the processor unit 6 and the output data from the bus interface 1 are checked and the use flag is "1". ” will be imported. If both use flags have a value of “1”, processor unit 6
Prioritize the output data from . If both use flags have a value of "0", the data is invalid. This invalid data passes through the transfer table memory 3 and data memory 4 and disappears before the queue memory device 5. If the use flag is "1" and the template flag is "0" in the transfer table memory 2, it is assumed that the data is normal processing data, and the transfer table memory 2 is accessed using the address of the transfer table memory 2. , sends the read data to the parameter table memory 3. Use flag is “1” and template flag is “1”
If so, data is written into and read from the transfer table memory 2 using the control bits. The data written into the transfer table memory 2 includes information for distinguishing processing after referring to the transfer table memory 2, and information when referring to the next transfer table memory 2 after data processing in the processor unit 6. , the address when referring to the parameter table memory 3, the address when referring to the parameter table memory 3, and the data sent to the parameter table memory 3 when they operate in pairs. It consists of information for

The parameter table memory 3 is referenced by the address of the parameter table memory 3 included in the data read from the transfer table memory 2. The parameter table memory 3 mainly stores instruction codes, information that controls data exchange when two data pairs operate, the number of output data, and data that goes out to external circuits. It contains the module number, code information for instructing the processing contents of the processor unit 6, and information for state management such as reading and writing of the data memory 4, data two-term queue control, and flow rate control.

Data is written to the parameter table memory 3 when the template flag is set, and during normal processing, permanent information whose contents do not change and temporary information of address information in the data memory 4 are written. It is divided into.
The parameter table memory 3 inputs the use flag, template flag, control bit, instruction code, and data exchange signal from the transfer table 2, and outputs a write enable signal to the data memory 4. The data memory 4 includes a queue for temporarily holding the data that arrived first until both data for a binary operation (operation that takes two types of data as input) is available, a constant for constant operation, It is used to store lookup tables, transition tables for state transition processing, and input/output data. A write enable signal for the data memory 4 is input from the parameter table memory 3. When a binary operation instruction is specified and both data are available, the input data from the parameter table memory 3 and the read data from the data memory 4 are output to the queue memory 5 at the same time. The queue memory device 5 is composed of a data queue and a generator queue. The data queue is used to temporarily hold data when the number of output data from the processor unit 6 is multiple, or when data is input from the bus interface 1, the processor unit 6 becomes busy and cannot input data. It's memory. The generator queue inputs startup data, the number of data generation, and control information for generating numerical values from the data memory, and sends the information to the processor unit 6 when there is a certain amount of free data queue space (in this example, half of the data queues) or more. It outputs the information as to whether it is true or not. The processor unit 6 is an arithmetic circuit having arithmetic operations, logical operations, shifts, comparisons, bit inversions, priority encoding, shunt value generation, and copying functions. Bit inversion is a process in which the bit positions of an input data value are inverted and the result is an output data value.

Priority encoding examines the value of each bit of the input data value in order from the bit with the highest priority to the bit with the lowest priority, and when a bit with a value of "1" appears for the first time, that bit position is determined. This is a process of displaying a binary integer as an output data value.

The shunt looks at the control bit, and if the value is "0", the address of template memory 2 in the input data is output as is as the address of template memory 2 in the output data, and the value of the control bit is If it is "1", the process is to add 1 to the address of the template memory 2 in the input data and output it as the address of the template memory 2 in the output data. Numerical generation looks at the data value in the input data, the number of occurrences, and the increment value, and sequentially adds the increment value to the data value in the input data by the number of occurrences, and generates output data for the number of occurrences. This is the process of This function is used when performing repetitive processing or when generating memory addresses. At this time, the address of the transfer table memory 2 in the output data does not change, and the address of the transfer table memory 2 in the input data is output as is. Copying is a process of checking the data value in the input data and the number of copies, and then copying the data value in the input data to the data value in the output data by the number of times of copying, and outputting the same. At this time, the address of the transfer table memory 2 in the output data becomes a value added one by one to the address of the transfer table memory 2 in the input data in the order of output. The number of input data to the processor unit 6 is one or two, and the number of output data can be specified from 1 to 16. Processing when the number of input data is one is called unary operation,
Processing when the number of input data is two is called binary operation. In the case of a unary operation, the number of input data is one, so there is no need to wait, but in the case of a binary operation, the operation cannot be executed until the two pieces of data are available, so the data that arrives first is stored in the data memory 4. When data arrives later after waiting, it is combined with the data read from the second item queue in the data memory and sent to the processor unit 6 through the queue memory device 5. Start calculation with . That is, execution control is performed using a data flow method for binary operations. When the number of output data is 2 or more, a busy flag is set while outputting, and input from the queue memory 5 is prohibited.

The data output from the queue memory device 5 in the data holding section that processes the data flow processing device includes: (1) Data output to an external circuit.

(2) Data that disappears.

(3) In the case of an operation on two input data (binary operation), the data that arrives first.

(4) Data that generates multiple data examples.

(5) Data to be copied.

(6) Data that results in two data outputs as a result of calculation.

Among these, the number of data will decrease for (1), (2), and (3), and the number of data will increase for (4), (5), and (6).

In particular, in cases (4) and (5), the number of data increases rapidly, and it is effective to control this data in order to prevent overflow of the queue memory.

FIG. 2 is a block diagram showing one embodiment of the present invention, and is a circuit block diagram of the queue memory device 5 in FIG. In the figure, 101 is a data queue memory, 102 is a queue memory control circuit, 1
03 is a generator queue memory, and 104 is a multiplexer. 111 is data written to the data queue memory 101, which is data output from the data memory 4 in FIG. 1 and input to the data queue memory 101. Data 112 is read from the data queue memory 101 and is input to the multiplexer 104.
114 is an address and control signal for the data queue memory 101. 115 is data written to the generator queue memory 103, which is data output from the data memory 4 in FIG. 1 and input to the generator queue memory 103. 116 is an address and control signal for the generator queue memory 103.

117 is data read out from the generator queue memory 103, and is read out from the multiplexer 10.
4 inputs. 118 is a multiplexer 104
The output data is output to the processor unit 6 in FIG. Reference numeral 113 denotes an input selection signal of the multiplexer 104, which selects either the output data 112 from the data queue memory 101 or the output data 117 from the generator queue memory 103 and sets it as output data 118. The data stored in the data queue memory 101 is the data that is output to the processor unit 6 in FIG. 1 via the multiplexer 104, and does not involve generation of data, so the number of data does not increase. The data stored in the generator queue memory 103 is the data that is output to the processor unit 6 in FIG. 1 via the multiplexer 104, and is accompanied by data generation. During this time, the processor unit 6 is in a busy state and does not input data.

The amount of data stored in the data queue memory 101 is limited by the capacity of the data queue memory 101, and if the limit is exceeded, the data queue memory 101
01 will result in an overflow state, making it impossible to obtain correct data processing results. This state is one of the fatal errors, and once the program enters this state, it is impossible to continue the program and the processing is interrupted. Therefore, a means is needed to prevent interruption of this process. In order to prevent interruption of processing, reading from the generator queue memory 103 may be prohibited when there is a possibility that the data queue memory 101 will overflow. Overflow may occur in data queue memory 10.
1 and the maximum amount of data generated by the output data from the generator queue memory 103 exceeds the capacity of the data queue memory 101. Data is no longer read from the generator queue memory 103 and the data queue memory 1
Control is performed so that data is read from 01.

When there is no possibility of overflow occurring,
In order to prevent performance from deteriorating due to data being lost in the data queue memory 101,
Reading from generator queue memory 103 is given priority over reading from data queue memory 101.

FIG. 3 is a block diagram of the queue memory control circuit 102 in FIG. 2.

In the figure, 211 is a counter, 212 is a consolidator, and 213 is a register. 221 is data to be written to the register 213, and 222 is a write pulse to the register 213. An upper limit setting value to prevent the data queue memory 101 from overflowing is preset in the register 213 by a write pulse 222. This value does not change in subsequent processing. 223 is a reset signal for the counter 211, which clears the counter 211 before processing. 224 is a reset signal for the counter 211, which clears the counter 211 before processing. 224 is a clock signal of the counter 211, and when the clock signal 224 is input to the counter 211 while the up/down switching signal 225 is in the UP state, the value of the counter 211 is incremented by one. When the up/down switching signal 225 is in the down state, when the clock signal 224 is input to the counter 211,
The value of counter 211 is decremented by one. The value of the counter 211 indicates the number of data currently stored in the data queue memory 101, and when writing to the data queue memory 101 occurs,
It is incremented by one, and decremented by one when reading from the data queue memory 101 occurs. 226 is the read data from the register 213, that is, the upper limit setting value. Comparator 212 outputs output data 114 from counter 211 and register 21
When the output data 114 from the counter 211 is larger than the output data 226 from the counter 211, the queue memory switching signal, that is, the read inhibit signal 2 from the generator queue memory 103 is
Outputs 27. This signal prohibits reading from the generator queue memory 103, and gives priority to reading from the data queue memory 101.

As explained above, the present invention monitors the amount of data stored in the queue memory in order to prevent overflow of the queue memory that waits for data in a data flow processing device, and reads data from the queue memory to prevent overflow. It is unique in that it is equipped with a cue control device for control. That is, data that generates data and data that does not generate data are stored in separate queue memories, and data that does not generate data is read from the generator queue memory that stores data that generates data. Control is performed based on the amount of data stored in the data queue memory. This control is performed by prohibiting reading from the generator queue when the sum of the maximum amount of data generated at one time and the amount of data in the data queue exceeds the capacity of the data queue. This eliminates the need to modify programs due to overflow errors, and has the effect of allowing programs to run without being aware of overflows.

Note that the only way to avoid overflow of the generator queue memory is to check it at the stage of writing the program and using the compiler. If the generator queue memory overflows, an error will occur, so the process will be interrupted and the program will be rewritten. Specifically, this is avoided by replacing the instructions stored in the generator queue memory with equivalent instructions stored in the data queue memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data flow processing device. FIG. 2 is a circuit block diagram of the queue memory device of the present invention. FIG. 3 is a circuit block diagram of the queue memory control circuit 102 in FIG. 2. In the figure, 1 is a bus interface, 2 is a transfer table memory, 3 is a parameter table memory, 4 is a data memory, 5 is a queue memory, 6 is a processor unit, 101 is a data queue memory, 102 is a queue memory control circuit, 103 is a generator queue memory, 104
is a multiplexer, 111 is write data of the data queue memory 101, 112 is read data of the data queue memory 101, 113 is an input selection signal of the multiplexer 104, 114 is an address and control signal of the data queue memory 101,
115 is write data of the generator queue memory 103, 116 is an address and control signal of the generator queue memory 101, 117 is read data of the generator queue memory 101, and 118 is output data of the multiplexer 104. 211 is a counter, 212 is a comparator, 213 is a register, 221 is a register 213
222 is a write pulse to the register 213, 223 is a reset signal for the counter 211, 224 is a clock signal for the counter 211, 225 is an up/down switching signal for the counter 211, 226 is read data from the register 213, 227 is the output signal of comparator 212.

Claims (1)

[Claims] 1 A queue memory device in a data flow processing device includes a data queue memory in which data waiting for an operation that does not involve generation is stored, a generator queue memory in which data waiting for an operation that involves generation is stored, and the data queue memory a counter that counts the amount of data stored in the memory; a register that stores the capacity of the data queue memory; and a sum of the value of the counter and the maximum amount of data generated from the generator queue memory. but,
and a comparator for determining whether the value exceeds the value of the register, and based on the comparison result from the comparator,
A queue memory device characterized in that reading from the data queue memory and the generator queue memory is selectively controlled.