JPH0447431A - Image memory device - Google Patents

Abstract

PURPOSE:To improve the utilization efficiency of an image memory by constituting the device so that plural image data can be divided and stored arbitrarily in one image memory. CONSTITUTION:In the case an access request to an image memory 1 is executed, when the request destination is a sequence #1 whose priority is the highest, the processing of the sequence #1 is executed. On the other hand,in the case the request destination is not the sequence #1, when it is a sequence #2 whose priority is high secondly, its processing is executed, and in the case the request destination is not the sequence #2, the processing of a sequence #3 whose priority is the lowest is executed. Also, the processing of the sequences #1 - #3 is executed by switching a selecting circuit 2. Moreover, write of image data to the image memory 1 is executed by an address from address generating circuits 31 - 33. In such a way, the utilization efficiency of the image memory can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to an image memory device for effectively and efficiently utilizing an image memory used in an image processing device or the like.

(Prior Art) When storing a plurality of image data in a memory at the same time, conventionally, separate memories are prepared for the number of image data, and each memory stores a plurality of image data.

Fig. 4 shows an example of a conventional image memory device, and this example consists of three series #1 to #3, and the whole is CPL.
It is controlled by Iloo. Series #1~#
3 have the same configuration, each having an image memory 111412, 113 dedicated to each series, and image processing units 121, 122 and 123 that process image data.
and write control circuits 131 and 132°13 that control data writing to the image memories 111 to 113, respectively.
3, and address generation circuits 141, 142, and 143 that generate write addresses for the image memories 111 to 113.
It is equipped with.

In such a configuration, since the operations of series #1 to #3 are completely the same, the operation will be explained here by taking series #l as an example. The image processing unit 121 processes the image data under the control of the CPU 100, returns a write signal based on the permission signal from the image memory 111, and writes the image to the image memory 111 according to the write address generated by the address generation circuit 141. Write data. In this case, the image memory 111 can store only the image data of series #1.

(Problems to be Solved by the Invention) As described above, in the conventional image memory device, an image memory is provided for each series, and image data processed in each series is exclusively stored. For this reason, if the capacity of the image data is larger than the capacity of the image memory prepared for the series, there is a drawback that the image data cannot be stored even if there is surplus image memory for other series.

This invention was made due to the circumstances mentioned above,
SUMMARY OF THE INVENTION An object of the present invention is to provide an image memory device that can arbitrarily divide and store a plurality of image data in one image memory and improve the efficiency of image memory use.

Structure of the Invention; (Means for Solving 'J'S) This invention relates to an image memory device used in an image processing device, etc., and the above object of the invention is to write data to image data of a plurality of image processing units. a plurality of address storage means for storing an access start address for one image memory; a plurality of address generation means for specifying an address of the image memory; a plurality of write control means for controlling writing of image data, and the plurality of image data can be selected by the selection means according to a predetermined priority order and written or read in the image memory in arbitrary divisions. This is achieved by making

(Function) In the present invention, one image memory is provided for a plurality of image processing units, and image data can be stored in an arbitrarily divided state by switching the image memory using a selection means. Therefore, the image memory can be used effectively depending on the image processing situation.

(Embodiment) FIG. 1 shows an embodiment of the present invention for series #1 to #3, which has one image memory 1. series#
1 to #3 have the same configuration, and include image processing units 11 to 3 that process image data of each series, and start address storage circuits (registers) 21 to 23 that store access start addresses for the image memory 1. , address generation circuits 31 to 33 that designate addresses of the image memory 1, and write control circuits 41 to 43 that control writing of image data to the image memory 1. In this example, series #1. #
2. The priority order increases in the order of #3. Each series #1
A selection circuit 2 for selecting a write request or a read request for each series of image data is provided between ~#3 and the image memory 1, and the CPU 3 controls the overall! Ia! It is designed to perform l. Note that before the image data is stored in the image memory 1, the storage start address of each image data is set in advance in each of the start address storage circuits 21-23.

When there is a request to write image data from each of the image processing units 11 to 13, the selection circuit 2 sets the permission signal to “true” unless the image memory 1 is being accessed. -13 enable image data, and address generation circuits 31-33 enable addresses, respectively.

And the permission signal is “false”.

When this happens, writing of 1 byte of data to the image memory 1 is completed. The address generation circuits 31 to 3 are constituted by counters, and by initializing them before starting storage, a preset start address value is loaded. When writing of one byte is completed, this counter is incremented by "+1".

The present invention will be described in detail with reference to the flowchart shown in FIG. 2. Normally, it is in an idle state (step S1), and it is constantly judged whether there is an access request to the image memory 1 (step S2). ). If there is an access request, it is first determined whether the request destination is the highest priority sequence #1 (step S3),
If the request destination is series #1, processing for series #1 is performed (step S4). Also, if the request destination is not series #l,
Next, it is determined whether or not it is an access request for series #2, which has the highest priority (step S5), and if the request destination is series #2, the process is performed (step S6), and the request destination is series #2.
If it is not 2, the process of sequence #3 having the lowest priority is performed (step S7). The processing of the above series #l to #3 is performed by switching the selection circuit 2, for example, the image processing section 1
If there is a write request from the image processing section 122 while the image processing section 21 is accessing the image processing section 21, the selection circuit 2 returns a permission signal to the image processing section 122 after the image processing section 121 has finished writing. Writing of image data to the image memory 1 is performed by the address generation circuit 31 to
33, the writing to the image memory 1 is as shown in FIGS. 3(A) and 3(B).

Although three series of image processing are shown in the above-described embodiment, the number of series can be set arbitrarily, and the priority order thereof can also be set arbitrarily.

Effects of the Invention: As described above, according to the image memory device of the present invention, one image memory is provided for a plurality of image processing sections, and the image memory is arbitrarily divided to store a plurality of image data. Therefore, the efficiency of image memory usage can be improved.

[Brief explanation of the drawing]

Fig. 1 is a block configuration diagram showing an embodiment of the present invention, Fig. 2 is a flowchart showing an example of its operation, and Fig. 3 (^)
, CB) is a diagram showing an example of division of an image memory, and FIG. 4 is a block diagram showing an example of a conventional image memory device. 1.111-113... Image memory, 2... Selection circuit, 3°100... CPU, 11-13,121
-123... Image processing section, 21-23... Start address storage circuit, 31-33, 141-143... Address generation circuit, 41-43, 131-133... Write control circuit. Geizu (,4) CB> 5th

Claims (1)

[Claims] 1. Selection means for selecting a write request or read request for image data of a plurality of image processing units, a plurality of address storage means for storing an access start address for one image memory, and specifying an address of the image memory. A plurality of address generation means and a plurality of write control means for controlling writing of the image data to the image memory are provided, and the plurality of image data are selected by the selection means according to a predetermined priority order to write the image data to the image memory. An image memory device characterized in that the memory can be arbitrarily divided into parts for writing or reading.