JPH0454032A - Multiplex conversion circuit - Google Patents

Abstract

PURPOSE:To improve a fault segmenting function considerably by outputting the result of comparison monitor of an input and output of its won driving circuit in plural multiplex exchange circuits to one common alarm bus as the alarm information of each time slot. CONSTITUTION:A monitoring circuit 106 receives an input signal 21 inherent in a channel leading to a drive circuit 103 and the output of a monitoring circuit 105 and compares and monitors the signals for only a time slot assigned specifically to its own channel. A driving circuit 107 sends a common alarm bus signal 207A to a common alarm bus 207 as the alarm information for only the time slot assigned inherent in to its own channel and the common alarm bus signal 207A is inputted to a monitoring circuit 109 via a monitoring circuit 108. The monitoring circuit 109 uses a monitoring pulse 211 representing each time slot location from a timing generating circuit 102 to monitor the common alarm bus signal 207A and the alarm information of all the time slots.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplex conversion circuit, and more particularly to a multiplex conversion circuit in which a fault monitoring circuit provided in a bus-type multiplex conversion circuit is improved.

[Conventional technology]

The configuration of a conventional bus-based multiplex conversion circuit is shown in the block diagram of FIG. 3, and the time charts 1 to 1 of the signals of each part are shown in FIG. That is, when performing time division multiplexing of n signals, the reference frame position pulses 201 and 202 of the time division multiplexed signal are sent from the multiplexing circuit common section 101.
A time slot pulse 202 indicating the multiplex time slot position is sent to the timing generation circuit 102 of each multiplex conversion circuit 11.12 to 1n. For example, the multiplex conversion circuit 11 (
The timing generation circuit 102 of CHI generates a timing signal 204 to be multiplexed from the timing pulses of the reference frame position pulse 201 and the time slot pulse 202 in accordance with the designated time slot signal 205 of CH1. The drive circuit 103 of the multiplex conversion circuit 11 (CHI) converts the input signal 21 into a time slot indicated by a timing signal 204 and outputs the designated CH only during this time slot.
A signal 204A is sent to drive the common bus 203, and a multiplexed signal is output from the multiplexed signal output 206 via the multiplexing circuit common section 101. Such a multiplexed signal of the common bus 203 and the frame position pulse 201 . Time slot pulse 202. The timing relationship of timing pulses 204 is shown in FIG. This bus-based multiplexing circuit can flexibly respond to changes in the multiplexing circuit, and since the multiplexing operation is performed only by the common bus 203, the circuit configuration is extremely easy.

Among such multiple conversion circuits, failures in the drive circuit 103 will be explained in particular. First, there are two types of failure modes in the drive circuit 103. Incidentally, in the case of a bus type, the drive circuit 103 operates so as to make the output active only during its own time slot and to have high impedance in other sections. Therefore, the two types of failure modes are a gate function failure in which the gate of the drive circuit 103 is made active or high impedance, and an output failure in the active section. When using a bus format, an output failure in its own active section is a failure only between its own time slots and does not affect others.
When a gate function fails, the gate becomes active even in a time slot section other than its own, so the signal of its own CH will be displayed normally, but the signals of other CHs will be disturbed. That is, the alarm information 20 from the own main signal system monitoring circuit 106
9 indicates normal when there is a gate function failure, and an alarm is displayed only when there is an output failure.

In such conventional bus-based multiplex conversion circuits, when a failure occurs in the drive circuit and the time designated time slot signal output 205 other than the time slot assigned to itself becomes active, other multiplex conversion circuits This will affect the output signal and cause serious damage. In the case of an output failure in the drive circuit itself, the failure in the drive circuit could be detected by monitoring the output bus signal 203 and comparing it with an internal signal.

[Problem to be solved by the invention]

However, in the conventional fault detection method of multiplex converter circuits, the outputs of timeslots other than those assigned to it are set to high.
In the case of a gate malfunction in the impedance drive circuit, the self-CH appears to be normally displayed, making it impossible to detect the self-failure and having a large effect on other signals.

As a solution to this problem, we stopped the bus-type multiple conversion circuit and
There are methods such as multiplexing individual signal lines individually using a multiplexing circuit in a common section of the multiplexing circuit, but this increases the number of signal lines,
This method has the disadvantage of not being able to respond flexibly to changes such as an increase in multiplexed channels.

[Means to solve the problem]

The multiplex conversion circuit of the present invention is a bus-type multiplex conversion circuit that supplies multiplex frame pulses and multiplex time slot pulses from a multiplex common circuit to multiplex input signals of a plurality of channels. a first drive circuit that generates a common bus drive signal based on frame pulses and time slot pulses for multiplexing; a first monitor circuit that monitors the common bus signal; and an input of the own channel. a first monitoring circuit for monitoring a fault by comparing the signal and the output signal of the first monitoring circuit only in time slots assigned to its own channel; and a first monitoring circuit configured for fault monitoring based on the output signal of the first monitoring circuit a second drive circuit that drives the common alarm bus, a second monitor circuit that monitors the bus signal of the common alarm bus, and a second monitor circuit that monitors the alarm status in each time slot of the output of the second monitor circuit. and a second monitoring circuit, which compares the output of the first monitoring circuit and the output of the second monitoring circuit, identifies whether the fault is in the own channel or another channel, and outputs a control signal in the case of a fault in the own channel. and a gate circuit that disconnects a drive line from the first drive circuit to the common bus based on the control signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of failure modes and alarm information of this embodiment. In the embodiment shown in FIG. 1, the multiplex conversion circuit 11, which is one of the n multiplex conversion circuits, uses the reference frame position pulse 201 from the multiplex circuit common section 101 and the time slot pulse 202 of each CH of the multiplex signal. A timing signal 204 is generated in the timing generation circuit 102 and controls the drive circuit 103, whereby the input signal 21 is sent to the common bus 203 and multiplexed. This circuit system is the same as the conventional example.

Next, the operation of the fault monitoring system added in this embodiment will be explained. In this embodiment, the drive circuit 10 is connected to the output of the drive circuit 103.
It is connected to the common bus 203 via a gate circuit 104 for isolating it from the common bus 203 in the event of a failure. on the other hand,
The bus signal of the common bus 203 is constantly monitored by the monitor circuit 105. Furthermore, the monitoring circuit 106
A comparison between the CH-specific input signal 21 to the drive circuit 103 and the output of the monitor circuit 105, that is, the bus signal, indicates that the self-C
Comparative monitoring is performed only during time slots uniquely assigned to H. Main signal system alarm information 209, which is the output of the monitoring circuit 106, is transmitted to the drive circuit 107. The drive circuit 107 sends a common alarm bus signal 207A to the common alarm bus 207 as alarm information only during the time slot uniquely assigned to its own CH, and this common alarm bus signal 207A is sent to the monitoring circuit via the monitor circuit 108. 109. The monitoring circuit 109 monitors the aforementioned common alarm bus signal 207A and the alarm information of all time slots using the monitoring pulse 211 from the timing generation circuit 102 indicating the position of each time slot. The fault monitoring control circuit 110 is a self-CH
Alarm information 209 for a unique time slot and alarm information 212 for all other time slots are monitored, and if it is determined that the failure is its own based on the failure mode, a control signal 213 is sent out to activate the gate circuit 104. The signal is controlled and separated from the common bus 203 to prevent damage from spreading to other signals.

Next, the failure mode and failure monitoring operation of the drive circuit 103, which is the object of this embodiment, will be explained with reference to the explanatory diagram of FIG.

In FIG. 2, a plurality of multiplex conversion circuits #1. #i, #
Various combinations occur depending on whether n causes a single failure or double failure, and whether the failure mode of each multiplex conversion circuit is gate function failure or output failure. In order to specifically illustrate the relationship between alarm information corresponding to these failures and alarm information on the common alarm bus, Cases 1 to 5 are assumed as examples of failures. That is, in cases 1 to 3, there is a single failure, and multiple conversion circuit #1. Out of #i, #n, only #1 is normal, or the other #i, #n is due to output failure or gate function failure.
It is assumed that n is normal. Cases 3A and 4.5 are double failures, where #i and #n are combinations of failures as shown in FIG. In case 3A, the output failure of #1 is not visible at first, but becomes visible when the gate circuit 104 is driven by the failure detection of #i and the bus is disconnected from #i. Since case 4 is an individual output failure, the individual failures of #1 and #i can be easily identified. In case 5, it is impossible to isolate which multiplex conversion circuit is at fault, but the probability of double faults due to gate dysfunction mode is low, so it is ignored. In this way, except for case 5, the gate function failure mode can be isolated and determined by combining the failure indication of the common alarm bus and the failure indication of each multiplex conversion circuit, and by disconnecting from the bus.

〔Effect of the invention〕

As explained above, the present invention outputs the comparative monitoring results of the input/output of its own drive circuit in a plurality of multiplex conversion circuits to one common alarm bus as alarm information for each time slot, thereby allowing each multiplex conversion circuit to Alarm information can be recognized by individual multiplex conversion circuits. In particular, even in the case of a gate malfunction, it is possible to detect the failure mode between the own channel and other channels, and to isolate the failure, which can significantly improve the function.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of this embodiment, Fig. 3 is a block diagram of a conventional multiplex conversion circuit, and Fig. 4 is an explanation of the operation of the conventional example. This is a time chart. 11.12~b~2n... Input signal, 101... Multiplexing circuit common part, 102... Timing generation circuit, 103, 107...
...Drive circuit, 104...Gate circuit, 105. j0
8... Monitor circuit, 106.109... Monitor circuit,
110...fault monitoring control circuit.

Claims (1)

[Claims] 1. In a bus-type multiplex conversion circuit that supplies multiplexed frame pulses and multiplexed time slot pulses from a multiplexing common circuit and multiplexes input signals of a plurality of channels, a first drive circuit that generates a common bus drive signal based on frame pulses and time slot pulses for multiplexing; a first monitor circuit that monitors the common bus signal; and an input of the own channel. a first monitoring circuit for monitoring a fault by comparing the signal and the output signal of the first monitoring circuit only in time slots assigned to its own channel; and a first monitoring circuit configured for fault monitoring based on the output signal of the first monitoring circuit a second drive circuit that drives the common alarm bus, a second monitor circuit that monitors the bus signal of the common alarm bus, and a second monitor circuit that monitors the alarm status in each time slot of the output of the second monitor circuit. and a second monitoring circuit, which compares the output of the first monitoring circuit and the output of the second monitoring circuit, identifies whether the fault is in the own channel or another channel, and outputs a control signal in the case of a fault in the own channel. and a gate circuit that disconnects a drive line from the first drive circuit to the common bus based on the control signal. 2. A claim characterized in that even if the failure of the first drive circuit of multiple channels is a simultaneous failure of at least two channels, and one of the failure modes of the two channels is a gate function failure, the failed channel can be identified. The multiple conversion circuit according to item 1.