JPH0472552A - Thin film transistor base and method and device for inspecting it - Google Patents
Thin film transistor base and method and device for inspecting itInfo
- Publication number
- JPH0472552A JPH0472552A JP2183906A JP18390690A JPH0472552A JP H0472552 A JPH0472552 A JP H0472552A JP 2183906 A JP2183906 A JP 2183906A JP 18390690 A JP18390690 A JP 18390690A JP H0472552 A JPH0472552 A JP H0472552A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- short circuit
- short
- signal line
- Prior art date
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- Liquid Crystal (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Investigating Or Analyzing Materials Using Thermal Means (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Liquid Crystal Display Device Control (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は液晶表示装置に用いる薄膜トランジスタアクテ
ィブマトリクス基板並びにその検査方法及びその装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor active matrix substrate used in a liquid crystal display device, and a method and apparatus for testing the same.
第2図に薄膜トランジスタアクティブマトリクス基板(
以後薄膜トランジスタ基板と略す)の電気的配線構成の
一例として、5×5画素配列の場合を示す。薄膜トラン
ジスタ基板は、走査線11〜15、信号線21〜25、
また各交点には薄膜トランジスタ7、透明画素電極8を
ガラス基板上に形成したものである。この薄膜トランジ
スタ基板と共通電極基板を平行に対峙させ1両基板間に
液晶を封入したものが液晶表示装置の基本構成である6
11P〜15p及び21p〜25pは電極端子パッドで
ある。Figure 2 shows a thin film transistor active matrix substrate (
As an example of the electrical wiring configuration of a thin film transistor substrate (hereinafter abbreviated as thin film transistor substrate), a case of a 5×5 pixel arrangement is shown. The thin film transistor substrate includes scanning lines 11 to 15, signal lines 21 to 25,
Further, at each intersection, a thin film transistor 7 and a transparent pixel electrode 8 are formed on a glass substrate. The basic structure of a liquid crystal display device is one in which the thin film transistor substrate and the common electrode substrate face each other in parallel and liquid crystal is sealed between the two substrates6.
11P to 15p and 21p to 25p are electrode terminal pads.
薄膜トランジスタ基板の製造においては、製造工程の塵
埃やホトレジスト欠陥等に起因する走査線と信号線の短
絡欠陥3が発生し易い。短絡3には、第3図(a)に示
すように、走査線と信号線の交差点で発生する短終3a
と、薄膜トランジスタ内で発生する短絡3bがある。こ
れらの欠陥は、走査線13及び信号!23に沿った線状
の表示不良の原因となる。この対策のため、第3図(b
)に示すように、交差部や薄膜トランジスタを複数化す
る方法がある。同図の場合、9a、9dの位置で配線を
切断することにより短絡を修正できる。In manufacturing thin film transistor substrates, short-circuit defects 3 between scanning lines and signal lines are likely to occur due to dust in the manufacturing process, photoresist defects, and the like. The short circuit 3 includes a short termination 3a that occurs at the intersection of the scanning line and the signal line, as shown in FIG. 3(a).
Then, there is a short circuit 3b that occurs within the thin film transistor. These defects are caused by scan line 13 and signal! This causes a linear display defect along the line 23. As a countermeasure for this, Fig. 3 (b)
), there is a method of using multiple intersections and thin film transistors. In the case of the same figure, the short circuit can be corrected by cutting the wiring at positions 9a and 9d.
しかしこの方法を実現するには、短絡の発生位置を特定
する必要がある。However, in order to implement this method, it is necessary to identify the location where the short circuit occurs.
第4図に、一般に短絡検査に用いらている電気的な方法
を示す。この検査では、薄膜トランジスタ基板は、走査
線11〜15が外部配線11cl〜15dと接続配線1
cにより接続され、信号線21〜25も外部配線21d
〜25dと接続配線2Cにより接続さ九ている。そして
探針等を接続配線1c、2cに接触させ、走査線と信号
線の間に電位差Vを印加し、電流計4で電流値を測定す
ることにより、短絡の有無を判別している。しかしこの
方法は短絡の発生している画素番地を特定できないとい
う課題がある。FIG. 4 shows an electrical method generally used for short circuit testing. In this inspection, on the thin film transistor substrate, scanning lines 11 to 15 are connected to external wirings 11cl to 15d and connecting wirings 1 to 15d.
c, and the signal lines 21 to 25 are also connected to the external wiring 21d.
~25d and are connected by connection wiring 2C. Then, the presence or absence of a short circuit is determined by bringing a probe or the like into contact with the connecting wires 1c and 2c, applying a potential difference V between the scanning line and the signal line, and measuring the current value with an ammeter 4. However, this method has a problem in that it is not possible to identify the pixel address where the short circuit has occurred.
この課題を解決するには、第2図に示す配線構造の薄膜
トランジスタ基板を対象とし、1本の走査線と1本の信
号線にだけ電位差Vを与えた状態での電流値の測定を、
全走査線及び全信号線に対し順次行えばよい。しかしこ
の方法は、走査線数と信号線数の積の回数だけ電流値を
測定する必要があり、液晶デイプレイ等の画素数の膨大
な薄膜トランジスタ基板では測定に長時間を要し実用に
適さない。また電圧印加のための探針の接触による電極
端子部lip〜15p、21p〜25pの損傷も問題と
なる。また検査時間を短縮するため、多数本の探針を同
時に接触させる構造にしたとしても、検査を行う走査線
あるいは信号線を電気的に切り替えるため、長時間を要
する。さらに、上述した電気的な検査方法では、第3図
(b)に示すように、走査線と信号線の交差部や薄膜ト
ランジスタを複数化した薄膜トランジスタ基板に対して
は、どの交差部あるいは薄膜トランジスタに短絡欠陥が
存在するのかを特定できない。To solve this problem, we measured the current value with a potential difference V applied to only one scanning line and one signal line using a thin film transistor substrate with the wiring structure shown in Figure 2.
This may be performed sequentially for all scanning lines and all signal lines. However, with this method, it is necessary to measure the current value as many times as the product of the number of scanning lines and the number of signal lines, and it takes a long time to measure on thin film transistor substrates with a huge number of pixels such as LCD displays, making it unsuitable for practical use. . Furthermore, damage to the electrode terminal portions lip~15p and 21p~25p due to contact with the probe for voltage application also poses a problem. Furthermore, even if a structure is adopted in which a large number of probes are brought into contact at the same time in order to shorten the inspection time, it takes a long time to electrically switch the scanning lines or signal lines for inspection. Furthermore, in the electrical inspection method described above, as shown in FIG. It is not possible to determine whether a defect exists.
検査時間を短縮する方法としては、薄膜トランジスタ基
板とエレクトロクロミック表示パネルを組み合わせ、エ
レクトロクロミンク基板の発色膜の発色状態から欠陥を
検出する方法が特開平1−154092号公報に記載さ
れている。この方法によれば、各画素電極の導通状態に
応じてエレクトロクロミック表示基板の発色膜が非発色
あるいは発色状態となるため、欠陥画素を特定すること
が可能となる。ただしこの方法は薄膜トランジスタ基板
の画素電極とエレクトロクロミック表示基板の発色膜と
を電解質を介して導通接続する必要があるため、液体の
電解質を用いた場合には薄膜トランジスタ基板が汚染す
る問題がある。また、電解質に固体を用いた場合でも金
属線との物理的な接触により薄膜トランジスタ基板に損
傷が生じ易く、また導通接続不良による欠陥検査の誤り
が生じ易いなどの課題がある。As a method for shortening inspection time, JP-A-1-154092 describes a method in which a thin film transistor substrate and an electrochromic display panel are combined and defects are detected from the coloring state of a coloring film of the electrochromic substrate. According to this method, the coloring film of the electrochromic display substrate becomes non-colored or colored depending on the conduction state of each pixel electrode, making it possible to identify defective pixels. However, this method requires conductive connection between the pixel electrode of the thin film transistor substrate and the coloring film of the electrochromic display substrate via an electrolyte, so if a liquid electrolyte is used, there is a problem that the thin film transistor substrate will be contaminated. Furthermore, even when a solid electrolyte is used, there are problems in that the thin film transistor substrate is likely to be damaged due to physical contact with metal wires, and errors in defect inspection are likely to occur due to poor conduction connection.
このように、従来技術では薄膜トランジスタ基板の短絡
欠陥を短時間に、かつ基板に損傷を与えないで検出する
ことは不可能であった。また短絡欠陥の存在する画素番
地を特定することができても、各画素に対して走査線と
信号線の交差点や薄膜トランジスタの複数化がなされて
いる場合、どの交差点あるいは薄膜トランジスタに短絡
が存在するかを特定することは不可能であった。As described above, with the prior art, it has been impossible to detect short-circuit defects in thin film transistor substrates in a short time and without damaging the substrate. Even if it is possible to identify the pixel address where the short circuit defect exists, if each pixel has an intersection of a scanning line and a signal line or multiple thin film transistors, it is difficult to determine which intersection or thin film transistor the short circuit exists in. It was impossible to identify.
本発明の目的は薄膜トランジスタ基板の短絡欠陥を、短
時間に、かつ基板への接触を最小限にした薄膜トランジ
スタ基板の検査方法及び装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method and apparatus for inspecting a thin film transistor substrate for short-circuit defects in a thin film transistor substrate in a short time and with minimal contact with the substrate.
また、本発明の他の目的は、走査線と信号線の交差点や
薄膜トランジスタが複数化された薄膜トランジスタ基板
でも、どの交差点あるいは薄膜トランジスタに短絡が発
生しているかを特定できる、薄膜トランジスタ基板の検
査方法及び装置を提供することにある。Another object of the present invention is a method and apparatus for inspecting a thin film transistor substrate, which can identify which intersection of a scanning line and a signal line or a thin film transistor has a short circuit, even in a thin film transistor substrate having a plurality of thin film transistors. Our goal is to provide the following.
また、本発明の他の目的は、短絡欠陥を有する薄膜トラ
ンジスタ基板の配線を自動的に修正できる薄膜トランジ
スタ基板の修正方法及び装置を提供することにある。Another object of the present invention is to provide a method and apparatus for repairing a thin film transistor substrate that can automatically repair wiring on a thin film transistor substrate having a short circuit defect.
また、本発明の他の目的は、短絡欠陥の検査に適した配
線パターンを有する薄膜トランジスタ基板を提供するこ
とにある。Another object of the present invention is to provide a thin film transistor substrate having a wiring pattern suitable for inspecting short circuit defects.
上記目的を達成するために、薄膜トランジスタ基板の走
査線と信号線の、いずれも一方の端子を電気的に接続し
、走査線と信号線の間に直流電圧を印加し、走査線と信
号線の短絡欠陥部を流れる電流による配線の発熱を赤外
画像検出器で検出し、これにより短絡欠陥の発生してい
る可能性のある画素番地を特定するようにした。In order to achieve the above objective, one terminal of both the scanning line and the signal line of the thin film transistor substrate is electrically connected, a DC voltage is applied between the scanning line and the signal line, and the scanning line and the signal line are connected electrically. An infrared image detector detects the heat generated by the wiring due to the current flowing through the short-circuit defect, thereby identifying the pixel address where the short-circuit defect may occur.
さらに短絡欠陥の発生している可能性のある画素番地の
配線パターンの発熱状態を赤外画像検出器で検出し、短
絡欠陥の位置を特定するようにした。Furthermore, an infrared image detector detects the heating state of the wiring pattern at a pixel address where a short-circuit defect may occur, and the position of the short-circuit defect is specified.
さらに短絡欠陥の発生している可能性のある画素番地の
配線パターンの発熱状態に加え、同一位置を検出した可
視画像を参照することにより、短絡欠陥の位置を特定す
るようにした。Furthermore, in addition to the heating state of the wiring pattern at the pixel address where the short-circuit defect may have occurred, the position of the short-circuit defect is specified by referring to a visible image detected at the same position.
さらに上記の方法で検出された短絡欠陥の位置データを
用い、レーザ等による配線修正位置を制御するようにし
た。Furthermore, the position data of short-circuit defects detected by the above method is used to control the position of wiring correction using a laser or the like.
さらに走査線及び信号線の電極端子部の外側に。Furthermore, on the outside of the electrode terminal parts of the scanning line and signal line.
幅の細い配線パターンを形成することにより、短絡の発
生した画素番地の特定を容易に行えるようにした。By forming a narrow wiring pattern, it is possible to easily identify the pixel address where a short circuit has occurred.
C作用〕
正常な薄膜トランジスタ基板は走査線と信号線の間の抵
抗値は数十メガオーム程度であるため、走査線と信号線
の間に数十ボルト程度の電圧を印加してもほとんど電流
は流れない。これに対し、薄膜トランジスタ基板内に走
査線と信号線の短絡欠陥が存在した場合、この短絡欠陥
部分を通して電流が流れ、配線は発熱する。この発熱を
赤外画像検出器で発熱状態を検出することにより、短絡
が発生している走査線及び信号線を検出することができ
、これより短絡の発生している画素番地が特定できる。C effect] In a normal thin film transistor substrate, the resistance value between the scanning line and the signal line is about several tens of megaohms, so even if a voltage of about several tens of volts is applied between the scanning line and the signal line, almost no current flows. do not have. On the other hand, if a short-circuit defect between a scanning line and a signal line exists in the thin film transistor substrate, current flows through the short-circuit defect, and the wiring generates heat. By detecting the heat generation state using an infrared image detector, it is possible to detect the scanning line and signal line where the short circuit has occurred, and from this, the pixel address where the short circuit has occurred can be specified.
また短絡部は正常な配線に比へ抵抗が太きい等の理由で
、赤外光の放射強度が強い。このため上記短絡画素番地
における配線パターンの赤外画像を検出することにより
、赤外光強度分布から短絡位置を特定できる。In addition, because the resistance of short-circuited parts is higher than that of normal wiring, the radiation intensity of infrared light is strong. Therefore, by detecting an infrared image of the wiring pattern at the shorted pixel address, the shorted position can be identified from the infrared light intensity distribution.
また可視画像を用いれば配線パターンを明確に検出でき
る。そこで赤外画像と同一位置の可視画像を検出し、該
可視画像内の配線パターンの位置を参照することで、短
絡位置の特定をさらに容易に実現できる。Furthermore, if a visible image is used, the wiring pattern can be clearly detected. Therefore, by detecting a visible image at the same position as the infrared image and referring to the position of the wiring pattern in the visible image, it is possible to more easily identify the short circuit position.
また上記方法で短絡位置が特定されると、配線を切断す
べき位置を決定できる。これを基にレーザ等により配線
修正照射位置を制御でき、自動的に配線を修正できる。Furthermore, when the short circuit position is identified by the above method, the position where the wiring should be cut can be determined. Based on this, the wiring correction irradiation position can be controlled using a laser or the like, and the wiring can be automatically corrected.
また走査線及び信号線の電極端子部の外側の配線の幅を
細くすることにより、配線抵抗が増加し、該配線からの
発熱量が増加する。これにより該配線の検出を容易に行
える。Further, by narrowing the width of the wiring outside the electrode terminal portions of the scanning line and the signal line, the wiring resistance increases and the amount of heat generated from the wiring increases. This makes it easy to detect the wiring.
以下9本発明の詳細な説明する。第1図に本発明による
薄膜トランジスタ基板の検査方法の手順を示す。本発明
では、薄膜トランジスタ基板の走査線1及び信号線2の
、いずれも一方の端子を電気的に接続した状態で検査を
行う。まず従来の電気的検査方法と同様に導通検査を行
う。次に導通検査で不良と判定された基板を対象に、短
絡が発生している可能性のある画素の番地(短絡画素番
地)を特定する。そして該短絡画素番地の配線パターン
を順次検査し短絡位置を特定した後、配線を修正する。Hereinafter, nine aspects of the present invention will be described in detail. FIG. 1 shows the procedure of a method for testing a thin film transistor substrate according to the present invention. In the present invention, inspection is performed with one terminal of each of the scanning line 1 and the signal line 2 of the thin film transistor substrate electrically connected. First, a continuity test is performed in the same manner as the conventional electrical test method. Next, for the board determined to be defective in the continuity test, the address of a pixel where a short circuit may have occurred (shorted pixel address) is identified. Then, after sequentially inspecting the wiring pattern of the shorted pixel address and specifying the shorted position, the wiring is corrected.
導通検査では、走査線1と信号線2の間に電位差■を与
え、電流計4で電流値を測定する。正常な薄膜トランジ
スタ基板では走査線1と信号線2の間の抵抗値は数十メ
ガオーム程度であるため、数十ボルト程度の電圧を印加
してもほとんど電流は流れない。これに対し、走査線1
と信号線2の間に短絡欠陥3が存在した場合、この短絡
部3を通して電流が流れる。そこで電f7を値が規定値
以上の基板を、短絡の発生した不良基板と判定する。In the continuity test, a potential difference ■ is applied between the scanning line 1 and the signal line 2, and the current value is measured with an ammeter 4. In a normal thin film transistor substrate, the resistance value between the scanning line 1 and the signal line 2 is about several tens of megaohms, so almost no current flows even if a voltage of about several tens of volts is applied. On the other hand, scan line 1
When a short-circuit defect 3 exists between the signal line 2 and the signal line 2, a current flows through this short-circuit portion 3. Therefore, a board whose voltage f7 is equal to or higher than a specified value is determined to be a defective board in which a short circuit has occurred.
短絡画素番地特定では、導通検査と同様に、走査線1と
信号線2の間に電位差■を与え、短絡の発生した走査線
と信号線に流れる電流による配線の発熱を検出し、短絡
画素番地特定する。これには10〜301Lm■程度の
微小領域の発熱部から放射される赤外光の強度に応した
出力が得られる赤外顕微@ 5 mを用い、走査Mlと
信号線2の端子部を破線6に沿って走査し、発熱してい
る配線を検出する。To identify the shorted pixel address, similarly to the continuity test, a potential difference ■ is applied between the scanning line 1 and the signal line 2, heat generation in the wiring due to the current flowing through the shorted scanning line and signal line is detected, and the shorted pixel address is detected. Identify. For this, we used an infrared microscope @ 5 m that can obtain an output corresponding to the intensity of infrared light emitted from a heat generating part in a micro area of about 10 to 301 Lm. 6 and detect the wiring that is generating heat.
第5図は短絡画素番地特定方法の詳細な実施例を示した
ものである。同図において薄膜トランジスタ基板は、走
査線11〜15が電極端子パッド]、 I P〜15P
の外側に形成された外部配線11d〜15dと接続配線
1cにより電気的に接続され、また信号線21〜25は
電極端子パッド21p〜25pの外側に形成された外部
配!21d〜25clと接続配置2cにより電気的に接
続されている。走査1iA11〜15と信号線21〜2
5の間に電位差Vを与えるには、接続配線1c、2cに
電圧印加用の探針を接触させればよい。同図に示すよう
に5短終3が走査!13と信号線23の交差する画素で
発生している場合、電流は外部配線13d−+電極端子
バッド13p→短終3→電極端子パッド23p→外部配
置123dと流れ、この間の配線は発熱する。そこで例
えば外部配線lid〜15dと外部配線21d〜25d
から放射される赤外線を、破線6に沿って赤外顕微鏡で
検出すれば、破線6部の赤外光強度分布波形It、2t
が得られる。これらの波形から赤外光強度の強い位置を
検出することにより、発熱した配線位置、すなわち走査
線13及び信号線23を検出できる。FIG. 5 shows a detailed embodiment of the shorted pixel address identification method. In the same figure, in the thin film transistor substrate, scanning lines 11 to 15 are electrode terminal pads], IP to 15P
The signal lines 21 to 25 are electrically connected to the external wirings 11d to 15d formed on the outside of the electrode terminal pads 21p to 25p by the connection wiring 1c, and the signal lines 21 to 25 are electrically connected to the external wirings 11d to 15d formed on the outside of the electrode terminal pads 21p to 25p. 21d to 25cl and are electrically connected by the connection arrangement 2c. Scan 1iA11-15 and signal lines 21-2
In order to apply a potential difference V between the lines 1c and 2c, a probe for voltage application may be brought into contact with the connection wirings 1c and 2c. As shown in the figure, 5 short ends 3 scan! 13 and the signal line 23, the current flows from the external wiring 13d-+electrode terminal pad 13p→short end 3→electrode terminal pad 23p→external arrangement 123d, and the wiring between them generates heat. Therefore, for example, external wiring lid~15d and external wiring 21d~25d
If the infrared rays emitted from the is detected by an infrared microscope along the broken line 6, the infrared light intensity distribution waveform It, 2t of the broken line 6 is detected.
is obtained. By detecting the positions where the infrared light intensity is strong from these waveforms, the wiring positions where heat is generated, that is, the scanning line 13 and the signal line 23 can be detected.
その結果、短絡画素番地を特定できる。なお本実施例で
は、基板内の短絡がN個ある場合は、検出される走査線
及び信号線はそれぞれ最大N本となり、最大NXN個の
交点を短絡が発生している可能性のある画素番地として
特定できる。As a result, the shorted pixel address can be identified. In this embodiment, if there are N short circuits in the board, the maximum number of scanning lines and signal lines to be detected will be N each, and the maximum of NXN intersections will be assigned to pixel addresses where short circuits may occur. It can be identified as
次に短絡位置特定方法の第1の実施例を説明する。第6
図に示すように、走査線と信号線の交差部及び薄膜トラ
ンジスタ7を複数化した基板では、短絡欠陥は短絡候補
領域73a〜73dで発生する可能性がある。このため
配線を修正するには。Next, a first embodiment of the short circuit position specifying method will be described. 6th
As shown in the figure, in a substrate having a plurality of intersections between scanning lines and signal lines and a plurality of thin film transistors 7, short circuit defects may occur in short circuit candidate regions 73a to 73d. To fix the wiring for this.
どの短絡候補領域で短絡が発生しているかを特定(短絡
位置特定)する必要がある。一般に、短絡部は正常な配
線に比べ抵抗が大きい等の理由で、赤外光の放射強度が
強い。そこで本実施例では、第1図に示すように、短絡
画素番地の配線パターンを赤外顕微鏡5mの視野内に順
次位置決めし、赤外画像を検出する。そして該赤外画像
の強度が一定値以上の場合には、その画素番地に短絡に
よる発熱が存在すると判断し、赤外画像内での短絡位置
を検出する。短絡位置は、例えば赤外光強度が最大とな
る位置として検出すればよい。このようにして求めた赤
外画像中の短絡位置座標の他、回路パターン設計データ
及び基板の位置決め座標データを用い、短終3が発生し
ている短絡候補領域を決定すればよい。これにより第6
図に示す短終3は、短絡候補領域73cに存在すること
が分かり、配線切断位置を90に決定できる。なお赤外
画像の強度が一定値未満の場合は、その短絡画素番地に
は短絡がないと判断し、短絡位置特定は行わない。It is necessary to specify in which short circuit candidate region a short circuit has occurred (short circuit position specification). In general, short-circuited parts have a higher resistance than normal wiring, and therefore emit infrared light at a higher intensity. Therefore, in this embodiment, as shown in FIG. 1, the wiring patterns of the shorted pixel addresses are sequentially positioned within the field of view of the infrared microscope 5m, and an infrared image is detected. If the intensity of the infrared image is above a certain value, it is determined that heat due to a short circuit exists at that pixel address, and the position of the short circuit in the infrared image is detected. The short circuit position may be detected, for example, as the position where the infrared light intensity is maximum. In addition to the short circuit position coordinates in the infrared image obtained in this manner, circuit pattern design data and board positioning coordinate data may be used to determine the short circuit candidate region where the short termination 3 has occurred. As a result, the 6th
It is found that the short end 3 shown in the figure exists in the short circuit candidate region 73c, and the wiring cutting position can be determined as 90. Note that if the intensity of the infrared image is less than a certain value, it is determined that there is no short circuit at that short pixel address, and the short circuit position is not specified.
次に短絡位置特定方法の第2の実施例を第7図により説
明する。第1の実施例では、赤外画像のみを用い短絡位
置を特定したが、本実施例では、赤外画像と同一位置を
検出する可視画像を参照し短絡位置を特定する。第7図
(b)は、透過照明を行い、第6図に示す配線パターン
を検出した可視画像である。透過照明は基板背面から照
明するため、同図のごとく金属の配線パターンをシルエ
ツト像として検出できる。まず同図(a)に示すような
特徴的なパターンを辞書パターン63として登録する。Next, a second embodiment of the short circuit position specifying method will be described with reference to FIG. In the first embodiment, only the infrared image was used to identify the short circuit position, but in this embodiment, the short circuit position is identified by referring to a visible image that detects the same position as the infrared image. FIG. 7(b) is a visible image obtained by performing transillumination and detecting the wiring pattern shown in FIG. 6. Since transmitted illumination illuminates from the back of the board, the metal wiring pattern can be detected as a silhouette image, as shown in the figure. First, a characteristic pattern as shown in FIG. 6(a) is registered as a dictionary pattern 63.
この際、辞書パターン63の位置77を原点とし、短絡
候補位置(短絡候補領域の代表位[)74a 〜74c
l及び切断位置98〜9dの座標を設定する。これによ
り辞書パターン位置77が分かれば、短絡候補位置74
a〜74d及び切断位1i9a〜9dを決定できる。短
絡位置特定では短絡欠陥画素番地の配線パターンを順次
検査するが、可視画像中の辞書パターン位置77は基板
の位置決め状態に応じ変化する。そこで検査ごとに透過
照明で可視画像を検出し、パターンマツチングにより、
その画像中で辞書パターン63が最も一致する位置の座
標77を求める。これにより可視画像中の短絡候補位置
74a〜74d及び切断位置9a〜9dの座標を算出で
きる。一方、短絡3の位置は赤外画像から求める。本実
施例では可視画像と赤外画像は同一位置を検出している
ため、可視画像と赤外画像の座標は等しい。そこで可視
画像から求めた短絡候補位置74a〜74dの中で、赤
外画像中の短絡3の位置までの距離が最小になる短絡候
補位置を、短絡が発生している位置として決定できる。At this time, the position 77 of the dictionary pattern 63 is set as the origin, and the short circuit candidate positions (representative positions of the short circuit candidate area [) 74a to 74c
1 and the coordinates of the cutting positions 98 to 9d. If the dictionary pattern position 77 is determined by this, the short circuit candidate position 74
a to 74d and cutting positions 1i9a to 9d can be determined. In short-circuit position identification, the wiring patterns at short-circuit defective pixel addresses are sequentially inspected, but the dictionary pattern position 77 in the visible image changes depending on the positioning state of the board. Therefore, for each inspection, visible images are detected using transmitted illumination, and through pattern matching,
The coordinates 77 of the position where the dictionary pattern 63 most closely matches in the image are determined. Thereby, the coordinates of the short circuit candidate positions 74a to 74d and the cutting positions 9a to 9d in the visible image can be calculated. On the other hand, the position of the short circuit 3 is determined from the infrared image. In this embodiment, the visible image and the infrared image detect the same position, so the coordinates of the visible image and the infrared image are the same. Therefore, among the short circuit candidate positions 74a to 74d determined from the visible image, the short circuit candidate position where the distance to the position of the short circuit 3 in the infrared image is the minimum can be determined as the position where the short circuit has occurred.
これにより第1の実施例と同様に、第6図に示す短絡3
は、短絡候補領域73cに存在することが分かり、配線
切断位置を9cに決定できる。本実施例では予め記憶す
べき座標データが、辞書パターン63の位1177を原
点としたときの、短絡候補位置74a〜7.4 d及び
切断位置9a〜9dだけであり、短絡位置の特定をさら
に容易に実現できる。As a result, similar to the first embodiment, the short circuit 3 shown in FIG.
is found to exist in the short circuit candidate region 73c, and the wiring cutting position can be determined to be 9c. In this embodiment, the coordinate data to be stored in advance is only the short circuit candidate positions 74a to 7.4 d and the cutting positions 9a to 9d when the origin is the digit 1177 of the dictionary pattern 63. It can be easily achieved.
以上述へた短絡位置特定方法により、配線切断位置は決
定される。そこで配線修正では、レーザ43等の配線修
正法により、該配線切断位置を切断することにより、短
絡の発生した基板を修正する。The wiring cutting position is determined by the short circuit position specifying method described above. Therefore, in the wiring correction, the board where the short circuit has occurred is corrected by cutting the wiring at the wiring cutting position using a wiring correction method using a laser 43 or the like.
次に薄膜トランジスタ基板検査装置の第1の実施例を第
8図〜第10図で説明する。本装置は機構系、導通検査
系、光学系からなる。機構系はθステージ31.2ステ
ージ32、Yステージ33、Xステージ34からなり、
薄膜トランジスタ基板30を載置し、基板30の任意の
位置を光学系視野内に位置決めする。導通検査系は直流
電源35゜電流計4、探針36a、36bからなり、探
針36a、36bを配線パターンに接触させて走査線と
信号線の間に電位差を与え、電流値から短絡欠陥の有無
を判別する。光学系は赤外画像検出系、配線切断のため
のレーザ光照射系、明視野照明系、透過照明系、可視画
像検出系からなる。赤外画像検出系は対物レンズ37、
ダイクロイックミラー38、レンズ39、赤外画像検出
器5からなり、薄膜トランジスタ基板3o上の発熱部か
ら放射される赤外光(波長域λ、:約5〜13μm)を
検出する0本赤外画像検出系は対物レンズ37で赤外像
を拡大しているため、10〜30μm[相]程度の微小
領域から放射される赤外光の強度を検出できる。レーザ
光照射系は、レーザ43、ビームエキスパンダ42、図
示しない移動機構を持つ開口部41、ダイクロイックミ
ラー40からなり、開口部41を透過したレーザ光を対
物レンズ37で縮小し、薄膜トランジスタ基板30上に
投影することにより、配線を切断する。明視野照明系は
ランプ46、レンズ45、ハーフミラ−44からなり、
対物レンズ37を介し、薄膜トランジスタ基板30を上
方から照明する。透過照明系はランプ50、レンズ49
からなり、薄膜トランジスタ基板30の背面側から照明
する。可視画像検出系は、可視画像検出器48、レンズ
47からなる。なお可視画像検出器48は赤外画像検出
器5と同一位置の可視像を検出するように調整されてい
る。本実施例において対物レンズ37は、可視域から赤
外域までの光を透過する必要があり、硝子材シこはZn
S等を用いれば良い。ダイクロインクミラー38は、赤
外画像検出器5の検出波長域λ、の光は反射し、検出波
長域λ、より波長の短い光は透過する特性の光学素子で
ある。またダイクロイックミラー40は、レーザ43の
波長λ2(λ2〈λ□)は反射し、可視光(波長域λ3
:λ3くλ2)は透過するする特性を有する。本実施例
は、前述の導通検査、短絡画素番地特定、短絡位置特定
、配線修正を1台の検査装置で実現するものである。Next, a first embodiment of the thin film transistor substrate inspection apparatus will be described with reference to FIGS. 8 to 10. This device consists of a mechanical system, a continuity test system, and an optical system. The mechanical system consists of a θ stage 31.2 stage 32, Y stage 33, and X stage 34.
A thin film transistor substrate 30 is placed, and an arbitrary position of the substrate 30 is positioned within the field of view of the optical system. The continuity test system consists of a 35° DC power supply, an ammeter 4, and probes 36a and 36b.The probes 36a and 36b are brought into contact with the wiring pattern to apply a potential difference between the scanning line and the signal line, and the current value is used to detect short-circuit defects. Determine presence/absence. The optical system consists of an infrared image detection system, a laser beam irradiation system for wiring cutting, a bright field illumination system, a transmitted illumination system, and a visible image detection system. The infrared image detection system includes an objective lens 37,
A zero-line infrared image detection system consisting of a dichroic mirror 38, a lens 39, and an infrared image detector 5, which detects infrared light (wavelength range λ, approximately 5 to 13 μm) emitted from the heat generating part on the thin film transistor substrate 3o. Since the system magnifies the infrared image with the objective lens 37, it is possible to detect the intensity of the infrared light emitted from a micro region of about 10 to 30 μm [phase]. The laser beam irradiation system includes a laser 43, a beam expander 42, an aperture 41 with a moving mechanism (not shown), and a dichroic mirror 40. Cut the wiring by projecting it onto the screen. The bright field illumination system consists of a lamp 46, a lens 45, and a half mirror 44.
The thin film transistor substrate 30 is illuminated from above through the objective lens 37. The transmitted illumination system includes a lamp 50 and a lens 49.
The light is illuminated from the back side of the thin film transistor substrate 30. The visible image detection system includes a visible image detector 48 and a lens 47. Note that the visible image detector 48 is adjusted to detect a visible image at the same position as the infrared image detector 5. In this embodiment, the objective lens 37 needs to transmit light from the visible range to the infrared range, and the glass material is Zn.
S etc. may be used. The dichroic ink mirror 38 is an optical element that reflects light in the detection wavelength range λ of the infrared image detector 5 and transmits light in the detection wavelength range λ and shorter wavelengths. Furthermore, the dichroic mirror 40 reflects the wavelength λ2 (λ2<λ□) of the laser 43, and reflects the visible light (wavelength range λ3).
:λ3×λ2) has the characteristic of being transparent. In this embodiment, the above-described continuity test, shorted pixel address identification, shorted position identification, and wiring correction are realized by one testing device.
次に短絡画素番地特定における赤外光強度分布波形検圧
方法の実施例を第9図で説明する。薄膜トランジスタ基
板3oはモータ51、送りねじ52により廓動されるX
ステージ34上に載置される。なおXステージ34の位
置は、位置検出器53で検出され、基板3oから放射さ
れる赤外光は、対物レンズ37を介し、赤外画像検出器
5で検出される。以上の構成において、画像検出時に赤
外画像検出器5の出力信号を位置検出器53の信号を基
準にサンプルホールド回路55でサンプルホールドし、
A/D変換器56でA/D変換しメモリ57に記憶する
。Y方向も同様に検出することにより、第5図に示す赤
外光強度分布波形It。Next, an embodiment of a method for detecting an infrared light intensity distribution waveform in identifying a shorted pixel address will be described with reference to FIG. The thin film transistor substrate 3o is rotated by a motor 51 and a feed screw 52.
It is placed on the stage 34. Note that the position of the X stage 34 is detected by the position detector 53, and the infrared light emitted from the substrate 3o is detected by the infrared image detector 5 via the objective lens 37. In the above configuration, when detecting an image, the output signal of the infrared image detector 5 is sampled and held in the sample and hold circuit 55 based on the signal of the position detector 53,
The A/D converter 56 performs A/D conversion and stores it in the memory 57. By similarly detecting the Y direction, the infrared light intensity distribution waveform It shown in FIG. 5 is obtained.
2tが得られる。2t is obtained.
次に短絡画素特定及び配線修正を自動で行うための回路
構成の実施例を第10図に示す。可視画像検出器48で
検出した画像は画像メモリ60に記憶される。そして2
値化回路61で2値化後、パターンマツチング回路62
で辞書パターン63とパターンマツチングを行い、第7
図に示した検出画像中の辞書パターン位置77を求める
。この位置データと、予め設定した短絡候補位置及び配
線切断位置の座襟データ65を、短絡候補位置算出回路
64に入力し短絡候補位置及び配線切断位置を算出する
。一方、赤外画像検出器5で検出した画像はメモリ66
に記憶後、まず発熱有無判定回路67で発熱の有無を判
定する。すなわち赤外画像の強度が一定値未満の場合に
は、短絡がない画素番地であると判定し、短絡位置特定
は行わない。赤外画像の強度が一定値以上の場合には、
短絡があると判断し、発熱位置検出回路68で画像中で
赤外光強度が最大となる位置を発熱位置として検出する
。短絡位置決定回路69では1発熱位置検出回路68で
求めた発熱位置に最も近い短絡候補位置を真の短絡位置
と決定する。これにより配線切断位置も求まる。これを
基に開口部位置算出回路70でレーザ照射系の開口部4
1の位置を算出する。さらに開口部コントローラ71で
開口部移動機構72を駆動し、開口部41を位置決めす
る。以後ビームエキスパンダ42を介し、レーザを照射
することにより、自動的に配線を切断し、短絡を修正で
きる。以上の実施例は、短絡位置特定のために可視画像
を参照する場合について述べたが、赤外画像のみを用い
る場合には、短絡候補位置算出回路64の出力の替わり
に、回路パターン設計データ及び基板の位置決め座標デ
ータから求めた短絡候補位置を短絡位置決定回路69に
入力すればよい。Next, FIG. 10 shows an embodiment of a circuit configuration for automatically identifying short-circuited pixels and correcting wiring. The image detected by the visible image detector 48 is stored in an image memory 60. And 2
After binarization in the digitization circuit 61, the pattern matching circuit 62
Perform pattern matching with the dictionary pattern 63 in
The dictionary pattern position 77 in the detected image shown in the figure is determined. This position data and the seat collar data 65 of the short-circuit candidate position and the wire cutting position set in advance are input to the short-circuit candidate position calculation circuit 64, and the short-circuit candidate position and the wire cutting position are calculated. On the other hand, the image detected by the infrared image detector 5 is stored in the memory 66.
After storing the information, first, the presence or absence of heat generation is determined by the heat generation presence/absence determination circuit 67. In other words, if the intensity of the infrared image is less than a certain value, it is determined that the pixel address has no short circuit, and the short circuit position is not specified. If the intensity of the infrared image is above a certain value,
It is determined that there is a short circuit, and the heat generating position detection circuit 68 detects the position where the infrared light intensity is maximum in the image as the heat generating position. The short circuit position determination circuit 69 determines the short circuit candidate position closest to the heat generation position determined by the one heat generation position detection circuit 68 as the true short circuit position. This also determines the wiring cutting position. Based on this, the aperture position calculation circuit 70 determines the aperture 4 of the laser irradiation system.
Calculate the position of 1. Further, the opening controller 71 drives the opening moving mechanism 72 to position the opening 41. Thereafter, by irradiating a laser through the beam expander 42, the wiring can be automatically cut and the short circuit can be corrected. In the above embodiments, a case has been described in which a visible image is referred to for identifying a short circuit position. However, when only an infrared image is used, circuit pattern design data and The short circuit candidate position determined from the board positioning coordinate data may be input to the short circuit position determining circuit 69.
なお以上の説明では透過照明での可視画像を配線パター
ンの位置検出に用いたが、これは明視野照明の可視画像
を用いても差し支えない。ただし安定に配線パターンの
2値画像が得られない場合には、濃淡画像を用いたパタ
ーンマツチングを行う必要があるであろう。またパター
ンマツチング以外の方法、例えば投影等の手法を用いて
特定の配線位置を求めてもよい・
第11図は薄膜トランジスタ基板検査装置の第2の実施
例を示す。本実施例では、可視光およびレーザ光用の対
物レンズ83と赤外光用の対物レンズ82を独立に設け
たものである。例えば可視光およびレーザ光用の対物レ
ンズ83を中央部に配置し、ドーナツ状の赤外光用の対
物レンズ82を対物レンズ83と同軸に設置したもので
あり、第1の実施例と同様な機能が得られる。なお84
は中央部に穴の空いたミラーであり、可視光及びレーザ
光は中央部を通過し、赤外光のみ反射する光学素子であ
る。Note that in the above description, a visible image under transmitted illumination is used to detect the position of the wiring pattern, but a visible image under bright field illumination may also be used. However, if a binary image of the wiring pattern cannot be stably obtained, it may be necessary to perform pattern matching using a grayscale image. Further, a method other than pattern matching, such as projection, may be used to determine the specific wiring position. FIG. 11 shows a second embodiment of the thin film transistor substrate inspection apparatus. In this embodiment, an objective lens 83 for visible light and laser light and an objective lens 82 for infrared light are provided independently. For example, an objective lens 83 for visible light and laser light is placed in the center, and a donut-shaped objective lens 82 for infrared light is placed coaxially with the objective lens 83, similar to the first embodiment. Functionality is obtained. In addition, 84
is a mirror with a hole in the center, and is an optical element that allows visible light and laser light to pass through the center and reflects only infrared light.
以上述べた薄膜トランジスタ基板検査装置の実施例では
、短絡欠陥の検査と配線の修正を一つの装置で行う場合
について示した。しかし本発明による短絡欠陥検査と配
線修正を、別々の装置で個々に実施してもよいことは言
うまでもない。In the embodiments of the thin film transistor substrate inspection apparatus described above, a case has been described in which short circuit defect inspection and wiring correction are performed using one apparatus. However, it goes without saying that the short circuit defect inspection and wiring correction according to the present invention may be performed individually using separate devices.
次に短絡画素番地特定に適した外部配線パターンの第1
の実施例を第12図に示す。配線の発熱量をW、配線抵
抗をR1配線に流れる電流値を■、配線材料の体積抵抗
率をρ〔Ω・m〕、配IIA長をg、配線幅をX、配線
厚さをtとするとW=I”R・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・■R=ρ
・Q/(x−t) ・・・・・・・・・・・・ ■と表
せる。つまり配線幅あるいは配線厚さを小さくすること
により、単位長さ当りの配線からの発熱量は増加、すな
わち配線から放射される赤外光強度が増加し、発熱した
配線の検知が容易になる。Next, the first external wiring pattern suitable for identifying the shorted pixel address.
An example of this is shown in FIG. The amount of heat generated by the wiring is W, the wiring resistance is R1, the current value flowing through the wiring is ■, the volume resistivity of the wiring material is ρ [Ω・m], the wiring IIA length is g, the wiring width is X, and the wiring thickness is t. Then W=I”R・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・■R=ρ
・Q/(x-t) ・・・・・・・・・・・・■ In other words, by reducing the wiring width or wiring thickness, the amount of heat generated from the wiring per unit length increases, that is, the intensity of infrared light emitted from the wiring increases, making it easier to detect the heating wiring.
第12図の実施例は、外部配線23cl、24dの配線
幅を、薄膜トランジスタ基板の配線パターンの最小露光
!Ill!相当に細くしたものである。なお外部配線は
、画素を駆動するためのICが接続される電極端子パッ
ド23p、24pの外側にあるため5画素の動作特性に
は影響しない。また電極端子パッドのように駆動用IC
との接触抵抗を低くするため、ある程度の幅を確保する
必要もない。In the embodiment shown in FIG. 12, the wiring widths of the external wirings 23cl and 24d are set to the minimum exposure of the wiring pattern of the thin film transistor substrate. Ill! It is quite thin. Note that the external wiring does not affect the operating characteristics of the five pixels because it is located outside the electrode terminal pads 23p and 24p to which ICs for driving the pixels are connected. Also, like the electrode terminal pad, the drive IC
There is no need to secure a certain width in order to reduce the contact resistance with the
このため上述のような形状の外部配線パターンを薄膜ト
ランジスタ基板に作り込むことは実現可能である。Therefore, it is possible to form an external wiring pattern having the above-described shape into a thin film transistor substrate.
第13図は外部配線パターンの第2の実施例である6第
7図の実施例との違いは、外部配線パターン23cl、
24d及びガラス基板81上に、薄膜トランジスタ基板
製造工程で使用するSiN等の絶縁膜80を被覆した点
にある。物体から放射される赤外光の強度は、同じ温度
の物体でも材料や表面状態により異なるが、本実施例に
よれば絶縁膜80の表面から放射される赤外光の強度を
検出することになり、赤外光強度分布は温度分布にほぼ
対応し、発熱した配線位置を検出するための処理を簡素
化できる。FIG. 13 shows a second embodiment of the external wiring pattern.6 The differences from the embodiment shown in FIG. 7 are the external wiring pattern 23cl,
24d and the glass substrate 81 are coated with an insulating film 80 such as SiN used in the thin film transistor substrate manufacturing process. The intensity of infrared light emitted from an object varies depending on the material and surface condition even if the object has the same temperature, but according to this embodiment, the intensity of infrared light emitted from the surface of the insulating film 80 can be detected. Therefore, the infrared light intensity distribution almost corresponds to the temperature distribution, and the process for detecting the position of the wiring that generates heat can be simplified.
以上述へたように本発明によれば薄膜トランジスタ基板
の配線の短絡不良を迅速に検知できるため、きわめて短
時間に薄膜トランジスタ基板の欠陥検査を行うことがで
きる6また。欠陥検査のための探針による接触回数は極
めて少なく、検査工程での基板損傷事故を低減できる6
また1本発明によれば、液晶デイスプレィの各画素に対
し複数の薄膜トランジスタ或いは複数の走査線と信号線
の交差部が形成された基板に対しても、従来不可能であ
った短絡位置の特定を行うことができ、短絡欠陥の存在
する基板を修正することが可能になる。このように本発
明によって、薄膜トランジスタ基板の検査を極めて短時
間に行うことができ、薄膜トランジスタ基板の歩留り向
上に効果を発揮するとともに、製品の原価低減に顕著な
効果がある。As described above, according to the present invention, short-circuit defects in the wiring of a thin film transistor substrate can be quickly detected, so that defects in the thin film transistor substrate can be inspected in an extremely short period of time.6. The number of contacts made by the probe for defect inspection is extremely small, reducing accidents that damage the board during the inspection process6.
Furthermore, according to the present invention, it is possible to identify the short circuit position, which was previously impossible, even for a substrate in which a plurality of thin film transistors or a plurality of intersections of scanning lines and signal lines are formed for each pixel of a liquid crystal display. This makes it possible to repair a board with short-circuit defects. As described above, according to the present invention, thin film transistor substrates can be inspected in an extremely short period of time, which is effective in improving the yield of thin film transistor substrates, and has a significant effect in reducing product costs.
第1図は本発明による薄膜トランジスタ基板検査方法の
実施例の説明図、第2図は薄膜トランジスタ基板の電気
的配線構成の一例を示す図、第3図は短絡欠陥の種類及
び短絡欠陥対策のための配線構造の一例を示す図、第4
図は従来の電気的な短絡欠陥検査方法の説明図、第5図
は短絡画素番地特定法の説明図、第6図は短絡位置特定
法の説明図、第7図は透過照明画像を用いた短絡位置特
定法の説明図、第8図は薄膜トランジスタ基板検査装置
の第1の実施例を示す図、第9図は短絡画素番地特定の
ための画像検出方法の説明図、第10図は回路構成の機
能ブロック図、第11図は薄膜トランジスタ基板検査装
置の第2の実施例を示す図、第12図及び第13図は各
々短絡画素番地特定に適した外部配線パターンの実施例
を示した図である。
1.11〜15・・走査線
2.21〜25・信号線
3.3a〜3d・・・短絡欠陥 4・・電流計5・・・
赤外画像検出器、 5m・・赤外顕微鏡6・・・赤
外光強度検出位置、
7.70〜7d・・薄膜トランジスタ
8・・・透明画素電極、 98〜9d・・配線切断位置
11p〜15p・・走査線電極端子パッド21p〜25
p・信号線電極端子パッドlc、2c・・・接続配線
lid〜15d、21d〜25d・・・外部配線it、
2t・・・赤外光強度分布波形
30・・・薄膜トランジスタ基板、31・θステージ3
2・・・Xステージ、 32・・・Yステー
ジ34・・・Xステージ、 35・・直流電
源36a、36b・・探針、 37・・対物レン
ズ38.40・・ダイクロインクミラー
39.45,47.49・・・レンズ、41・・開口部
42・ ビームエキスパンダ、 43・・・レーザ4
4・ハーフミラ−146及び5o・・・ランプ48・・
・可視画像検出器、 51・・モータ52・・・
送りねじ、 53・・位置検出器55・・・
サンプルホールド回路
56・・A/D変換器、 57・・メモリ63
・辞書パターン
73a〜73d・・・短絡候補領域
74a〜74cl・・・短終候補位置
75・等赤外光強度線
76・赤外光強度分布波形
77・・・辞書パターン位置、 80・絶縁膜81・
・ガラス基板
82・・赤外光用のの対物レンズ
83・・可視光とレーザ光用の対物レンズ84・−・中
央部に穴の空いたミラーFIG. 1 is an explanatory diagram of an embodiment of the thin film transistor substrate inspection method according to the present invention, FIG. 2 is a diagram showing an example of the electrical wiring configuration of a thin film transistor substrate, and FIG. 3 is a diagram showing the types of short circuit defects and measures for short circuit defects. Diagram 4 showing an example of wiring structure
The figure is an explanatory diagram of the conventional electrical short circuit defect inspection method, Figure 5 is an explanatory diagram of the short circuit pixel address identification method, Figure 6 is an explanatory diagram of the short circuit position identification method, and Figure 7 is an illustration of the method using transmitted illumination images. An explanatory diagram of the short circuit position identification method, Fig. 8 is a diagram showing the first embodiment of the thin film transistor substrate inspection apparatus, Fig. 9 is an explanatory diagram of the image detection method for identifying the short circuit pixel address, and Fig. 10 is the circuit configuration. 11 is a diagram showing a second embodiment of the thin film transistor substrate inspection apparatus, and FIGS. 12 and 13 are diagrams each showing an embodiment of an external wiring pattern suitable for identifying shorted pixel addresses. be. 1.11~15...Scanning line 2.21~25/Signal line 3.3a~3d...Short circuit defect 4...Ammeter 5...
Infrared image detector, 5m...Infrared microscope 6...Infrared light intensity detection position, 7.70~7d...Thin film transistor 8...Transparent pixel electrode, 98~9d...Wiring cutting position 11p~15p ...Scanning line electrode terminal pads 21p to 25
p/signal line electrode terminal pad lc, 2c...connection wiring lid~15d, 21d~25d...external wiring it,
2t...Infrared light intensity distribution waveform 30...Thin film transistor substrate, 31・θ stage 3
2...X stage, 32...Y stage 34...X stage, 35...DC power supply 36a, 36b...probe, 37...objective lens 38.40...dichroic ink mirror 39.45, 47.49...Lens, 41...Aperture 42/Beam expander, 43...Laser 4
4. Half mirror 146 and 5o... lamp 48...
・Visible image detector, 51...Motor 52...
Feed screw, 53...Position detector 55...
Sample hold circuit 56...A/D converter, 57...Memory 63
- Dictionary patterns 73a to 73d...Short circuit candidate areas 74a to 74cl...Short end candidate position 75 - Equal infrared light intensity line 76 - Infrared light intensity distribution waveform 77...Dictionary pattern position, 80 - Insulating film 81・
- Glass substrate 82 - Objective lens 83 for infrared light - Objective lens 84 for visible light and laser light - Mirror with a hole in the center
Claims (1)
線と信号線を、いずれも一方の端子で電気的に接続し、
走査線と信号線の間に電位差を与え、走査線と信号線の
短絡欠陥部を流れる電流による走査線、信号線及び短絡
部の発熱状態を赤外画像検出器で検出することを特徴と
する薄膜トランジスタ基板の検査方法。 2、走査線を電気的に接続する端子と画素領域との間に
存在する走査線及び、信号線を電気的に接続する端子と
画素領域との間に存在する信号線の発熱状態を赤外画像
検出器で検出することにより、短絡欠陥が発生している
可能性のある画素番地の特定することを特徴とする請求
項1記載の薄膜トランジスタ基板の検査方法。 3、短絡欠陥が発生している可能性のある画素番地の赤
外画像の強度が基準値より大きい場合には、該画素番地
に短絡欠陥が存在すると判断し、赤外光強度分布から短
絡位置が発生している位置を特定することを特徴とする
請求項1記載の薄膜トランジスタ基板の検査方法。 4、薄膜トランジスタアクティブマトリクス基板の配線
パターンの可視像を参照し、短絡欠陥が発生している位
置を特定することを特徴とする請求項3記載の薄膜トラ
ンジスタ基板の検査方法。 5、薄膜トランジスタアクティブマトリクス基板の走査
線と信号線を、いずれも一方の端子で電気的に接続し、
走査線と信号線の間に電位差を与え、走査線と信号線の
短絡欠陥部を流れる電流による走査線、信号線及び短絡
部の発熱状態を赤外画像検出器で検出し、短絡欠陥が発
生している可能性のある画素番地の赤外画像の強度が基
準値より大きい場合には、該画素番地に短絡欠陥が存在
すると判断し、赤外光強度分布から短絡位置が発生して
いる位置を特定し、該特定した短絡欠陥位置データを用
いてレーザ等による配線修正位置を制御することを特徴
とする薄膜トランジスタ基板の修正方法。 6、薄膜トランジスタアクティブマトリクス基板の走査
線と信号線の間に電位差を与える電圧印加手段と、赤外
画像を検出する手段と、該赤外画像から発熱位置を検出
する手段を有し、該赤外画像から走査線、信号線の発熱
状態から短絡欠陥が発生している可能性のある画素番地
を特定することを特徴とする薄膜トランジスタ基板の検
査装置。 7、薄膜トランジスタアクティブマトリクス基板の走査
線と信号線の間に電位差を与える電圧印加手段と、赤外
画像を検出する手段と、該赤外画像から発熱位置を検出
する手段を有し、該赤外画像から短絡位置を特定するこ
とを特徴とする薄膜トランジスタ基板の検査装置。 8、該赤外画像と同一位置の可視画像を検出する手段を
有し、該可視画像中の配線パターン位置を参照し、短絡
欠陥が発生している位置を特定することを特徴とする請
求項7記載の薄膜トランジスタ基板の検査装置。 9、薄膜トランジスタアクティブマトリクス基板の走査
線と信号線の間に電位差を与える電圧印加手段と、赤外
画像を検出する手段と、該赤外画像から発熱位置を検出
する手段と、該赤外画像から短絡位置を特定し、該特定
した短絡欠陥位置データを用いてレーザによる配線修正
位置を制御する制御手段とを備えたことを特徴とする薄
膜トランジスタ基板の修正装置。 10、薄膜トランジスタアクティブマトリクス基板であ
って、基板周辺に形成された走査線と信号線の電極端子
パッドの外側に、該基板の配線パターンの最小露光線幅
相当に配線幅を細くした金属配線パターンを形成したこ
とを特徴とする薄膜トランジスタ基板。 11、配線幅を細くした金属配線パターン上に絶縁膜を
被覆したことを特徴とする請求項10記載の薄膜トラン
ジスタ基板。[Claims] 1. A scanning line and a signal line of a thin film transistor active matrix substrate are both electrically connected by one terminal,
A potential difference is applied between the scanning line and the signal line, and an infrared image detector detects the heating state of the scanning line, the signal line, and the shorted part due to the current flowing through the shorted defective part of the scanning line and the signal line. Inspection method for thin film transistor substrates. 2. The heating state of the scanning line that exists between the terminal that electrically connects the scanning line and the pixel area and the signal line that exists between the terminal that electrically connects the signal line and the pixel area is detected using infrared light. 2. The method for inspecting a thin film transistor substrate according to claim 1, further comprising identifying a pixel address where a short circuit defect may occur by detecting it with an image detector. 3. If the intensity of the infrared image of a pixel address where a short-circuit defect may occur is greater than the reference value, it is determined that a short-circuit defect exists at that pixel address, and the short-circuit position is determined from the infrared light intensity distribution. 2. The method for inspecting a thin film transistor substrate according to claim 1, further comprising specifying a position where the occurrence of the problem occurs. 4. The method for inspecting a thin film transistor substrate according to claim 3, further comprising the step of identifying a position where a short circuit defect has occurred by referring to a visible image of a wiring pattern of the thin film transistor active matrix substrate. 5. Electrically connect the scanning line and signal line of the thin film transistor active matrix substrate with one terminal,
A potential difference is applied between the scanning line and the signal line, and an infrared image detector detects the heating state of the scanning line, signal line, and short-circuited part due to the current flowing through the short-circuited part of the scanning line and signal line, and a short-circuited defect is detected. If the intensity of the infrared image of a pixel address that may be damaged is higher than the reference value, it is determined that a short circuit defect exists at that pixel address, and the position where the short circuit occurs is determined from the infrared light intensity distribution. 1. A method for repairing a thin film transistor substrate, comprising: identifying a short-circuit defect, and controlling a wiring repair position using a laser or the like using the identified short-circuit defect position data. 6. A voltage applying means for applying a potential difference between the scanning line and the signal line of the thin film transistor active matrix substrate, a means for detecting an infrared image, and a means for detecting a heat generation position from the infrared image, and the infrared A thin film transistor substrate inspection device characterized by identifying a pixel address where a short-circuit defect may occur based on the heat generation state of a scanning line or signal line from an image. 7. A voltage applying means for applying a potential difference between a scanning line and a signal line of a thin film transistor active matrix substrate, a means for detecting an infrared image, and a means for detecting a heat generation position from the infrared image, and the infrared A thin film transistor substrate inspection device characterized by identifying short circuit positions from images. 8. Claim 8, comprising means for detecting a visible image at the same position as the infrared image, and identifying the position where the short circuit defect has occurred by referring to the position of the wiring pattern in the visible image. 7. The thin film transistor substrate inspection device according to 7. 9. Voltage applying means for applying a potential difference between the scanning line and the signal line of the thin film transistor active matrix substrate, means for detecting an infrared image, means for detecting a heat generation position from the infrared image, and a means for detecting a heat generation position from the infrared image. What is claimed is: 1. A thin film transistor substrate repair apparatus comprising: a control means for specifying a short circuit position and controlling a wiring correction position using a laser using the specified short circuit defect position data. 10. A thin film transistor active matrix substrate, in which a metal wiring pattern whose wiring width is narrowed to correspond to the minimum exposed line width of the wiring pattern of the substrate is provided on the outside of the electrode terminal pads of scanning lines and signal lines formed around the substrate. A thin film transistor substrate comprising: 11. The thin film transistor substrate according to claim 10, characterized in that an insulating film is coated on a metal wiring pattern having a narrowed wiring width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18390690A JP3150324B2 (en) | 1990-07-13 | 1990-07-13 | Method of inspecting thin film transistor substrate and method of repairing wiring of thin film transistor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18390690A JP3150324B2 (en) | 1990-07-13 | 1990-07-13 | Method of inspecting thin film transistor substrate and method of repairing wiring of thin film transistor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0472552A true JPH0472552A (en) | 1992-03-06 |
| JP3150324B2 JP3150324B2 (en) | 2001-03-26 |
Family
ID=16143885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18390690A Expired - Lifetime JP3150324B2 (en) | 1990-07-13 | 1990-07-13 | Method of inspecting thin film transistor substrate and method of repairing wiring of thin film transistor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3150324B2 (en) |
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