JPH0477971A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to an image processing device that stores image data and controls output of the image data.

[Prior Art] Conventionally, image data is stored, and the image data, for example,
The image processing device 1400 that controls print output is the fourteenth image processing device 1400 that controls print output.
It is configured as shown in the figure. Assuming that the starting address of the storage unit 1460 is address 0 (the address seen from the bus mask is the address to which the offset address is added), if the input/output unit of image data is 8 pixels, the storage unit of image data 1460, as shown in FIG.
In the figure, 8 pixels are stored at address 0, the 8 pixels to the right are stored at address 1, and the leftmost pixels of the 0th-order row are stored in order up to the 8 pixels in the final column. Behind the last row (
However, the pixels in that row are stored in the storage section in sequence, and the pixels in that row are stored in the storage section in sequence.

Therefore, as shown in FIG. 15, the address of each data unit (8 pixels in this case) of two-dimensional data such as image data is the address of the y-th row counting from 0, in units of 8 pixels counting from O. The address of the storage section where the column data is stored is (pitch xy+x). however,
Patch indicates the value of the final address of each row of the memory section actually arranged in a matrix, and pftch≧the length of the column of image data (hereinafter referred to as col and end). Normally, pi
As the value of tch, a value that is a power of 2 (2°) is used.

In this way, for example, the address for the storage unit during printing generated in the printer control unit 1430 of the image processing apparatus 1400 shown in FIG. No arithmetic circuit is required; just connect them.

Next, the case of a printer, such as a laser beam printer, which sends and prints data line by line of an image will be explained. Here, it is assumed that the printer device has the configuration shown in FIG. 14. FIG. 17 is a waveform diagram of various signals showing timing during printing. When the bus mask 1410 wants to write image data to the storage section 1460 or print edited image data, it issues a print request command to the bus control section 1420. At this time, the bus control unit 1420 generates a print request signal in response to the print request command and sends it to the printer control unit 1430. Printer controller 1430 communicates the request to a printer (not shown here) via printer controller 1440. When the printer is ready to print, it issues a page-by-page synchronization signal. 16th
The figure is a block diagram inside the printer control section 1430.

The printer control unit 1430 controls the column direction counter 1610 and the row direction counter 1 using the page-by-page synchronization signal shown in FIG.
620 and generates a print enable signal.
0 to the print address, and transmits a print data request signal to the bus control unit 1420.

Further, the outputs of the two counters 1610 and 1620 are connected and provided as an address to the storage section 1460 via the address selector section 1480. Therefore, the address of the storage unit 1460 when sending a page-based synchronization signal is 0.
Since the address is specified and a print data request signal is sent to the bus control unit 1420 at the same time, the bus control unit 1420
When the primary timing clock is transmitted, a control signal is sent to the storage unit 1460, and the data stored at address 0 is sent to the printer via the output data buffer 1470 and the printer control unit 1440. 1
Only 610 is incremented and a print data request signal is generated at the same time, so that the data stored at address 1 of the storage unit 1460 is sent to the printer as print data. Similarly, the values of the column counters are col, e
This is repeated until nd is reached. At this point, the printer control unit 1430 recognizes that one row of image data has been sent to the printer, so it changes the state of the column direction counter 1610 from count enable to disable, and outputs the print data request signal. The generation is stopped and the state is set to wait for a synchronization signal for each row. On the other hand, when the printer is ready to print the next line, it generates a line-by-line synchronization signal.

At this time, the printer control unit 1430 controls the column direction counter 1.
610 is cleared to zero, the row direction counter 1620 is incremented, and a print data request signal is generated again. Next, the printer stores 1460 (x
+pitch) The contents of the address are sent. In this way, the print data of the second line is sequentially sent by the timing clock which is intermittently transmitted. After this,
One line of print data is sent for each line synchronization signal. When the transmission of the last data of the last row is completed, the output of the column direction counter 1610 is col, end,
The output of the row direction counter 1620 is 1ine, end (
The print production department 1430 uses these col, end, Line,
When the value of end is detected, a print end signal is generated, and based on this, the print enable signal is set to a disable state. At this time, the bus control unit 1420 is switched to accept access from the bus mask 1410, and the address selector unit 1480 is also switched to accept access from the bus mask.

[Problems to be Solved by the Invention] However, the above conventional example has the following drawbacks.

The cut sheets that can be used with printers are usually A4 and A4.
5, B4, etc., and the image processing device also stores image data according to these paper sizes.
I was editing it. Additionally, some image processing devices can handle both portrait and landscape orientations of the same paper when printing out data, but due to manufacturing costs, etc. Generally, only print output was supported. In such a case, in order to print out a horizontally oriented image edited with an image processing device, it is necessary to send the image rotated by 90" to the printer. However, in the above conventional example, data of the rotated image is obtained. requires software processing, which increases the load on the bus mask, and as a result, other processing becomes impossible or the processing speed of other processing becomes significantly slower during printout. .

Also, for the same reason, a mirror image of the stored image data (
Since the load on the bus mask also increases when printing out a reverse image, other processing becomes impossible or the processing speed of other processing becomes significantly slow during printing.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide an image processing device that can reduce the load on the bus mask when outputting image data.

[Means for Solving the Problems] In order to achieve the above object, an image processing apparatus of the present invention has the following configuration. That is, an image processing apparatus that stores image data and outputs the image data to an output means, which includes a storage section that stores the image data, and a part of the address of the image data when inputting the image data. a first sorting means for sorting the image data and storing the image data in the storage section; reading out the image data from the image section; rotating and/or mirroring the image data; and outputting the image data to the output means. and a second rearrangement means for reading out the image data from the storage section and rearranging the image data to be output to the output means according to the instruction from the instruction means. Has equipment.

[Function] With the above configuration, the present invention rearranges input image data according to the address of the image data and stores it in the storage unit, and when reading the image data, rearranges and outputs the image data according to instructions for rotation and/or mirror image. Operate.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an image processing apparatus having an input/output data unit of 8 bits, which is a preferred embodiment of the present invention. In FIG. 1, 1 is a bus mask for the CPU, graphic controller, image processor, etc., 2 is a storage unit that stores image data, and 3 is a bus mask for storing image data such as the storage unit 2 from the address and control signal of the bus master l. 4 is an input/output data rearrangement unit that rearranges the data accessed by the bus master 1 according to part of the image data address; 5 is a bus controller that generates control signals;
Printer control that generates an address for reading out image data to send to (not shown here), a rearrangement signal for the data read out at that time, a printer control signal, and other control signals for printing. Part 6 is the bus/
An address that switches between the address when accessing master 1 and the address generated by printer control 5 when printing.
A selector unit 7 is a print data rearrangement unit 8 that rearranges the image data read from the storage unit 2 in accordance with a rearrangement signal from the printer control unit 5 to send to the printer.
is a printer control unit which is an interface with the printer.

In this embodiment, each part (#7 to #0) of the storage section 2 of the image processing apparatus will be explained as having 2 megabits (1 megabit=1048576 (=2 to 0) bits). Furthermore, assuming that the image data is 1 pixel and 1 bit, 1
The input/output of each bit is stored in memory units #7 to # for the unit of human power.
Suppose that they are respectively assigned to 0. In such a case, the address A represents the storage location of the image data stored in the storage unit 2. Since the capacity of each part (#7 to #0) of storage section 2 is 2 megabits (= 2'' bits),
It can be expressed as a length of 1 bit. Now this address Al
Let each bit of l be A2° to A0.

Further, the total storage capacity of the storage unit 2 in this embodiment is 2 megabits x 8 = 16 megabits, so for example, 409
With a configuration of 6 pixels x 96 lines, it is possible to handle 1 bit of image data per stroke.

Next, as shown in FIG. 2(A), 1 pixel, 1 bit, 40
If the entire image data consisting of 96 pixels (horizontal) x 4096 lines (vertical) is divided into blocks of 8 lines x 8 pixels, the address A is shown in FIG. 2(B).

The internal structure of is A, -A, the block address of each column, A20~Ars is the block address of each row, and each line address of 8 rows in each block is A + +
~A, can be combined to express each. In particular, A, ~A 0, A*. ~A11, A11~
A, M B CA 8~O (Memory
Block ColumnAddress: Memory block column address), MBRA 8 to 0 (Mea+o
ry Block Row Address: Memory block row address), MLNA 2~O (Mem
oryBlock Line Address: Memory block line address). In the image processing device shown in FIG. 1, the bus master 1 actually
When accessing and writing or reading image data, M B CA n (n == 0
~8) and MB RAn (n=o~8) are passed through the address selector section 6 and stored as they are in the storage section 2, BCAn (block column address) and BRAn (
M B CA n
=BCAn, MBRAn=BRAn. Also, M
The value of LNAn (n=O~2) is commonly supplied to MAn (memory address) of each part of the storage section 2 through the address selector section 6.

In an image processing device using such an image data storage method, when storing images in the vertical direction, the section 31 of the storage unit 2 is used as shown in FIG. In order to memorize , part 32 of ■ should be used.

In this embodiment, the image data handled by the bus master 1 is rearranged by the input/output data rearranging unit 4 and read from and written to the storage unit 2 according to MLNAn. Here, as shown in FIG. 4(A), the left end of the 8 pixels of the image data input/output unit handled by bus master 1 is bl,
It is assumed that reading and writing are performed through the input/output data sorting unit 4 with the right end as bO. Various rearranging methods can be applied, but in this embodiment, the input (in7. in6. in5゜i
n4. in3. in2. inl, 1no) and data 41 (bl.

b6. b5. b4. b3. b2. bl, b
O) is input, the output (out7. out6.
out5. out4. out3. out2゜ou
tl, auto) are rearranged according to the values of MLNA2 to 0 and are considered to be as follows. Figure 4 (A
), MLNA2-0 consists of 3 bits, so each bit is 82, Sl.

I am SO. For convenience of explanation, swap S2 SI SO (S2 SI
A value of O or 1 is entered in each SO. However, 52=
If S1=SO=0, swapoo means no reordering. ) and name it.

When (S2 SI SO) = (0, 0, 0), (b
l, b6. b5. b4. b3. b2. bl, bO):
swapoo(S2 SI So) = (0,0
, 1), (b6.bl, b4.b5.b2.b3.
bO, bl) : swapool(S2 SI SO
) ” (0,1,0).

(b5.b4.b7.b6.bl, bo, b3.b2)
: swapolo(S2 SI SO) =
When (0, 1, 1), (b4.b5.b6.b7.bo
, bl, b2. b3): swapoll (S2 S
ISO) = (1,00), (b3.b2.b
l, bo, b7. b6. b5. b4): swapl
When oO(S2 SI SO) = (1,0,1),
(b2.b3.bO, bl, b6.b7.b4.b5)
: swaplol(S2 SI So) = (1
, 1, 0), (bl, bo, b3.b2.b5.b
4. b7. b6): swapH0(S2 St S
o) = (1, 1, 1), (bo, bl, b2.
b3. b4. b5. b6. b7n: swapph
The logical formula corresponding to this sorting method is shown in Figure 4 (B).
As shown in FIG. 2, the circuit that implements this can be configured with eight 8→1 (indicating that one item is selected from eight input data) data selectors.

FIG. 5 shows the configuration of the input/output rearranging section 4. As shown in FIG. Since the image data has the property of returning to its original state if the rearrangement swap S2 SI SO is performed twice, when the bus master 1 writes image data, the data to be written is swap S2 by the input/output data rearrangement unit 4.
The information is rearranged according to the method expressed by SI So and stored in the storage unit 2. Furthermore, when the bus master 1 reads the same image data, the input/output data sorting unit 4 again swaps S2 SI S.

are sorted and read out according to the method expressed by .

Therefore, as a result, the same data that was written will be read. For this reason, bus master 1
can access the storage unit 2 without being aware of the rearrangement method (similarly to normal memory).

Based on this reason, the input/output data sorting unit 4 shown in FIG.
Two bit swappers 51 and 52 having the same rearrangement circuit for input and output are used by utilizing the property of . Using the input/output data sorting unit 4 designed in this way, the bus/mass RI 1 writes image data into one image data block composed of 8 lines x 8 pixels as explained using FIG. FIG. 6 shows how the storage section 2 stores data at this time. 61 in FIG. 6 is the bit arrangement for one block of image data when input to the input/output data rearranging section 4, and 62 in FIG. 6 is stored in the storage section 2 after being rearranged by the input/output data rearranging section 4. It represents the bit arrangement for one block of image data that is output for the image data.

In this embodiment, the above-mentioned sorting method is used, but as another sorting method, for example, as a sorting method at the time of input, (S2 SI SO) = (0, 0, 0
) is 0 bit, (0, 0, 1) is 1 bit, (
0, 1, 0), it is 2 bits, and in the same way, (1, 1
, l), a method may be used in which each of the 7 bits is rotated to the left, and a method in which the output is rearranged at the time of output is rotated to the right. However, when using such a method, input, output Since the reordering methods are different, it is necessary to design the input/output data reordering section 4 so that the same data written in the storage section 2 as seen from the bus master 1 is read out.

Next, consider a case where the bus master 1 writes into the storage section 2 and outputs edited image data to a printer. rotate·
Mirror image specification is performed using the rotation/mirror image specification signal (mode2.mo
The three types of signals (del, modeo) are bus
This is done by the bus control section 3 sending a message to the printer control section 5 based on a command from the master 1. In this embodiment, it is assumed that there is a method for specifying rotation/mirror image as shown in FIG. 7(A), and based on the specification, rotation/mirror image processing as shown in FIG. 7(B) is performed. do. Figure 7 (
In B), the character pattern "R" is used as an example.

Here, 0° without mirror image means that the same image data as the input data is output to the printer. FIGS. 8(A) and 8(B) are block diagrams showing the configuration of the printer control section 5. FIG. Compared to the printer control unit 143o of the conventional example explained in FIG. and row direction counter 504
Based on part of the mirror image designation signal (model and model), either up counting or down counting is selected, and the counter output is used to determine the address for the storage unit 2 and the print data rearrangement unit. A function is added to generate a rearrangement designation signal for 7.

On the other hand, the control signals to the printer I/F section 8 and the bus control section 3 are the same as in the prior art.

First, consider processing in blocks of 8 lines x 8 pixels. The column direction counter 501 counts the output paper of the printer in the column direction (in 8 pixel units), and the address of the column of 8 lines x 8 pixel blocks on the output paper is counted as a (CCN78 to 0) of the column direction counter 501. Output. In addition, the row direction counter 504 counts the row direction (in units of one line) of the output paper of the printer, and the row address of the 8 lines x 8 pixel block on the output paper is output from the row direction counter 504 (RCNTII to 3).
Also, the row address in this 8 line x 8 pixel block is the same as the output of the row direction counter 504 (RCNT
2 to 0). The usage of RCN72-0 will be explained later in 6 column and row direction counters 501.5.
04 can be moved up or down by specifying rotation/mirror image.
Works as a counter. During up-count operation, the column and row direction counter initial value setting units 502 and 505 set each counter 50 by the load operation of each counter 501 and 504.
The counter value of 1.504 is set to O, and the column and row direction comparators 503 and 506 respectively set the counter value of the column and row direction counters 501 and 504 and the column direction final image data block value (col, end) and row direction. direction final image data block value (1-ow, end)
Compare with. Similarly, during the down count operation, the initial value setting sections 502 and 505 are set to col and 505, respectively, during the load operation.
The values of end, row, and end are set in the column and row direction counters 501 and 504, respectively, and the comparator 5
03.506 are column and row counters 501, respectively.
．． The counter value of 504 is compared with 0. Each counter output CCNT8~0 and RCNT11~3 is connected to P B CA 8~O (Pr1n
t Block ColumnAddress Niblint block column address) P B RA 8~0 (P
rint Block Raw Address An address for accessing the storage unit 2 is supplied through the address selector unit 6 as the rint block raw address. In this way, PBCA8~0, PERA
Column and row addresses of an 8 line x 8 pixel block of image data stored in the storage unit 2 are designated by each of 8 to 0.

When the rotation specification is O'' or 180° (mode 2
(exor model=O, exor is exclusive OR), the 2→1 data selector 507 inputs two input data CCNT8-0 and RCNTII-3 from the 0 side of input gates 81 and 82, and Since the data is output from the two corresponding output gates 83 and 84, CCN78~0 are sent to PBCA8~0, RCNTII~
3 will be passed to PBRA8-0. Therefore, the manner in which the columns and rows of the 8 line x 8 pixel block of the image data stored in the storage unit 2 are specified is the same as that of the output paper of the printer. On the other hand, the rotation specification is 90' or 270'
In the case of (mode2 exor model=1)
In this case, the 2-1 data selector 507 selects the input data C
Two human powered gates: CNT8~0 and RCNTII~3
Since the data is input from the 1 side of 1 and 82 and output from the two corresponding output gates 83 and 84, C
CN78-0 will be passed to PBRA8-0, and RCNTII-3 will be passed to PBCA8-0. Therefore, the correspondence between the output paper of the printer and the column and row specifications of the 8-line x 8-pixel block of image data in the storage section 2 is reversed. This correspondence between row and column specifications and column and row counters 50
Based on the up/down/count correspondence of 1.504, the relationship of the state change of print output according to the designation of rotation/mirror image of the image data in the storage unit 2 is shown in FIGS. 9(A) to 9(I). As shown in the figure, it can be seen that print output is performed in accordance with rotation/mirror image specifications in block units of 8 lines x 8 pixels.

Next, consider the inside of an 8 line x 8 pixel block.

The designation of the row inside the block is represented by RCNT2-0. First, the case where the rotation designation is 00 designation will be explained. Figure 10 (A) shows 0° designation (mod, e2
RCNT2 to 0 in the case of = model = O)
The value of and the memory address of each part of storage unit 2 (#7 to #0) (
It is a figure showing the relationship with MA2-0). PM output from the printer control unit 5 based on the values of RCNT2 to 0
A2~0(Pr1nt Memory Address
2blint memory address) is supplied to the storage unit 2 via the address selector unit 6 as MA2 to MA0.

As shown in FIG. 10(A), in the case of 00 designation, MAn
=RCNTn. The state in which the image data shown at 61 in FIG. 6 is stored in the storage unit 2 is shown as the internal state of the block 101 in FIG. 10(B).

Here, the subscript at the top right of each pixel is the value of RCNT2 to 0 expressed in lO base.For example, the first row where this subscript is 0 is RCNT2 to 0 = (0, 0, 0)
represents the pixel read out when . The same applies to cases where the subscript number is 1 to 7. Based on the instruction indicated by this subscript number, the image data is read from the storage section 2 and becomes input to the print data sorting section 7 shown at 1.02 in FIG. 10(B). The print data sorting unit 7 sorts the image data 102 based on the sorting method 105 in the case of 0'' modeO=O) without mirror image.
10(B) 103 is output, and the same print data as the original image is obtained.

Also, there is an Oc′ mirror image (mode.

= 1), as shown in the reordering method 106, S
2~0 = RCNT2~O, so Figure 10 (
B) Print data is rearranged as shown in 104 and has a 0° mirror image.

Next, specify 90° to the left (mode2 = O, model
Consider the case of =1). From printer control unit 5 to RCNT
PMAs2-0 output based on the values 2-0 are supplied to the storage unit 2 as MA2-0 via the address selector unit 6. At this time, the values of RCNT2 to O and the memory addresses (MA2 to 0) of each part of the storage unit 2 (#7 to #0)
The relationship between each storage unit (
#7 to #0) are different. This means that the 11th
It is expressed by the subscript number at the upper right of each pixel shown in the internal state of block 111 in FIG.

For example, when RCNT2~o = (o, o, o), the pixel whose subscript value is O is read out, so
The data in the first line input to the print data rearrangement unit 7 shown at 112 in FIG. 11(B) is a list of these data. RCNT2~0 = (0,0,1)~
The same applies to the case of (1, 1, 1). The print data rearranging unit 7 sets the left 90° mirror image mode.
o = 1), the image data 112 is rearranged based on the rearrangement method 115, so the image data 112 is rearranged based on the rearrangement method 115.
) 113, print data without the left 90' mirror image is obtained.

In addition, in the case of a left 90° mirror image (a+odeO=0), the reordering method is as shown in 116, S2~0=
Since the RCNTs are RCNT2 to 0, print data with a left 90' mirror image as shown in FIG. 11(B) 114 is obtained.

Figures 12 and 13 are designated as 1800, respectively, and 270 on the left.
This shows the case where ° is specified, and the explanation is the same as above.

[Other Embodiments] When the storage unit 2 is configured with a dynamic RAM, the bus control unit 3 generates RAS, CAS, and WE signals, and the output address of the address selector unit 6 is divided into two RA
It is sufficient to supply it to the dynamic RAM in accordance with S and CAS.

Furthermore, in the above embodiment, a system that handles image data of 1 pixel and 1 bit has been explained, but in the case of a system that stores 1 pixel as multiple bits, such as a printer that outputs gradations or a color printer, If the present invention is applied to each bit, it becomes possible to print out a rotated/mirror image.

Therefore, according to this embodiment, it is possible to print out a rotated or mirrored image of stored image data without the need for software or complicated hardware.

[Effects of the Invention] As described above, according to the present invention, stored image data can be rotated or mirrored without software processing, so that the load on the system can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an image processing device that is a typical embodiment of the present invention. Fig. 2 (A) shows the entire image data and each block when the image data is divided into blocks of 8 lines x 8 pixels. A diagram showing the correspondence between blocks. Figure 2 (B) is an internal configuration diagram of an image data address An when image data is divided into blocks of 8 lines x 8 pixels. Figure 3 is an image data storage unit and image data output. Figure 4 (A) shows the input and output data and control data of the data input/output sorting circuit; Figure 4 (B) shows the logic corresponding to the input/output data sorting method. Figure 5 is a block diagram showing the internal configuration of the input/output data rearranging unit. Figure 6 shows the correspondence between input image data and storage unit in an image data block consisting of 8 lines x 8 pixels. Figure 7 (A) is an explanatory diagram of specifying rotation/mirror image, Figure 7 (B)
) is a diagram showing a specific example of rotation/mirror image of image data, Figure 8 (A) is a diagram showing the configuration of the column and row counter units of the printer control unit, and Figure 8 (B) is a diagram showing the pressure of the printer control unit. FIG. 9(A) is a diagram showing the image data stored in the storage section and 8.
Figures 9(B) to 9(I), which show the correspondence within one block of image data composed of lines x 8 pixels, are composed of 8 lines x 8 pixels read out according to rotation/mirror image specifications. Figures 10 to 13 show image data 1 of 8 lines x 8 pixels.
FIGS. 14 to 17 are explanatory diagrams of rotation and mirror image operations within a block, and FIGS. 14 to 17 are explanatory diagrams of conventional examples. In the figure, 1... bus mask, 2... memory section, 3...
・Bus control unit, 4...Input/output data sorting unit, 5
...Printer control section, 6.. Address selector section, 7.. Print data sorting section, 8.. Printer 171 section, 51.. Pit swapper, 52..
Pit swapper, 501...Column direction counter, 502
. . . Column direction counter initial value setting unit, 503 . . . Column direction comparator, 504 . . . Row direction counter, 505
. . . row direction counter initial value setting unit, 506 . . . row direction comparator, 507 . . . 2→l selector. Patent Applicant Canon Co., Ltd. Figure Σ and Figure (G) Figure 9 (H) Figure (1) 慟. C Figure 17

Claims (1)

[Scope of Claims] An image processing device that stores image data and outputs the image data to an output means, comprising: a storage unit that stores the image data; and an address address of the image data when inputting the image data. In accordance with a part of the invention, a first rearrangement unit rearranges the image data and stores the image data in the storage unit, reads the image data from the image unit, and performs rotation and/or mirror image processing on the image data. an instruction means for instructing the output means to output; and a second rearrangement means for reading the image data from the storage unit and rearranging the image data to be output to the output means according to instructions from the instruction means. An image processing device comprising: