JPH0496845A - Data storage methods in shared memory systems - Google Patents

Abstract

PURPOSE:To gather update information of a specific module with a system operated by providing a selecting means which selects the mode of disconnection of a part of a shared memory only for the specific module and the mode of disconnection of a partial memory from the update processing of normal work. CONSTITUTION:An SVP 10 selects a mode 1 by a mode selecting means 14 of a switching means 11 to select control modules 7 to 9 as specific control modules. One of memories 5 and 6 is designated as the private memory of specific modules 7 to 9. The SVP 10 selects a mode 2 by the mode selecting means 14 of the switching means 11 and simultaneously selects only memories 5 and 6 and interrupts the update processing of selected memories to gather recorded information. Thus, one memory which is not designated continues the normal work and information of specific modules can be acquired from selected memories in any mode.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory storage method in a system where multiple CPUs share multiple memories, the purpose of this invention is to update multiple memories at the same time, with the aim of making it possible to collect update information about a specific module. Mode O2: Select any module from among multiple control modules and update or read only the selected module. Mode 1: Select any memory from among the multiple memories. mode selection means for selecting mode 2 for interrupting updating of the selected memory; module selection means for selecting a designated control module; and memory selection means for selecting memory in mode 1 or mode 2; In mode 2, a control module and memory are selected and the update information of the selected control module is obtained from the selected memory, and in mode 2, only memory is selected and the update of the selected memory is interrupted and the recorded updates are obtained. It has a configuration to obtain information.

[Industrial application field]

The present invention relates to a memory storage method in a system in which multiple CPUs share multiple memories.

In a system where multiple CPUs share memory,
Data on the memory is updated by a plurality of modules such as CPUs, and information updated by a certain module is not always updated by that module, but may be updated by another module.

Therefore, in conventional memory sharing systems, it is difficult to collect and save data updated in a specific module.

On the other hand, when a failure occurs in a specific module, it is necessary to collect and analyze update information for the specific module in order to investigate the failure. I had no choice but to stop updating the entire memory and collect the necessary information.

The present invention provides a memory sharing method that allows information about a specific module to be collected while continuing normal system operations.

[Conventional technology]

FIG. 7 shows a conventional shared memory system.

In the figure, 65 to 67 are CPLII to CPUm, which share multiple memories, and 70 is a memory control unit, which controls reading or writing of memory according to instructions from CPLJ1 to CPL]+n. , 71.72 are memory 0 and memory 1, respectively,
For example, 73 is a control module A consisting of a semiconductor disk memory, and memory 0. A director module that controls the interface between memory 1 and the host device (command reception analysis, response, data transfer control, etc.)
74 is a control module B, for example, a back amplifier disk controller (BDC) that performs control as a disk controller (assembly, disassembly, format conversion, etc. of data); 75 is a control module C;
5EEK, READ, according to the instructions of BDC.
A micro disk adapter (MDA) performs assembly microprogram control (semiconductor memory access, etc.) such as WRITE, and 76 is a service processor (
SVP).

The operation of the memory sharing system shown in the figure is as follows. Memory O and memory 1 in the figure are shared by CPUI to CPIJm, and are updated simultaneously by the memory control unit 7o upon request from any of the CPUs. It is.

For example, when the CPU issues a request to update memory 0 and memory 1, control module A (DIR) confirms that these memories are not being updated and responds with permission to use the memory.

Next, control module B (BDC) and control module C (
MDA) executes control to simultaneously update memory 0 and memory l.

The 5VP 76 executes service-like processing such as diagnostic processing for control modules A to C.

[Problem to be solved by the invention]

In a system as described above in which multiple CPUs share multiple memories via multiple control modules, a certain C
The data updated by PU may be further updated by other CPCI, and even on the control module side,
Since the same module is not always updated, it is difficult to grasp the update status of only a specific module.

For example, when a failure occurs in a specific module, it is necessary to collect update information for the failed module in order to investigate the failure, but in conventional shared memory systems, memory is constantly updated. Because
Gathering updated information about specific modules was difficult.

Furthermore, interrupting the update process is not desirable in terms of system operation.

An object of the present invention is to provide a data storage method in a shared memory system that can collect updated information about a specific module while the system remains in operation, even when a failure occurs in a specific module. .

(Means for Solving the Problems) The present invention provides a mode in which a part of the shared memory, which is normally updated at the same time, is separated from the normal work for exclusive use of a specific module, and a part of the memory is separated from the update processing of the normal work. A mode selection method has been provided for the disconnection mode. Update information about a specific module can be obtained from the disconnected memory. Also, during normal operations, update processing can be continued using the memory on the side that is not specified. .

FIG. 1 shows the basic configuration of the present invention.

In the figure, 1 is a memory control unit, and 2 to 4 are CPUs 1 to C.
Modules consisting of PUm, 5 and 6 each have memory 0
．． A memory 1 is a semiconductor disk memory or the like, 7 is a control module A, for example a DIR, and 8 is a control module B, for example a BD.
9 is a control module C, for example an MDA; 10 is a service processor (SVP);
) which executes administrative processing of the memory control unit 1; 11 is a switching means which selects and disconnects a specific module and memory to be separated from normal system operations; 12 is a module selection means; 13 is a memory selection means for selecting a memory to be separated; 14 is a mode for selecting normal mode 0 for updating multiple memories at the same time; mode 1 for selecting a dedicated memory for a specific module; and mode 2 for selecting only a specific memory. It is a means of selection.

[Effect]

The operation of the basic configuration of the present invention will be explained with reference to FIG. Refer to FIG. 1 as necessary.

In FIG. 2 (al, et al.), 20 to 23 are control modules, for example, a module for controlling a semiconductor disk memory, and the control module A in FIG.
- Corresponding to C, 25 is a switching means that selects a mode, selects a specific module, selects a dedicated memory for a specific module, or selects a separate memory; 2;
Reference numeral 6.27 represents a memory, such as a semiconductor disk memory, 28 represents module selection means for selecting a specific module, and 29 represents mode selection means.

FIG. 2(a) shows the case of mode 1.

In figure (a), for example, 5VP2. A case is shown in which one of the semiconductor disk memories is dedicated to module A because it becomes necessary to collect the diagnostic progress of module A while II is diagnosing the module.

The 5VP 24 selects mode 1 by the mode selection means 29 of the switching means 25, and selects module A as the specific module. The SVP then designates the memory 27 as a dedicated memory for a specific module. The memory 26 serves as a shared memory for module B, module C, and module D, and continues the update process.

As a result, the memory 27 makes it possible to collect the diagnostic progress of module A.

FIG. 2(b) shows the case of mode 2.

FIG. 0)) shows a case where, for example, when a failure occurs in one of the modules, it is necessary to collect information on the progress up to the occurrence of the failure.

Therefore, SvP sets the mode selection means 29 of the switching means 25 to mode 2, and at the same time interrupts the updating process of the memory 27. The other memory 26 is allowed to continue updating.

Since the memory 27 stores records of updates up to that point, by collecting this information, it is possible to obtain the progress up to the occurrence of a failure.

According to the present invention, in any of the above modes, the one memory that is not designated continues normal operations, and information on a specific module can be obtained from the selected memory.

〔Example] FIG. 3 shows an embodiment (1) of the present invention.

In Figures (a) and (b), the shared memory is a semiconductor disk memory, and since the SVP needs to obtain the progress of the diagnosis while diagnosing the BDC, one of the semiconductor disk memories is dedicated to the BDC. Indicate the case.

The figure (→ indicates the flow of mode 1, and the figure) shows a state in which mode 1 is selected in the configuration of a shared system.

Note that the configuration of the CPU, etc. is omitted.

In Figure (1)), 30 to 32 are control modules, 30 is a DIR, 31 is a BDC 132 is an MDA, 33 is an SVP, 34 is a switching means, 35 is a semiconductor disk memory (PSAO), and 36 is a semiconductor A disk memory (PSAI), 37 is a mode selection means, and 3 is a module selection means.

The operation of the configuration shown in FIG. 1 will be explained using the flow shown in FIG.

The flow will be explained according to the numbers shown.

■ 5VP33 starts executing diagnosis of BDC31.

■ After starting the diagnosis, it became necessary to dedicate one memory to the BDC31, so the 5VP33 selected mode 1 and dedicate one of the semiconductor disk memories 35 and 36 to the BDC31.
and instructs the switching means 34 to make it exclusive use for.

■ Mode 1 is set in the mode selection means 37 in the switching means 34, and the module selection means 38,
The BDC is selected as a specific module based on the module ID of the BDC 31 .

Then, PSAI becomes a dedicated memory for the BDC 31.

(2) As a result, since the PSAI becomes a dedicated memory of the BDC 31, it becomes possible to collect the diagnosis progress from any time thereafter.

FIG. 4 shows an embodiment (2) of the present invention.

In Figures (a) and (b), the shared memory is a semiconductor disk memory, and when a failure occurs in the DIR of the control module, the memory PS is used to collect previous information.
The case where AI update processing is interrupted is shown.

Figure [a] is a flow, and Figure (g)) shows the selected state of mode 2 in the configuration of the shared system. In addition, the CPU
Structures such as these are omitted.

In Figure (b), 40 to 42 are control modules, 40 is a DIR 141, a BDC 142 is an MDA, 43 is an SVP, 44 is a switching means, 45 is a semiconductor disk memory (PSAO), and 46 is a semiconductor disk memory ( PSAI), 47 is a module selection means, and 48 is a mode selection means.

The operation of the configuration of the section) will be explained with reference to the flow shown in FIG.

The flow will be explained according to the numbers shown.

■ Connect the failed control module (DIR40) to 5V.
P43 recognizes it.

(2) The 5VP 43 instructs the switching means 44 to select mode 2. Then, mode selection means 48 sets mode 2.

■ PSAI update is interrupted. PSAO updates continue.

■ From the data recorded in PSAI, DIR40
It becomes possible to collect information up to the point where a failure occurs.

FIG. 5 shows an embodiment of the switching means of the present invention.

In the figure, 50 is a control bus control circuit (C-B
us control circuit), 51 is a mode switching register that sets a value for each selected mode, and for example, the combination of bit 0 and bit 1 (bit 0. bit 1) is (0, 0
) is the normal mode, (0, 1) is the specific module selection mode, (l0) is for selecting one side memory update interruption,
Reference numeral 52 denotes a mode switching circuit (DEC), which outputs A and B according to the setting value of the mode switching register 51.
, C for example, A, B, C (7) combination (A.

As for B and C), the normal mode is (1, 0, 0), the specific module selection mode is (0, 1, 0), the one-sided memory update interruption mode is (0, 0, 1), and 53 is the memory. A certain PSAOPSAI address/data register (
ADR5/DATAREG, ), 54 is a module ID register (MOD) that sets the ID of the specified module.
ULEID REG, ), 55 is the ID of each module
The module selection register (MODU
LE 5ELECT REG, ), 56 is the value of the module ID register 54 and the module selection register 55
For example, if there is a module ID specified and they match, the value 1 is output, and if there is no module ID specified and they do not match, the value 57 is output to the output of the mode switching circuit. Value and address data register 53
58 is an AND circuit (A2) that ANDs the value of the output B of the mode switching circuit, the value of the address/data register 53, and the output of the comparator 56, and 59 is a mode switching circuit. An AND circuit (A3) that ANDs the value of the output C of the circuit and the value of the address/data register 53, 60 a NOT circuit (N) that negates the value of the output C of the mode switching circuit, and 61 an AND circuit A1. A
2. An OR circuit (OR) that takes the OR of A3, and an AND circuit (62) that takes the AND of the values of the NOT circuit 60 and the OR circuit 61.
A4), 63 and 64 are semiconductor disk memories P, respectively.
SAI and PSAO.

FIG. 6 shows an example of mode setting values in the present invention.

In the normal state, for the combination of focus 0 and bit 1 of the mode switching register (bit 0° focus 1), the normal mode is (0, 0), the specific module selection mode is (0, 1), and one side memory update is interrupted. The mode is (1,0
).

In addition, the mode switching circuit (DEC) 52 outputs the outputs A, B, and C of the mode switching register 51 and selects the combination (A, B,
C), the normal mode is (1,.

O), the specific module selection mode is (0,10) and the one-sided memory update interruption mode is (001).

The operation of the embodiment shown in FIG. 5 will be explained with reference to FIG.

(1) Update processing in mode 0 (normal mode) As shown in FIG. 6, the output A of the mode switching circuit 52
, B, and C are each 1. It becomes O, O.

77 times BA 1 is selected, and AND circuit A 2 ,
:! : Both A3 are unselected. Therefore, the address and data of the address data register 53 are input to the OR circuit 61.
The signal is input to the AND circuit A4 via.

Since the value of the output C is 0, it becomes 1 in the NOT circuit 60, and the AND circuit A4 is selected and data is written to the address designated by PSAI.

On the other hand, PSAO has an address/data register 53L.
Data is written to the specified address.

(2) In mode l (specific module selection mode), the outputs A and BC of the update processing mode switching circuit 52 are each 0.
It is 1.0.

Therefore, AND circuit A2 is selected, and AND circuit A1
and A3 becomes unselected.

Also, if the ID of the selected module is input to the module ID register 54 and matches the set value of the module selection register 55, compare! 'The value l is output from S56.

Therefore, the data specified by the address stored in the address/data register 53 regarding the data generated from the selected module passes through the AND circuit A2 and the OR circuit 6J.

On the other hand, since the output C of the mode switching circuit 52 is 0, it is negated by the negator 160 and becomes l, and the AND circuit A4
is the choice.

Therefore, the data of the selected module is written to the designated address of PSAI via AND circuit A2, OR circuit B61, and AND circuit A4.

On the other hand, for data with a module ID that is not specified, the output of the comparator 56 becomes 0, the AND circuit A2 is not selected, and the data is written only to the PSAO with the specified address specified, and updates in normal work are performed. It can be carried out.

(3) Outputs A, B, and C of the update processing mode switching circuit 52 in mode 2 (a mode in which updating of one side of the memory is interrupted) are as follows:
O, 0, 1.

Therefore, as a result of the value l of C being negated by the negation circuit 60, the AND circuit becomes non-selected, PSAI is separated from the address/data register 53, and the data is not updated.

On the other hand, data is written to the address specified by the address/data register 53 in the PSAO, and normal operations are updated.

Furthermore, in the configuration of FIG. 5, data on the memory is read from the PSAO.

〔Effect of the invention〕

According to the present invention, in a memory sharing system, it is possible to obtain update information of data on memory regarding a specific module while continuing normal operations of the system.

Therefore, even if a failure occurs in a specific module, it is possible to diagnose the specific module without interrupting system operations.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention. FIG. 2 is an explanatory diagram of the operation of the basic configuration of the present invention. FIG. 3 is a diagram showing Example (1) of the present invention. FIG. 4 is a diagram showing Example (2) of the present invention. FIG. 5 is a diagram showing an embodiment of the switching means of the present invention. FIG. 6 is a diagram showing an example of mode setting values in the present invention. FIG. 7 is a diagram showing a conventional shared memory system. 14: Mode selection means.

Claims (1)

[Claims] In a system in which a plurality of CPUs (2 to 4) share a plurality of memories (5 to 6) via a memory control unit (1), the memory control unit (1) has a plurality of control modules. (7-9
), Mode 0 updates multiple memories (5-6) simultaneously, selects any module (7-9) from multiple control modules (7-9), and updates or reads only the selected module. Multiple memories (5~
6) mode selection means (14) for selecting a mode 1 arbitrarily specified from among the above, and a mode 2 for selecting an arbitrary memory and suspending updating of the selected memory; module selection means (12) for selecting the selected control modules (7 to 9); and memory selection means (13) for selecting the memory.
In the above mode 1, the control module (7 to 9) and the memory are selected, and update information of the selected control module (7 to 9) is obtained from the selected memory, and in the above mode 2, the memory is selected. A data storage method in a shared memory system, characterized in that only (5 to 6) is selected, the update of the selected memory is interrupted, and the recorded update information is acquired.