JPH05114857A - PLL circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] The lockup time is shortened by suppressing the fluctuation of the control voltage to the voltage controlled oscillator when the frequency lock is lost. [Configuration] A PLL circuit configured by a crystal oscillator 11, a 1 / N frequency divider 12, a phase comparator 13, a low pass filter (LPF) 14, a voltage controlled oscillator (VCO) 15 and a 1 / M frequency divider 16, Control voltage Vi to the voltage controlled oscillator 15
A lock state storage circuit 20 and a lock state reproduction circuit 23 for controlling the above are added. The phase comparator 13 has a function of determining the state of frequency lock in addition to the function of outputting the phase error signal e. The lock state storage circuit 20 has a first switch 17 that is closed when the frequency is locked, and a control voltage Vi is applied to the first switch 17 through the first switch 17.
A / D converter 18 and a data holding circuit 20 are provided. The lock state reproduction circuit 23 includes a D / A converter 21 to which the output of the data holding circuit 19 is given and a second switch 22 which is closed when the frequency lock is released.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit capable of shortening lockup time.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional PLL circuit. In the figure, 11 is a crystal oscillator, 12 is a 1 / N frequency divider, 13 is a phase comparator, and 14 is a low-pass filter (L
PF), 15 is a voltage controlled oscillator (VCO), 16 is 1 /
It is an M frequency divider.

The phase comparator 13 divides the output of the crystal oscillator 11 by the 1 / N frequency divider 12 into a signal fr and the output of the voltage controlled oscillator 15 by the 1 / M frequency divider 16 into a signal fv.
The phase difference between the two signals is compared with the phase error signal e
Output as. Moreover, the low-pass filter 14, the voltage controlled oscillator 15, and the 1 / M frequency divider 16 are the phase comparator 13
Since it is connected in a loop via the control voltage Vi to the voltage controlled oscillator 15 so that there is no phase difference between the two signals fr and fv, that is, the phase error signal e becomes zero during so-called frequency locking. Occurs, and a signal having a desired frequency is obtained from the voltage controlled oscillator 15.

[0004]

The conventional PLL circuit described above includes a low-pass filter 14, a voltage-controlled oscillator 15 and 1.
Since the / M frequency divider 16 constitutes a simple loop via the phase comparator 13, if the frequency lock is lost for some reason, the output signal fr of the 1 / N frequency divider 12 and 1 / M frequency
A phase difference is generated between the output signal fv of the frequency divider 16 and the control voltage Vi to the voltage controlled oscillator 15 fluctuates. Moreover,
Since the control voltage Vi repeatedly fluctuates until the frequency locked state returns to the frequency locked state, there is a problem that the recovery time, that is, the lockup time becomes long.

An object of the present invention is to reduce the lock-up time by suppressing the fluctuation of the control voltage applied to the voltage controlled oscillator when the frequency lock is lost.

[0006]

In order to achieve the above object, the present invention holds information on the control voltage Vi when the frequency is locked, and based on the held information, the control voltage Vi when the frequency is out of lock. It adopts a configuration for controlling the.

Specifically, the present invention, as shown in FIG. 1, includes a crystal oscillator 11 for obtaining an original oscillation, and a first frequency divider 12 for dividing the output of the crystal oscillator 11. , A voltage-controlled oscillator 15 for obtaining an output signal having an oscillation frequency according to a given control voltage Vi, and a second frequency divider 16 for dividing the output signal of the voltage-controlled oscillator 15.
And the phase error e of the output signal fv of the second frequency divider 16 is detected with the output signal fr of the first frequency divider 12 as a reference, and the control voltage Vi corresponding to the phase error e is controlled by the voltage control. A phase comparator 13 for giving to the oscillator 15, a lock state storage circuit 20 for holding the value of the control voltage Vi to the voltage controlled oscillator 15 at the time of frequency lock, and a lock state storage circuit 20 when the frequency lock is lost. And a lock state reproducing circuit 23 for receiving the value of the control voltage Vi held by the above and applying the received control voltage Vi to the voltage controlled oscillator 15.

[0008]

According to the present invention, when the frequency is locked, the value of the control voltage Vi to the voltage controlled oscillator 15 is set to the lock state storage circuit 2.
It is held at 0. And when the frequency lock is released,
Since the control voltage Vi to the voltage controlled oscillator 15 is controlled based on the held contents, the fluctuation of the control voltage Vi when the frequency lock is released is suppressed and the lock-up time is shortened.

[0009]

1 is a circuit diagram of a PLL circuit according to an embodiment of the present invention. In the figure, 11 is a crystal oscillator, 12
Is a 1 / N frequency divider, 13 is a phase comparator, 14 is a low pass filter (LPF), 15 is a voltage controlled oscillator (VCO),
Reference numeral 16 is a 1 / M frequency divider, which has the same configuration as the conventional one. However, the phase comparator 13 is the 1 / N frequency divider 1
In addition to the function of outputting the phase error signal e corresponding to the phase error of the output signal fv of the 1 / M frequency divider 16 with respect to the output signal fr of 2, the function of determining the state of frequency lock is provided. That is, the phase comparator 13 in the present embodiment
Activates the first lock determination signal g1 when the frequency is locked, while the second lock determination signal g1 is activated when the frequency is released.
That is, the lock determination signal g2 is activated.

Reference numeral 17 is a first switch which is closed when the first lock judgment signal g1 from the phase comparator 13 becomes active, 18 is an A / D converter, and 19 is a digital signal of the A / D converter 18. A data holding circuit for holding data, which constitutes the lock state storage circuit 20.

Further, 21 is a D / A converter to which the output of the data holding circuit 19 is given, and 22 is a second switch which is closed when the second lock judgment signal g2 from the phase comparator 13 becomes active. Therefore, these compose the lock state reproducing circuit 23.

When the PLL circuit of the present embodiment having the above configuration is in the frequency locked state, the phase comparator 13 causes the first comparator
The first lock determination signal g1 for the switch 17 is activated, while the second lock determination signal g2 for the second switch 22 is deactivated. This causes the first switch 17 to close and the second switch 22 to
Opens. When the first switch 17 is closed, the control voltage Vi applied from the phase comparator 13 to the voltage controlled oscillator 15 via the low pass filter 14 is also applied to the A / D converter 18. This A / D converter 18
Causes the value of the control voltage Vi when the frequency is locked to be digitized, and causes the data holding circuit 19 to hold the digitized value of the control voltage Vi.

When the frequency lock is released for some reason, the phase comparator 13 causes the first lock determination signal g for the first switch 17 contrary to the above frequency lock.
While making 1 inactive, the second lock judgment signal g2 for the second switch 22 is made active.
As a result, the first switch 17 is opened and the second switch 22 is closed. At this time, the D / A converter 21 receives the control voltage Vi from the data holding circuit 19 at the time of the frequency lock immediately before.
Data of the control voltage Vi is received, and the received data of the control voltage Vi is converted into an analog signal and applied to the control voltage line between the low pass filter 14 and the voltage controlled oscillator 15. Therefore, the voltage controlled oscillator 1 when the frequency lock is released
The fluctuation of the control voltage Vi to 5 is suppressed, and the PLL circuit returns to the frequency lock state within a short time.

When the frequency lock state is restored in this manner, the first lock determination signal g1 becomes active and the second lock determination signal g1 becomes active.
Lock decision signal g2 of each returns to inactive,
Both of the first and second switches 17 and 22 return to the states when the frequency is locked.

In the present embodiment, the A / D converter 18 holds the value of the control voltage Vi when the frequency is locked in the data holding circuit 19 in a digital format, so that the frequency is locked when compared to the analog format. It is easy to hold the information of the control voltage Vi.

[0016]

As described above, according to the present invention, the information on the control voltage to the voltage controlled oscillator at the time of frequency lock is held and the voltage control at the time of frequency lock is released based on the held information. Since the configuration for controlling the control voltage to the oscillator is adopted, the lock-up time can be shortened by suppressing the fluctuation of the control voltage when the frequency lock is lost.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional PLL circuit.

[Explanation of symbols]

 11 Crystal Oscillator 12 1 / N Frequency Divider (First Frequency Divider) 13 Phase Comparator 14 Low Pass Filter (LPF) 15 Voltage Controlled Oscillator (VCO) 16 1 / M Frequency Divider (Second Frequency Divider) 17 1st switch 18 A / D converter 19 Data holding circuit 20 Lock state memory circuit 21 D / A converter 22 Second switch 23 Lock state reproducing circuit e Phase error signals g1, g2 First and second lock Judgment signal

Claims (1)

[Claims] 1. A crystal oscillator for obtaining original oscillation, a first frequency divider for dividing the output of the crystal oscillator, and an output signal having an oscillation frequency according to a given control voltage. For controlling the output signal of the voltage controlled oscillator, a second frequency divider for dividing the output signal of the voltage controlled oscillator, and an output of the second frequency divider based on the output signal of the first frequency divider. A phase comparator for detecting a phase error of a signal and giving a control voltage corresponding to the phase error to the voltage controlled oscillator, and a lock for holding a value of the control voltage to the voltage controlled oscillator during frequency locking A state memory circuit; and a lock state reproducing circuit for receiving the value of the control voltage held by the lock state memory circuit when the frequency lock is released and applying the received control voltage to the voltage controlled oscillator. Having prepared A PLL circuit characterized by: