JPH0511724A - LCD drive circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In a liquid crystal display device that inputs display data from an external system and performs display, a drive circuit is configured on the glass substrate of the liquid crystal panel, and drive that enables cost reduction with a small number of parts Provide the circuit. [Structure] One line data shift means 110 for dividing display data 100 into a plurality of blocks for storage, one line data latch means 112, multiplexer 114 for outputting data in a time division manner, and data 115 for time division in a signal line 117. Can be composed of line data distribution means for distributing and outputting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a drive circuit for supplying display data input from the outside to each pixel portion to display an image.

[0002]

2. Description of the Related Art A conventional liquid crystal display device receives display data and an interface signal from the outside, converts the display data into a drive signal for the liquid crystal display device, and supplies the drive signal to a liquid crystal drive means such as Hitachi HD66107. In this case, the display data is captured by a given drive signal for each line in the horizontal direction of the screen, and the liquid crystal drive voltage corresponding to the captured display data is output to the liquid crystal panel to display an image. However, in the conventional driving means of the liquid crystal display device, for example, in the case of a personal computer type that performs color display in red, green and blue with a horizontal resolution of 640 dots,
There is a problem in that it is necessary to use twelve drive LSIs: HD66107, which increases the price of the entire display device.

A conventional liquid crystal display device will be described below with reference to FIGS.

FIG. 8 is a block diagram showing a conventional liquid crystal display device.

In FIG. 8, 100 is display data and 10 is display data.
Reference numeral 1 is a vertical synchronizing signal, 102 is a horizontal synchronizing signal, and 103 is a dot clock synchronized with the display data 100. In the present embodiment, since the display data 100 is handled as a color liquid crystal display device, the display data 100 is red (hereinafter abbreviated as R) data, green (hereinafter abbreviated as G) data, and blue (hereinafter abbreviated as B) data. Hold. Furthermore, these display data 10
0 has an arbitrary bit width, but in the present embodiment,
Each of R, G, and B is treated as display data having a one-bit width and a total of three-bit width. Reference numeral 800 is a data conversion unit, 801 is liquid crystal display data, 802 is a shift clock, 107 is a latch clock, and 108 is a vertical start enable signal. Reference numeral 803 denotes an X drive unit composed of HD66107. Of the X driving means 803, 804 is a data shift means, which fetches liquid crystal display data 801 for one line by a shift clock 802. 807 is data for one line shifted by the one-line data shift means 804. Reference numeral 806 denotes a one-line data latch means, which latches the data 805 with the latch clock 107. In the one-line data latch means 806, the liquid crystal applied voltage corresponding to the data to be latched is 640 (dots) × 3.
The signal is output from a total of 1920 signal lines of 807 (R, G, B). Reference numeral 118 is a Y driving means, and 119 is a scanning line.
120 is a liquid crystal panel.

FIG. 9 is a timing diagram showing the operation of the data converting means 800 in the block diagram of the liquid crystal display device shown in FIG.

In FIG. 9, the vertical synchronizing signal 10 shown in FIG.
Reference numeral 1 is a sync signal of one frame period, and horizontal sync signal 102 of (b) is a sync signal of one horizontal cycle, which has a repetition frequency much faster than that of the vertical sync signal 101. (C)
The dot clock 103 has a repetition frequency much faster than the horizontal synchronizing signal 102, and is the R data 100R of (d), which is the 3-bit data of the display data 100, (e).
G data 100G, and (f) B data 100B. With regard to the display data 100, in the present embodiment, the display data 100 is handled as a display with a horizontal resolution of 640 dots.
640, the G data 100G is sequentially G1, G2, ...
G640 and B data 100B are sequentially B1, B
2, ..., B640. The latch clocks 802 of (g) and (l) are clocks generated every time the X driving means 803 shown in FIG. 8 fetches the display data 100 for one horizontal line, and has the same frequency as the horizontal synchronizing signal 102. Note that (l) is described by reducing the time scale of (g). The shift clocks 802 in (h) and (m) are clocks for the X driving means 803 to sequentially take in the liquid crystal display data 801. Note that (h) is a reduced scale of the time scale of (m). The liquid crystal display data 801 is data having an 8-bit width in order to match the interface of the X driving means 803.
801A of (i) and (n) in sequence from the left side of
Data 801B of (j) and (o), ..., (k) and (p)
Corresponding data 801H. Then, D1, D2, ..., D240 are sequentially set in units of 8 bits. (I)
Is a time scale of (n), (j) is (o), and (k) is a scale of (p).

FIG. 10 is a timing chart showing the operations of the X drive means 803 and the Y drive means 118 of FIG.

In FIG. 10, the X drive means 803 is
In one cycle of the latch clock 107 of (a) and (d), the liquid crystal display data 801 of one line (b) and (e) and the shift clock 802 of (c) which is a capture clock synchronized with it are input. . Then, after the liquid crystal display data 801 for one line is fetched, the data for one line is simultaneously transferred to the signal line 807 in (f) for one cycle of the latch clock 107 in (f) by the latch clock 107 in (d). It is valid for a while. Vertical start enable signal 1 in (g)
Reference numeral 08 is a signal that determines the display start position in the vertical direction. When this signal is valid, Y-1 of the selection signal (h) of the horizontal line at the uppermost vertical direction of the scanning lines 119 is valid, and the latch clock 107 Each time, is enabled, the second line selection signal (i) Y-2 and the third line selection signal (j) Y-3 are sequentially selected.

FIG. 11 is a block diagram showing the internal structure of the liquid crystal panel 120 in the block diagram of the liquid crystal display device shown in FIG. Reference numeral 1100 denotes a display pixel portion, and each pixel portion 1100 has a thin film transistor (hereinafter abbreviated as TFT) 1101 which is a switching element, and 110.
It is composed of 2 liquid crystals and 1103 storage capacitors. Liquid crystal 110
2 and the storage capacitor 1103 are connected to the counter electrode. Further, each pixel unit 1100 is provided with R, G, and B color filters, and the pixel units 1100-1-1,
1100-1-2 has an R filter and a pixel unit 1100-
2-1, 1100-2-2 has a G filter,
100-3-1 and 1100-3-2 have a vertical stripe structure with a B filter.

Hereinafter, in order to explain the operation, FIG.
Refer to.

In FIG. 8, the R, G, B 1-bit serial display data 100 are 8-bit wide liquid crystal display data 80 of R, G, B mixed through the data converting means 800.
Converted to 1. The operation will be described in detail with reference to the timing chart of FIG. Since the horizontal resolution of the display screen is 640 dots as described above, the R data 100R is R1 to R640, the G data 100G is G1 to G640, and the B data 100B is B1 in the display data 100 during one period of the horizontal synchronizing signal 102. From 640 to B640, a total of 1920 pixels are transferred. Then, it is converted into liquid crystal display data 801. The conversion format of the display data depends on the specifications of the input interface of the X driving means 803 and the specifications of the pixel configuration of the liquid crystal panel 120. The X driving means 803 is an 8-bit parallel interface, and the signal lines 807 generated by the X driving means 803 correspond to eight lines, and the liquid crystal display data 8 shown in FIG.
The data 801A of (i) and (j) of 01 corresponds to the signal line on the left side of the screen, and the data 801H of (k) and (p) corresponds to the signal line 807 on the right side of the screen. Also, the liquid crystal panel 1
As shown in the block diagram of FIG. 11, reference numeral 20 has a configuration in which R, G, B color filters are sequentially arranged from the left side of the display screen. Therefore, the data conversion means 800 shown in FIG.
As shown in FIG. 9, the liquid crystal display data 801 generated in step (c) includes R1 data in (n) data 801A, G1 data in (o) data 801B, ..., G3 data in (p) data 801H. Output in synchronization with. Furthermore, in the next cycle of the shift clock 802,
B3 data is output to the data 801A of (n), R4 data is output to the data 801B of (o), ..., R6 is output to the data 801H of (p), and the (n) data 801A is output to the shift clock 802 at 240 cycles. G638 data,
(O) data 801B, B638 data, ..., (p)
B 640 is output to the respective data 801H.

Further, since the R, G, B 3-bit serial display data 100 is converted into the 8-bit liquid crystal display data 801, the shift clock 802 has a lower frequency than the dot clock 103.
2 can be easily generated by dividing the dot clock 103. Further, since the latch clock 107 has the same period as the horizontal synchronizing signal 102 and the vertical start enable signal 108 has the same period as the vertical synchronizing signal 101, both can be easily generated from the synchronizing signal.

Next, the operation of the X driving means 803 will be described in detail with reference to FIG. The X driving means 803 inputs the liquid crystal display data 801, the shift clock 802 and the latch clock 107 and outputs them to the signal line 807.

The liquid crystal display data 801 is transferred to the shift clock 8
At 02, one line is taken into the one line data shift means 804. The one-line data shift means 804 outputs the fetched data to the one-line data latch means 806 via the data 805. When the liquid crystal display data 801 for one line is taken in by the shift clock 802, the latch clock 107 becomes valid (hereinafter, the valid time is the “H” level, and the invalid time is the “L” level). One line is taken in at the same time,
Next, the latch clock 107 is held until it becomes the “H” level. When the data is fetched by the one-line data latch means 806, the one-line data shift means 804 operates so as to fetch the liquid crystal display data 801 of the next line. While the liquid crystal display data 801 on the second line is fetched by the shift clock 802 during one cycle of the latch clock 107, the liquid crystal applied voltage corresponding to the data on the first line is output to the signal line 807. Further, while the liquid crystal display data 801 on the third line is being fetched by the shift clock 802, the liquid crystal applied voltage corresponding to the data on the second line is output to the signal line 807. The X driving means 803 repeats this operation.

Next, the operation of the Y drive means 118 will be described with reference to FIG.
Description will be made in association with 0. The Y driving means 118 takes in the vertical start enable signal 108 and the latch clock 107 and sequentially selects the scanning lines 119. The vertical start enable signal 108 is a signal that enables selection of the uppermost vertical line of the liquid crystal panel 120 among the scanning lines 119, and the latch clock 107 is the sequential scanning lines 119.
Is a signal for selecting. The operation will be described with reference to FIG. When the liquid crystal applied voltage corresponding to the data on the first line of the signal line 807 is valid, the vertical start enable signal 108 becomes the “H” level, and the latch clock 1
In synchronization with 07, Y-1 of the scanning line 119 becomes the “H” level. Then, when the liquid crystal applied voltage corresponding to the data of the second line becomes effective on the signal line 807, the vertical start enable signal 108 is set to the “L” level, the latch clock 107 is set to the “H” level, and the scanning line 119 is
The scanning line Y-1 of the first line becomes the “L” level, and the scanning line Y-2 of the second line becomes the “H” level. The vertical start enable signal 108 is set to the “L” level state when selecting a line other than the first line. This operation is repeated for all lines in the vertical direction, and in the next frame, the vertical start enable signal 108 is made valid again and this operation is repeated.

Next, the operation of the liquid crystal panel 120 of FIG. 8 will be described with reference to FIG.
0 will be described with reference to FIG.

In FIG. 10, the liquid crystal panel 120 is R,
Display pixel unit 11 to which G and B color filters are added
00, a signal line 813 for supplying a liquid crystal applied voltage to the display pixel portion 1100, a scanning line 119 for selecting the display pixel portion 1100, and a counter electrode 1104 for the signal line 807. Further, the pixel portion 1100 is composed of a TFT 1101 which is a switching element, a liquid crystal 1102 and a storage capacitor 1103. Among the scanning lines 119, Y-1 is the pixel units 1100-1-1, 1100-2-1, 1 and 1 of the first line.
Y is added to the gate electrode of the TFT 1101 such as 100-3-1.
-2 is the pixel section 1100-1-2, 1100 of the second line
-2-2, 1100-3-2, etc. are connected to the gate electrode of the TFT 1101. X-1 of the signal line 807 is the TFT 110 of the pixel portions 1100-1-1, 1100-1-2, etc.
1 is a drain electrode, X-2 is a pixel portion 1100-2-1,
Drain electrode of the TFT 1101 such as 1100-2-2,
X-3 is connected to the drain electrodes of the TFTs 1101 of the pixel units 1100-3-1, 1100-3-2, etc., respectively.

As shown in FIG. 11, when the first scanning line Y-1 of the scanning lines 119 is in the "H" level state,
TFT 110 of each pixel unit 1100 connected to Y-1
1 is turned on. At the same time, the liquid crystal applied voltage corresponding to the data is supplied from the signal line 807, and the voltage is accumulated in the liquid crystal 1102 and the storage capacitor 1103 via the TFT 1101 which is in the ON state. At this time, the TFT 11 of each pixel portion connected to the scanning line 119 other than the scanning line Y-1
Since 01 is in the off state, the liquid crystal applied voltage supplied through the signal line 807 is applied to the liquid crystal 1102 and the storage capacitor 1103.
Never accumulate in. Since the liquid crystal 1102 has a property of tilting in one direction with respect to the applied voltage, the applied voltage is controlled, the tilt of the liquid crystal 1102 is changed, and display is performed depending on whether or not light is transmitted. Next, the scanning line Y-1 is'
When in the L'level state, the TFT 1101 is turned off, and the previously accumulated voltage is held until the TFT 1101 is turned on again. Also, the scanning line Y-1
Becomes the “L” level state, the second scanning line Y-2 of the scanning lines 119 becomes the “H” level state, and Y−
The TFT 1101 of each pixel portion 1100 connected to 2 is turned on. At the same time, the liquid crystal applied voltage corresponding to the data is supplied from the signal line 807, and the liquid crystal 1102 and the storage capacitor 1 are passed through the TFT 1101 which is turned on.
The voltage is stored in 103. At this time, the TFT 1 of each pixel portion 1100 connected to the scanning line 119 other than the scanning line Y-2
Since 101 is in the off state, the liquid crystal applied voltage supplied by the signal line 807 is not stored in the liquid crystal 1102 and the storage capacitor 1103. The display is performed by sequentially repeating this operation on the line.

[0020]

In the conventional liquid crystal display device, it is necessary to form the X driving means by a plurality of LSIs. For example, in the case of Hitachi HD66107, if the horizontal resolution is 640 dots, the signal line is (6
40 (dots) × 3 (RGB) =) 1920 lines are required, and the HD 66107 having 160 signal line outputs needs to use 12 lines. When a plurality of driving LSIs are used, there are problems that the price of the entire liquid crystal display device becomes high and that the driving means of the entire liquid crystal display device occupies a large area. In order to solve these problems, it is necessary to provide a driving unit that employs a system that can be driven with a small number of parts.

[0021]

In order to realize a driving LSI used for X driving means with a small number of parts, a driving LS is required.
It is necessary to drive 1920 signal lines while suppressing the signal lines output by I. That is, the driving means can be integrated by providing a means for expanding a small number of input signal lines to 1920 signal lines on the glass substrate of the liquid crystal panel.

Means for solving the first problem are storage means for temporarily storing and outputting display data for one horizontal line, and means for time-division and outputting the stored data into a plurality of pieces.
A means is provided for distributing and outputting the data to be time-division transferred to the corresponding signal lines of the liquid crystal panel. Either the storage means or the time-division output means or any one of them is integrated, and means for distributing and outputting the data to be transferred in the time-division manner to corresponding signal lines is formed on the glass substrate of the liquid crystal panel.

A means for solving the second problem is that the storage means for temporarily storing and outputting the display data for 1 / N horizontal lines and the liquid crystal panel for the display data for 1 / N horizontal lines. And a means for distributing and outputting the signal to the corresponding signal line. The storage means is integrated, and means for distributing and outputting the signal lines is formed on the glass substrate of the liquid crystal panel.

[0024]

In the means for solving the first problem, the means for temporarily storing the display data for one horizontal line can simultaneously output the display data for one horizontal line as parallel data.

Since the parallel data to be input is data for one horizontal line, the time-division output means has a structure of means for distributing the time-division data to corresponding signal lines of the liquid crystal panel and outputting the data. The number of data lines can be converted to be smaller than the number of corresponding signal lines of the liquid crystal panel.

The means for inputting the time-divided data, distributing it to the corresponding signal lines of the liquid crystal panel, and outputting it distributes the time-division data transferred by the data lines to all the signal lines of the liquid crystal panel,
Output is possible during one horizontal period, and data transfer from the signal line to the pixel portion operates similarly to the conventional liquid crystal display device.

In the means for solving the above-mentioned second problem, the means for temporarily storing the display data for 1 / N horizontal lines is divided into N horizontal times for one horizontal period, and sequentially divided by 1 / N horizontal lines. It is possible to simultaneously output the display data of as parallel data.

The means for inputting the time-divided data, distributing it to the corresponding signal lines of the liquid crystal panel and outputting it distributes the time-division data transferred by the data lines to all the signal lines of the liquid crystal panel,
Output is possible during one horizontal period, and data transfer from the signal line to the pixel portion operates similarly to the conventional liquid crystal display device.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of a liquid crystal display device using the liquid crystal drive circuit of the present invention.

In FIG. 1, 100 is display data and 10 is display data.
Reference numeral 1 is a vertical synchronizing signal, 102 is a horizontal synchronizing signal, and 103 is a dot clock synchronized with the display data 100. In the present embodiment, since the display data 100 is handled as a color liquid crystal display device, the display data 100 includes a red signal (hereinafter abbreviated as R), a green signal (hereinafter abbreviated as G), and a blue signal (hereinafter, abbreviated as G).
Abbreviated as B. ). Further, although each of these display data has an arbitrary bit width, in the present embodiment, R, G, B
Handled as display data with a total width of 1 bit each, for a total of 3 bits. Reference numeral 104 is a data conversion means, 105 is first liquid crystal display data, 106 is a shift clock, 107 is a latch clock, 108 is a vertical start enable signal, 1
Reference numeral 09 is a line data selection signal. Reference numeral 110 is a data shift means, and in this embodiment, 110-1 to 110-.
The area is divided into six blocks of six. Reference numerals 111-1 to 111-6 are second liquid crystal display data, which are output from respective areas of the one-line data shift means 110. The liquid crystal display data 111-1 to 111-6 are (640
(Horizontal resolution) × 3 (RGB) ÷ 6 (block) =) 3
It is 20-bit wide parallel data. Reference numerals 112-1 to 112-6 are data latch means, and 113-1 to 113-6 are third liquid crystal display data each having a 320-bit width. Reference numeral 114 denotes a multiplexer, which selects the third liquid crystal display data 113 divided into six in a time division manner,
The fourth liquid crystal display data of No. 5 is output. Reference numeral 116 denotes a line data distribution means, which sequentially stores the six time-divided fourth liquid crystal display data 115 and outputs them simultaneously to the signal line 117. Reference numeral 118 is a Y driving means, and 119 is a scanning line. 120 is a liquid crystal panel.

FIG. 2 is a block diagram of the line data distribution means 116 shown in FIG.

In FIG. 2, the six line data selection signals 119 are 119-1, 119-2, 119-3, and 1.
19-4, 119-5 and 119-6. Reference numeral 200 is a sample and hold means for sampling the input liquid crystal display data 111, temporarily storing it, and outputting it simultaneously.
The line data distribution means 116 is provided with 320 sample hold means 200. (2 in Figure 2
Only 00-1, 200-2, 200-3 are described. ) Each sample hold means 200 has a liquid crystal display data 115.
One of them is shared by adjacent pixel data, and the pixel data is distributed to the six signal lines 117. 201 is a switching element of the sample hold means 200 for sampling the input signal, and 202 is a hold means for temporarily storing the input signal. The holding means 202 can be composed of a capacitor. The stored data is transferred by the data line 203. 204 is a counter electrode of the holding means 202. Reference numeral 205 is a switching element for simultaneously outputting the data temporarily stored in the holding means 202 to the signal line 117. A holding unit 206 holds the data output to the signal line 117 during one horizontal period. The holding means 206 can be composed of a capacitor.

FIG. 3 shows an example of the liquid crystal display device shown in FIG.
Data conversion means 104, one-line data shift means 11
FIG. 6 is a timing chart showing the operations of 0, 1 line data latch means 112 and multiplexer 114.

In FIG. 3, the horizontal synchronizing signal 10 shown in FIG.
Reference numeral 2 is a signal that becomes valid once in one horizontal period (hereinafter, "H" level when valid and "L" level when invalid).
The dot clock 103 in (b) is (c), (d),
It is synchronized with the display data 100 of (e). In the present embodiment, the red signal 100 of (c) which is the display data 100.
R, the green signal 100G of (d) and the blue signal 100B of (e) each have a horizontal resolution of 640 dots on the display screen, and the red signal 100R of (c) is displayed during the horizontal period.
, R640 in sequence, and the green signal 100G in (d) is G1, G2, ..., G640 in sequence.
The blue signal 100B of (e) is B1, B2, ..., B in order.
640 are transferred for each 640 pixels, for a total of 1920 pixels. The latch clock 107 in (f) has the same frequency as the horizontal synchronizing signal 102 in (a), and can be easily created from the horizontal synchronizing signal 102. The shift clock 106 in (g) is a clock having a frequency half that of the dot clock 103 in (b), and the 3-bit width display data 100 is parallelized to the 6-bit width first liquid crystal display data 105. .
(H) The data 105R1 is the odd pixel data R of R
1, R3, ..., R639 are converted to the data 105R2 of (i).
, R even and odd pixel data R2, R4, ..., R640
In the data 105G1, odd-numbered pixel data G1, G1
, ..., G639, the data 105G2 is G even pixel data G2, G4 ,.
1 is odd-numbered pixel data B of B1, B3, ..., B639.
, And the even pixel data B2, B4, ..., B640 of B are transferred to the data 105B2 of (j). (Data 105
Not shown are G1, data 105G2, and data 105B1. ) (L) (m) (n) is the shifted second liquid crystal display data 111. Note that (h) and (o) are the latch clocks 10 described by reducing the time scale of (f).
7 (P) (q) (r) is the third liquid crystal display data 113 synchronized with the latch clock 107 of (o). (S) (t) (u) (v) (w) (x) are line data selection signals 119-1 to 119-6. (Y)
Is the fourth liquid crystal display data 1 for time-division data transfer
Output to 15 in time division. Liquid crystal display data 105 of (y)
D1 changes the data 113R1 of (p) to D1 during one horizontal period.
The data 113R2 of (q) to D2 and the data 113
G1 to D3, data 113 G2 to D4, data 11
3B1 is output to D5 and (r) data 113B2 is output to D6. (Data 113G1, 113G2, 113B1
Is not shown. 4) FIG. 4 is a timing chart showing the operation of the line data distribution means 116 shown in FIG. In addition, in order to simplify the description, the sample hold means 200-1
Although only described, the operation timing is the same for other sample and hold means.

In FIG. 4, the line data selection signal 119-1 in (a) is the fourth liquid crystal display data 11 in (g).
5 is synchronized with D1 and (b) 119-2 is synchronized with D2.
119-3 in (c) is D3, and 119-4 in (d) is D.
4, (e) 119-5 is D5, and (f) 119-.
6 is synchronized with D6. (H) to (m) are the held data 203-1 to 203-6. And
The data from (o) to (t) are output at the same time in synchronization with the line data selection signal 119-6 shown in (n).
17-1 to 117-6.

Hereinafter, FIG. 1 will be referred to again in order to explain the operation.

In FIG. 1, the R, G, B 1-bit serial display data 100 is converted into R, G, B 2-bit parallel liquid crystal display data by a data conversion means 104. The operation will be described with reference to the timing chart of FIG. In the display data 100, (c) R data 100R, (d) G data 100G, (e) B data 100B, even-pixel data, and odd-pixel data are separated from each other by serial / parallel conversion. 1
02 and the shift clock 106 of (g). That is, of the first liquid crystal display data 105, odd pixel data R1, R3, ..., R637, R639 of the R data 100R are included in the liquid crystal display data 105R1 of (h), and R data is included in the liquid crystal display data 105R2 of (i). , R638, R640, the odd pixel data G1, G3, ..., G637, G639 of the G data 100G, and the liquid crystal display data 105G2 the even pixel of the G data 100G. Data G2, G4, ..., G638, and G640 are added to the liquid crystal display data 105B1 as odd pixel data B of B data 100B.
, B637, B639, the even pixel data B2, B4, ..., B638, B640 of the B data 100B are transferred to the liquid crystal display data 105B2 of (j).
(Liquid crystal display data 105G1, 105G2, 105B1
Is not shown. It can be seen that the liquid crystal display data 105 is synchronized with the shift clock 106.

In FIG. 1, the data shift means 110
Captures the liquid crystal display data 105 with the shift clock 106. The data shift means 110R1 is the liquid crystal display data 105R1, the data shift means 110R2 is the liquid crystal display data 105R2, the data shift means 110G1 is the liquid crystal display data 105G1, and the data shift means 110G2 is the liquid crystal display data 105G2 and the data shift means 110B1.
Is liquid crystal display data 105B1 and data shift means 110
B2 operates so as to fetch the liquid crystal display data 105B2. The data that has been taken in is the data shift means 11
The data is output as parallel second liquid crystal display data 111 each having a width of 0 to 320 bits. In FIG. 3, liquid crystal display data 111R1 is shown in (l) and liquid crystal display data 1 is shown in (m).
11R2, (n) shows the timing of the liquid crystal display data 111B2. (Liquid crystal display data 111G1, 111G
2, 111B1 is not shown. ) In order to simplify the following description, they are collectively referred to as D1, D2, ..., D6.

In FIG. 1, the data latch means 112 simultaneously latches data for one horizontal line in synchronization with the latch clock 107, and aligns data on the same horizontal line. The latch means 112R1 is the liquid crystal display data 1
11R1 and the latch means 112R2 are the liquid crystal display data 1
11R2, the latch means 112G1 is the liquid crystal display data 1
11G1 and the latch means 112G2 are the liquid crystal display data 1
11G2, the latch means 112B1 is the liquid crystal display data 1
11B1 and the latch means 112B2 is the liquid crystal display data 1
11B2 are each latched. The operation is shown in FIG.
The latch clock 107 of (o) is a signal that becomes effective in each horizontal period, and latches the liquid crystal display data 111 of (l), (m), and (n) to obtain the third liquid crystal display data 113. The liquid crystal display data 111R1 of (l) is the liquid crystal display data 113R1 of (p), the liquid crystal display data 111R2 of (m) is the liquid crystal display data 113R2 of (q),
The liquid crystal display data 111B2 of (n) becomes the liquid crystal display data 113B2 of (r). This operation is sequentially repeated.

Each liquid crystal display data 113 of FIG. 1 is input to the multiplexer 114 and the line data selection signal 1 is input.
09, one horizontal period is time-divided into six and sequentially output. In the present embodiment, the line data selection signal 109 is composed of six signals, each of which is effective by shifting the phase. The operation of the multiplexer 114 is shown in FIG. The line data selection signal 109 is (s) (t) (u)
(V) (w) (x) 109-1 to 109-6 in total, and at (s) 109-
After sequentially validating from 1 and validating 109-6 of (x), this operation is repeated from 109-1 of (s) again in the next one horizontal period. Then, in each data line selection signal 109, the corresponding liquid crystal display data 113
Is output to the fourth liquid crystal display data 115 of (y). That is, (p) of the liquid crystal display data 113
113-1 of (s) is changed to 113R1 of 113 of 113 (q).
109-2 of (t) selects R2, and 109-6 of (x) selects 113B2 of (r), and sequentially makes D1 to D6 valid during one horizontal period. In addition, the fourth liquid crystal display data 11
Since 5 is time-division controlled, it becomes parallel data having a width of 320 bits.

In FIG. 1, the fourth liquid crystal display data 11
5 is input to the line data distribution means 116, and the signal line 11
It operates so as to simultaneously output 7 to 1920 lines. The operation of the line data latch means 116 will be described with reference to FIGS. 2 and 4.

In FIG. 2, sample hold means 200
Then, the fourth liquid crystal display data 115 are respectively given as X-1, X-
Input from 2 etc., and are commonly connected to the input lines of the six switching elements 201. Further, the six switching elements 201 have corresponding line data selection signals 119.
Enter individually. Liquid crystal display data 1 input in time division
Line data selection signal 1 in which 15 is synchronized with each data
19 are sequentially activated, and six switching elements 201
Are sequentially turned on, and temporarily stored in the holding means 202 via the data line 203. To simplify the description, the operation of the sample hold means 220-1 will be described with reference to FIG. Line data selection signals 119-1 to 119-6 of (a) to (f) latch the data input from the signal line 115 of (g) in a time division manner.
The line data selection signal 119-1 in (a) is D1 valid on the signal line 115 in (g), the line data selection signal 119-2 in (b) is D2, and the line data selection signal 119- in (c). 3 is D3, (d) line data selection signal 119-4 is D4, (e) line data selection signal 1
19-5 designates D5 as the line data selection signal 11 of (f).
9-6 latches D6, and each (h) data line 203
-1, data line 203-2 of (i), data line 203-3 of (j), data line 203-4 of (k), data line 203-5 of (l), data line 203 of (m). Output to -6.

Returning to FIG. 2, the data valid on the data line 203 is connected to the input line of the switching element 205, and the line data selection signal 119-6 which is the selection signal of the switching element 205 is valid. Then, the switching element 205 is turned on, stored in the holding means 206, and simultaneously output from the signal line 117. The operation will be described with reference to FIG. The timing when the data for the same horizontal line is aligned on each data line 203 is when the line data selection signal 119-6 is valid, so data for one line is aligned at this timing and output to the signal line 117. It will be. (H)
The data 203-1 of is the data 117-1 of (o),
The data 203-2 of (i) is the data 117-2 of (p)
In addition, the data 203-3 of (j) is the data 117 of (q)
-3, the data 203-4 of (k) is the data 1 of (r)
17-4, (l) data 203-5 is output to (s) data 117-5, and (m) data 203-6 is output to (t) data 117-6. The output data is held until the (n) line data selection signal 119-6 becomes valid again. Then, the image is output to the liquid crystal panel 120 shown in FIG. 1 to display an image. In the present embodiment, in the sample hold means 200 of the line data distributing means 116 shown in FIG. 2, one data line is distributed to six signal lines, so the data shift means 11 shown in FIG.
0 and the data latch means 111 are divided into six blocks to process the data, but when the number of samples to be distributed by the sample hold means 200 shown in FIG. 2 increases, the data shift means 110 shown in FIG. Latch means 111
This can be dealt with by increasing the number of blocks to be divided.

Here, the data conversion means 10 shown in FIG.
4, data shift means 110, data latch means 11
2, multiplexer 114, line data distribution means 11
It is also possible to construct any one of the six on the glass substrate of the liquid crystal panel, and to integrate a plurality of means.

Another embodiment of the present invention is shown in FIGS.
Will be explained.

FIG. 5 is a block diagram of a liquid crystal display device using the liquid crystal drive circuit of the present invention.

In FIG. 5, reference numeral 500 is a data conversion means, 501 is first liquid crystal display data, 502 is a shift clock, 503 is a 1 / N line data latch clock, and 504 is a line data selection signal. 505 is 1
/ N line data shift means, and liquid crystal display data 5
01 is taken in by the shift clock 502. In this embodiment, N = 6 will be taken as the basis of the discussion. 506 is the second liquid crystal display data, which is (640 (horizontal resolution) × 3 (RGB) ÷ 6
(1/6 line data) =) 320-bit wide parallel data. Reference numeral 507 is a 1 / N line data latch means, and 508 is third liquid crystal display data. The liquid crystal display data 508 is also parallel data having a width of 320 bits. 509 is line data distribution means, and 510 is 1
There are 920 signal lines.

FIG. 6 is a block diagram of the line data distribution means 509 shown in FIG.

In FIG. 6, line data selection signal 50
4 is composed of six signals 504-1 to 504-6. The third liquid crystal display data 508 is from 508-1 to 50.
It is composed of 320 signals of 8-320. 600 is a switching element, which is the total number of signal lines 510 600
The minimum number of 1920 is -1 to 600-1920. A data line 601 transfers the output data of each switching element 600. Reference numeral 602 denotes a holding unit, which can be configured by a capacitor. 603 is a holding means 6
02 counter electrode. Reference numeral 604 is a switching element, and 605 is holding means for holding data for one horizontal period. The signal lines 510 are 510-1 to 510-192.
It is composed of 1920 signals of 0.

FIG. 7 is a timing chart showing the timing of the input signal of the data conversion means 500 of the liquid crystal display device of FIG. 5 and the internal operation of the line data distribution means 509 shown in FIG. (A) and (f) are horizontal synchronization signals 102,
(F) is a time scale of (a) reduced. (G) is 1 / N line data latch clock 503
That is, the display data for one horizontal portion is time-divided into six pieces. (H) is the third liquid crystal display data 508 time-divided into six. The line data selection signals 504-1 to 504-6 of (i) to (n) are synchronized with each of the six time-divided liquid crystal display data 508. In order to simplify the explanation, data lines 604-1, 604-321, 604- for performing data transfer are shown from (o) to (t).
641, 604-961, 604-1281, 604-
Only the operation of 1601 is shown. Furthermore, from (u) to (z)
Are signal lines 510-1 and 510-32 for transferring data synchronized with the line data selection signal 504-6 of (n).
1, 510-641, 510-961, 510-128
The operation of No. 1, 510-1601 is shown.

Hereinafter, FIG. 5 will be referred to again in order to explain the operation.

In FIG. 5, the R, G, B 1-bit serial display data 100 are mixed with the liquid crystal display data 5 of a plurality of bit widths of R, G, B mixed through the data converting means 104.
Is converted to 01. The bit width to be converted is caused only by the speed of the shift operation of the 1 / N line data shift means, that is, the operating frequency of the shift clock 502 is
It is set to be lower than the shift frequency of the 1 / N line data shift means 505. First liquid crystal display data 501
Are sequentially taken into the 1 / N line data shift means 505 by the shift clock 502 and output as the second liquid crystal display data 506 which is parallel data having a width of 320 bits. In the 1 / N line data latch means 507, the 1 / N line data latch clock is generated at the timing when 1/6 of the display data for one horizontal line, that is, 320 pixels of data are arranged in the second liquid crystal display data 506. 503 becomes the “H” level. This operation will be described with reference to FIG. (F) 1 / N line data latch clock 503 of (g) during one cycle of the horizontal synchronizing signal 102
Is synchronized with the second liquid crystal display data 506 and becomes the “H” level six times. Then, (h) the third liquid crystal display data 5
It outputs to 08 in time division.

Line data distribution means 509 in FIG.
The operation will be described with reference to FIGS. 6 and 7. In FIG.
The signal line 508-1 is a switching element 600-1, 60.
0-7, ..., 600-1915 are input at 6-pixel intervals. Similarly, the signal line 508-2 is the switching element 600.
-2, 600-8, ..., 600-1916 to the signal line 5
08-6 is a switching element 600-6, 600-1
6, ..., 600-1920. Further, the line data selection signal 504-1 is the switching element 600-1,
, 600-320, the line data selection signal 504-2 indicates the switching elements 600-321, 6-.
00-322, ..., 600-640, the line data selection signal 504-6 is the switching element 600-160.
1, 600-1602, ..., 600-1920. When the data corresponding to the switching elements 600-1 to 600-320 is input as the third liquid crystal display data 508, the line data selection signal 504-1 becomes valid, and the switching elements 600-1 to 600-320 are turned on. The data lines 601-1 to 601-become in the ON state.
Hold means 602-1 to 602-via 320
It is temporarily stored in 320. Next, in the third liquid crystal display data 508, the switching elements 600-321 to 600
When the data corresponding to −640 is input, the line data selection signal 504-2 becomes valid, the switching elements 600-321 to 600-640 are turned on, and the data lines 601-321 to 601-640 are routed. Then, they are temporarily stored in the holding means 602-321 to 602-640. This operation is repeated and temporarily stored in all the holding means 602. When the data for one horizontal line is processed in the above operation, the line data selection signal 504-
All the switching elements 604 connected to 6 are turned on and output to the signal line 510 at the same time. Further, at this time, since the data equivalent to the data output to the signal line 510 is stored in all the holding means 605, until the switching element 604 is turned on again, that is,
The same data is output from the signal line 510 during one horizontal period. While the switching element 604 and the holding means 605 are performing the data alignment processing, the switching element 600 and the holding means 602 perform the above-described processing on the data of the next line. This operation will be described with reference to FIG. LCD display data 5 of (h)
(I) line data selection signal 504 transferred at 08
The data corresponding to -1 is output to the data line 604-1 of (o). Similarly, the data corresponding to the line data selection signal 504-2 of (j) is similarly input to the data line 604 of (p).
-321 to the (k) line data selection signal 504-3.
The data corresponding to the (q) data line 604-641
Data corresponding to the line data selection signal 504-4 of (l) to the data line 604-961 of (r), (m)
Data corresponding to the line data selection signal 504-5 of (s) on the data line 604-1281, and data corresponding to the line data selection signal 504-6 of (n) on the data line 604-1601 of (t). Output. Then, the same operation is repeated on and after the next line. Then, when the data for one line is aligned on the data line 604, that is, when the line data selection signal 504-6 becomes the “H” level, the data line 604-1 of (o) is the signal line of (u). 5
10-1, (p) data line 604-1 to (v) signal line 510-1, (q) data line 604-1 to (w) signal line 510-1, and (r). Data line 604
-1 is the (x) signal line 510-1, the (s) data line 604-1 is the (y) signal line 510-1, and the (z) data line 604-1 is the (u) signal. Output to line 510-1. Again, when the line data selection signal 504-6 becomes valid, the data of the next line becomes valid for one horizontal period,
By repeating this, display is performed on the liquid crystal panel 120 of FIG.

Here, the data conversion means 50 shown in FIG.
0, 1 / N line data shift means 505, 1 / N line data latch means 507, line data distribution means 11
It is also possible to construct any one of the six on the glass substrate of the liquid crystal panel, and to integrate a plurality of means.

[0056]

According to the present invention, the switching element and the holding means in the line data distributing means can be formed in a small space on the glass substrate like the TFT and the holding capacitor in the liquid crystal panel.

Further, the driving means is divided into the data storage means and the data distribution means, and the data to be transferred is time-divided, so that the bus width for transferring the data can be made smaller than the signal line of the liquid crystal panel. The means can be easily integrated, and the drive circuit of the liquid crystal display device can be configured with a small circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display device using an embodiment of the present invention,

FIG. 2 is a block diagram of the line data distribution unit shown in FIG.

FIG. 3 is a timing diagram showing the operation of the data conversion means shown in FIG.

FIG. 4 is an operation explanatory diagram of the line data distribution unit shown in FIGS. 1 and 2.

FIG. 5 is an explanatory view of a liquid crystal display device using an embodiment of the present invention,

6 is a block diagram of the line data distribution unit shown in FIG.

7 is a timing chart showing the operation of the liquid crystal display device shown in FIG.

FIG. 8 is a block diagram of a conventional liquid crystal display device,

9 is a timing chart showing the operation of the data conversion means shown in FIG.

10 is a timing chart showing the operation of the X drive means and the Y drive means shown in FIG.

11 is a block diagram of the liquid crystal panel shown in FIG.

[Explanation of symbols]

100 ... Display data, 103 ... Dot clock, 104
... data conversion means 105 ... first liquid crystal display data, 1
06 ... shift clock, 107 ... latch clock, 11
0 ... Data shift means, 111 ... Second liquid crystal display data, 112 ... Data latch means, 113 ... Third liquid crystal display data, 114 ... Multiplexer, 115 ... Fourth liquid crystal display data, 116 ... Line data distribution means, 117
... signal line, 118 ... Y driving means, 119 ... scanning line, 12
0 ... Liquid crystal panel.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Naruhiko Kasai             Hitachi, Ltd., 292 Yoshida-cho, Totsuka-ku, Yokohama-shi             Manufacturing Microelectronics equipment development             In the laboratory (72) Inventor Isao Takita             Hitachi, Ltd., 292 Yoshida-cho, Totsuka-ku, Yokohama-shi             Manufacturing Microelectronics equipment development             In the laboratory (72) Inventor Toshio Futami             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Sakusho Mobara Factory

Claims (6)

[Claims] 1. A liquid crystal display device which has an electrode for driving liquid crystal in a pixel portion arranged in a matrix form and which displays an image by applying a voltage to the liquid crystal, and displays data for every horizontal line from the outside. Means for simultaneously outputting one horizontal line to the first signal line after inputting and storing the data, and N data for one horizontal line transferred by the first signal line.
Means for dividing and time-divisionally outputting to the second signal line each display data for 1 / N horizontal lines, and data for transferring by the second signal line for each 1 / N line data Means for storing data for one horizontal line, and means for simultaneously outputting data for one horizontal line to the third signal line, and a pixel for applying a voltage corresponding to the image data to the third signal line. A drive circuit for a liquid crystal display device, which is supplied to a liquid crystal display device. 2. A means for inputting display data for every one horizontal line from the outside from the outside and storing it, and then simultaneously outputting for one horizontal line to a first signal line, and said first signal. Data for one horizontal line to be transferred by line is divided into N, and is output to the second signal line by means of time division output for each 1 / N horizontal line of display data, and is transferred by the second signal line. One of a means for storing data for each 1 / N line data and a means for storing one horizontal line data and then simultaneously outputting one horizontal line data to the third signal line. A drive circuit for a liquid crystal display device that integrates 3. A means for inputting display data for each horizontal line for one horizontal line from the outside and storing the display data, and then simultaneously outputting the display data for one horizontal line to the first signal line, Means for dividing the data for one horizontal line transferred by the first signal line into N and outputting to the second signal line for each 1 / N horizontal line of display data in a time-division manner; Means for storing data to be transferred by line for each data of 1 / N line, and after storing data for one horizontal line,
A drive circuit for a liquid crystal display device, which forms one of data for one horizontal line on a third signal line at the same time on a glass substrate of a liquid crystal panel 4. A liquid crystal display device which has electrodes for driving liquid crystal in a pixel portion arranged in a matrix form and which displays an image by applying a voltage to the liquid crystal, receives display data from the outside, and displays it horizontally. The display data for one line is divided into N parts and stored for each data for 1 / N horizontal lines, and then the display data for 1 / N line is simultaneously output to the first signal line; The data transferred by the signal line is 1 /
A means for storing data for each N lines, a means for storing data for one horizontal line and then simultaneously outputting to a second signal line, and a voltage corresponding to display data on the second signal line. A driving circuit for a liquid crystal display device, which is supplied to a pixel portion. 5. The display data according to claim 4, wherein the display data is input from the outside and the display data for one horizontal line is divided into N,
Means for simultaneously outputting 1 / N line of display data to the first signal line after storing for every N horizontal lines of data, and 1 / N line of data transferred by the first signal line. The driving circuit of the liquid crystal display device, which integrates either the means for storing the data for each of the data and the means for storing the data for one horizontal line and then simultaneously outputting the data to the second signal line. 6. The display data according to claim 4, wherein the display data is input from the outside and the display data for one horizontal line is divided into N and 1 /
Means for simultaneously outputting 1 / N line of display data to the first signal line after storing for every N horizontal lines of data, and 1 / N line of data transferred by the first signal line. A liquid crystal display device in which either one of the data storing means for storing each data and the means for simultaneously storing the data for one horizontal line and then outputting to the second signal line, or one of them is formed on the glass substrate of the liquid crystal panel. Drive circuit.