JPH05110097A - Thin film mos type transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent punch-through of thin film MOS transistor (TFT). In a reverse staggered TFT, the gate electrode is concave so that the channel of the TFT crosses the concave step of the gate electrode, and the thickness of the step of the gate electrode is used as the channel to reduce the planar dimension. It is possible to secure a channel length that does not cause punch-through even if it is made into a material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a thin film MOS transistor.

[0002]

2. Description of the Related Art Thin film MOS type transistors (Thin
Film Transistor TFTs) are widely used in highly integrated SRAMs and liquid crystal panels.
The conventional structure will be described with reference to FIG. FIG. 3 shows an inverted staggered P-channel TFT, where 301 is a P-type silicon substrate, 302 is a silicon oxide film, 303 is a gate electrode of a TFT made of an N-type polycrystalline silicon film, and 304 is a TFT made of a silicon oxide film. Gate oxide film, 305, 3
Reference numerals 06 and 307 are TFT bulks made of a polycrystalline silicon film, and reference numerals 305 and 306 are TFs into which a P-type impurity is introduced.
A source / drain region of T and a channel region 307 of the TFT.

In FIG. 3, 0 is assigned to the source 305 of the TFT.
V, drain 306 with -5V added, gate electrode 30
When -5V is applied to 3, the TFT turns on and a current flows between the source and drain. Next, when the gate electrode is set to 0V, the TFT is turned off and no current flows between the source and drain.

[0004]

However, in the conventional TFT, when the channel length L is shortened in order to miniaturize the TFT, a punch-through phenomenon occurs in which a current flows between the source and the drain even if the gate electrode is 0V. It had the problem of getting up.

An object of the present invention is to solve such a problem, and an object of the invention is to provide a TFT which does not cause punch through even if it is miniaturized.

[0006]

A thin film MOS transistor according to the present invention comprises a first insulating film provided on a semiconductor substrate and a first conductive film provided on the first insulating film. A thin film MOS transistor including a gate electrode of a thin film MOS transistor, a second insulating film provided on the gate electrode of the thin film MOS transistor, and a first semiconductor film provided on the second insulating film. Inverted staggered thin film MO consisting of source, drain and channel regions
In the S-type transistor, the gate electrode of the thin film MOS transistor is concave, and the channel region of the thin film MOS transistor exists across the concave gate electrode.

In the thin film MOS type transistor of the present invention, the thickness of the step of the recess of the gate electrode of the thin film MOS type transistor made of the first conductive film corresponds to the channel region of the thin film MOS type transistor made of the first semiconductor film. It is characterized by being thicker than the film thickness.

In the thin-film MOS transistor of the present invention, the gap between the steps of the gate electrode of the concave thin-film MOS transistor made of the first conductive film is the channel region of the thin-film MOS transistor made of the first semiconductor film. It is characterized in that it is wider than twice the thickness.

The thin-film MOS transistor of the present invention is characterized in that the first conductive film is a polycrystalline silicon film.

The thin film MOS transistor of the present invention is characterized in that the first conductive film is a refractory metal polycide film.

The thin film MOS transistor of the present invention is characterized in that the first conductive film is a refractory metal film.

[0012]

EXAMPLE An example of the present invention will be described with reference to FIG. 1
01 is a P-type silicon substrate, 102 is a silicon oxide film, 1
Reference numerals 03 and 104 denote a gate electrode of a TFT made of an N-type polycrystalline silicon film, 105 a gate oxide film of a TFT made of a silicon oxide film, 106, 107, 109 and 110 a bulk of the TFT made of a polycrystalline silicon film. 11
Reference numeral 0 is a source / drain region of the TFT in which a P-type impurity is introduced, and 107 and 109 are channel regions of the TFT.

Next, the manufacturing method of the present invention will be described with reference to FIG. First, as shown in FIG. 2A, the P-type silicon substrate 2
01 onto the silicon oxide film 202 by LPCVD.
000Å and then LPC on the silicon oxide film 202.
The VD method was used to remove the polycrystalline silicon film to 2000 at 620 ° C.
Å Form. Subsequently, P + ions are implanted at 45 KeV and 5 × 10 ¹⁵ to form an N-type polycrystalline silicon film. Next, a pattern of the gate electrode is formed on the N-type polycrystalline silicon film by photolithography, and then reactive ion etching is performed to perform TF as shown in FIG.
The T gate electrodes 203 and 204 are formed. At that time, the pattern of the gate electrode is in the shape of two or more islands as shown in FIG. 2 (b), and reactive ion etching is performed in time without etching to the end point, and the polycrystalline silicon film is etched to 1000 Å When etching is completed, stop etching. Next, as shown in FIG. 2C, TEOS "S is formed on the gate electrodes 203 and 204 and on the side surfaces.
A silicon oxide film 205 of 400 Å is formed by the LPCVD method using i (OC ₂ H ₅ ) ₄ ″ and O ₃ , and then an amorphous silicon film is formed on the silicon oxide film 205 by the LPCVD method using Si 2 H 6 gas at 480 ° C. Then, 400 Å is formed, and then annealing is performed in an N ₂ atmosphere at 600 ° C. for 20 hours to form an amorphous silicon film by solid phase growth to form a polycrystalline silicon film having a grain size of 0.5 μm or more. T on the polycrystalline silicon film
After forming a bulk pattern consisting of FT source, drain, and channel regions, reactive ion etching is performed to form a TFT bulk. At that time, TF
The channel region of T is formed so as to cross the step of the gate electrode of the concave TFT as shown in FIG. Next, FIG.
As shown in (d), a pattern is formed by photolithography so that no resist remains on the source and drain parts on the bulk of the TFT, and then BF2 + is 30 KeV, 5 ×
The source of the TFT by ion implantation at 10 ¹⁴
Drain regions 206 and 210 are formed. Finally N ₂
Annealing is performed at 900 ° C. for 20 minutes in the atmosphere to activate the ion-implanted boron.

In FIG. 1, when the distance between the concave gate electrodes is 0.5 μm, the thickness of the bulk of the TFT is 400 Å
Therefore, the distance between the concave gate electrodes is wider than twice the thickness of the bulk of the TFT. Further, since the film thickness of the step of the gate electrode of the TFT is 1000Å, the film thickness of the step of the gate electrode of the TFT is thicker than the film thickness of the bulk of the TFT. In the TFT having such a film structure, the channel length L when seen in a plan view
The more substantial channel length L ′ is twice as long as the gate electrode step. Furthermore, if the gate electrode is divided into three parts with such a film structure as shown in FIG. 4, a substantial channel length L ′ is obtained.
Is longer than the thickness of the gate electrode step by four times. For example, in FIG. 1, when the planar channel length L is 1.3 μm, the substantial channel length L ′ is 1.5 μm, and in FIG. 4, the substantial channel length L ′ is 1.7 μm. Become.
Therefore, even if the planar dimension is shortened, it is possible to secure a substantial TFT channel length that does not punch through. According to the present embodiment, the gate electrodes 103 and 104 are formed of the N-type polycrystalline silicon film, but a P-type polycrystalline silicon film may be used, or a high-quality material such as Mo or W may be formed on the polycrystalline silicon film. A high melting point metal polycide film formed with a melting point metal may be used. Further, a refractory metal such as Mo or W may be used.

Further, according to the present embodiment, the bulk of the TFT uses a polycrystalline silicon film obtained by solid phase growth of amorphous silicon, but this may be an amorphous silicon film or a polycrystalline silicon film.

According to this embodiment, the TFT is a source,
The drain is a P-channel type in which a P-type impurity is introduced, but it may be an N-channel type in which an N-type impurity is introduced.

[0017]

According to the thin film MOS transistor (TFT) of the present invention, even if the element size of the TFT on the plane is reduced, the TFT does not punch through, so that it is highly integrated and has low power consumption. There is an effect that can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view and a plan view of a thin film MOS transistor according to the present invention.

2A to 2D are cross-sectional views in order of the steps of a thin-film MOS transistor of the present invention.

FIG. 3 is a cross-sectional view and a plan view of a conventional thin film MOS transistor.

FIG. 4 is a sectional view of another embodiment of the thin film MOS transistor of the present invention.

[Explanation of symbols]

101, 201, 301, 401 ... Silicon substrate 102, 202, 302, 402 ... Silicon oxide film 103, 104, 203, 204 303, 403, 404, 411 ... TFT gate electrode 105, 205, 305, 405 ... TFT gate oxide film 106, 110, 206, 210 305, 306, 406, 410 ... TFT source / drain regions 107, 109, 307, 407 409, 413 ... TFT channel Area 211 ・ ・ ・ Resist

Claims (6)

[Claims] 1. A gate electrode of a thin film MOS type transistor comprising a first insulating film provided on a semiconductor substrate and a first conductive film provided on the first insulating film, and the thin film MOS type. A reverse stagger structure having a second insulating film provided on a gate electrode of a transistor and a source, a drain, and a channel region of a thin film MOS transistor including a first semiconductor film provided on the second insulating film. Thin film MO
In the S-type transistor, the thin-film MOS-type transistor has a concave gate electrode, and the channel region of the thin-film MOS-type transistor exists across the concave-shaped gate electrode. 2. The thin film MOS transistor made of the first conductive film has a stepped portion of the recess of the gate electrode thicker than the channel region of the thin film MOS transistor made of the first semiconductor film. The thin film MOS transistor according to claim 1. 3. A concave thin film MOS formed of a first conductive film.
The gap between the steps of the gate electrode of the transistor is wider than twice the thickness of the channel region of the thin film MOS transistor made of the first semiconductor film. Thin-film MOS transistor. 4. The thin film MOS transistor according to claim 1, 2, or 3, wherein the first conductive film is a polycrystalline silicon film. 5. The thin film MOS type transistor according to claim 1, wherein the first conductive film is a high melting point metal polycide film. 6. The first conductive film is a refractory metal film, and the first conductive film is a high melting point metal film.
The thin film MOS transistor described.