JPH05110388A - Synchronous clock generation circuit, delayed pulse generation circuit using the circuit, and latch circuit used in the circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To generate a synchronous clock without using a high-frequency clock. [Configuration] The reference clock S1 is inverted by the inverting delay element 101a to
Inversion delay clocks S101a to S108a and non-inversion delay clock S10 are sequentially delayed by 108b.
1b to S108b are generated, and D is generated at the fall of the reference clock S1 and the non-inverted delay clocks S101b to S108b.
The data applied to the data input terminal D of the type flip-flops 200 to 208 is output. To the data input terminal D, the outputs of the adjacent D type flip-flops 200 to 208 are connected to the NAND circuits 300 to 3 respectively.
08 is given as a comparison, and N
One of the inverted delay clocks S101a to S108a is selected by the output of the AND circuits 300 to 308, and this is further inverted to output the synchronous clock S3. [Effect] It is possible to obtain an accurate synchronous clock without generating noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generating circuit which synchronizes a reference clock with an asynchronous input signal from the outside and outputs it as a synchronous clock, and an input signal from the outside, particularly an asynchronous signal, with high precision. The present invention relates to a delay pulse generation circuit capable of setting a delay value and a pulse width, and a latch circuit which holds a level of an input signal.

[0002]

2. Description of the Related Art FIG. 29 is a block diagram showing a conventional synchronous clock generating circuit. As shown in the figure, the asynchronous input signal S2 input from the asynchronous signal input terminal 2 for inputting the asynchronous trigger signal is given to one input of the counter 502, and the frequency division enable signal which is the output of the counter 502. S502 is given to the control input of the frequency divider 503. Further, the high frequency clock S501 output from the high frequency clock generation circuit 501 is applied to the other input of the counter 502 and the frequency division input of the frequency divider 503, and the synchronous clock S3 output from the frequency divider 503 is the synchronous clock. It is given to the output terminal 3.

It is assumed that the frequency of the high frequency clock S501 is higher than the frequency of the synchronous clock S3.

Next, the operation will be described. FIG. 30 shows FIG.
10 is a timing chart showing the operation of the conventional synchronous clock generation circuit shown in FIG. When the counter 502 detects the trigger of the asynchronous input signal S2 from the asynchronous signal input terminal 2, it starts counting the rising edges of the high frequency clock S501 which is the output of the high frequency clock generation circuit 501. When the count number reaches a fixed number (3 in this embodiment), the counter 502 lowers the "H" level frequency division enable signal S502 output to the frequency divider 503 to "L" level. When the frequency division enable signal S502 falls to the "L" level, the frequency divider 503 divides the high frequency clock S501 by a predetermined frequency division ratio (4 in this embodiment) to generate a synchronous clock S3. Output to the output terminal 3.

In this conventional circuit, even if the fall of the trigger input of the asynchronous input signal S2 fluctuates within the range shown by the broken line in FIG. 8, the synchronous clock S3 comes out at the same timing. That is, the synchronization accuracy is high frequency clock S5.
The higher the frequency of 01, the better, and approximately, it can be said that the synchronization accuracy = the cycle of the high frequency clock S501.

For example, to obtain a synchronization accuracy of 1 ns, the frequency of the high frequency clock S501 needs to be 1 GHz.

On the other hand, FIG. 31 is a circuit diagram showing a conventional delay pulse generating circuit. As shown in the figure, the pulse input terminal 70 is connected to one end of the resistor 71. The other end of the resistor 71 is connected to one end of the capacitor 72 and the input of the buffer 73. Further, the other end of the capacitor 72 is grounded, and the output of the buffer 73 is the pulse output terminal 75.
It is connected to the.

FIG. 32 is a timing chart showing the operation of the circuit of FIG. In the delayed pulse generation circuit of FIG. 31, the pulse S70 applied to the pulse input terminal 70 is used.
Passes through an integrating circuit composed of a resistor 71 and a capacitor 72, so that the edge becomes dull and becomes a signal S74 having a waveform as shown.

This signal S74 is input to the buffer 73. Then, the delay pulse S75 delayed by the threshold value of the buffer 73 with respect to the pulse S70 input from the pulse input terminal 70 appears on the delay pulse output terminal 75.

[0010]

Since the conventional synchronous clock generating circuit shown in FIG. 29 is configured as described above, it is necessary to increase the frequency of the high frequency clock S501 in order to improve the synchronization accuracy. It was However,
There is a problem of high-frequency noise generated inside the synchronous clock generation circuit, and there is a limit to increasing the frequency of the high-frequency clock S501, and there is a problem that high synchronization accuracy cannot be obtained.

On the other hand, since the conventional delay pulse generating circuit shown in FIG. 31 is constructed as described above, the resistors 71,
When the value of the capacitor 72 fluctuates due to temperature change or the like, there is a problem that the delay time of the delay pulse S75 fluctuates.

Further, the delay value of the delay pulse S75 must be set by changing the values of the resistor 71 and the capacitor 72, but the values that the resistor 71 and the capacitor 72 should take are limited, and the delay pulse S75 However, there is a problem that the delay width of is limited.

Further, there is a problem that the pulse width of the delay pulse S75 cannot be set.

The present invention has been made in order to solve the above-mentioned problems, and, firstly, an object thereof is to obtain a synchronous clock generating circuit having high synchronization accuracy without requiring a high frequency clock. ..

Secondly, it is an object of the present invention to obtain a delay pulse generation circuit which has a small variation in the delay time of the delay pulse, has no limitation on the delay time setting, and can set the pulse width of the delay pulse.

Thirdly, it is also an object to obtain a latch circuit suitable for use in the synchronous clock generation circuit and capable of easily realizing a high-speed latch operation.

[0017]

According to a first aspect of a synchronous clock generation circuit of the present invention, a reference clock is sequentially inverted by a plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. An inversion delay means for generating, a storage means composed of a plurality of storage elements for outputting data applied to its data input terminal from an output terminal in response to a reference clock and a plurality of non-inverted or inverted delay clocks, and adjacent storage By comparing the signals output from the output terminals of the elements and applying the comparison signal as the comparison result to one of the data input terminals of the adjacent storage elements, the phase detection means and the comparison signal output by the phase detection means are used. , A selecting means for deriving a synchronous clock by selecting one of a plurality of inverted or non-inverted delayed clocks. That.

A second aspect of the synchronous clock generating circuit according to the present invention is an inverting delay means for sequentially inverting a reference clock by a plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. In response to the reference clock and the plurality of non-inverted or inverted delayed clocks, the storage means composed of a plurality of storage elements for outputting the data given to the data input terminal from the output terminal and the output means of the output terminal of the adjacent storage element A plurality of inverted or non-inverted signals depending on the phase detection means for comparing the signals to be compared with each other and applying the comparison signal as the comparison result to one data input terminal of one of the adjacent storage elements and the comparison signal output from the phase detection means. Select the specified one of the inverted delay clocks, and if there are multiple selected ones, use the comparison signal It is configured to include a selecting means for deriving a synchronous clock one of the plurality of inverting or non-inverting delay clock by a predetermined priority.

A third aspect of the synchronous clock generating circuit according to the present invention is an inverting delay means for sequentially inverting a reference clock by a plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. Comparing the signals output from the output terminals of the adjacent storage elements with the storage means composed of a plurality of storage elements that outputs the data applied to the data input terminals from the output terminals in response to the asynchronous input signal Then, one of the plurality of inverted or non-inverted delayed clocks is selected by the phase detection means for outputting the comparison signal as the comparison result and the comparison signal output by the phase detection means to derive the synchronous clock. And a selection unit for performing the selection.

A fourth aspect of the synchronous clock generating circuit according to the present invention is an inverting delay means for sequentially inverting a reference clock by a plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. Comparing the signals output from the output terminals of the adjacent storage elements with the storage means composed of a plurality of storage elements that outputs the data applied to the data input terminals from the output terminals in response to the asynchronous input signal Then, by the phase detection means for outputting the comparison signal as the comparison result, and the comparison signal output by the phase detection means, while selecting a designated one of the plurality of inverted or non-inverted delay clocks, When there are a plurality of selected ones, the plurality of inversions or non-inversions are performed according to a predetermined priority using the comparison signal. It is configured to include a selection means for deriving one of the delayed clock as a synchronous clock.

A fifth aspect of the synchronous clock generating circuit according to the present invention is one inversion delay for sequentially inverting a reference clock by a plurality of inversion delay elements to generate a plurality of inversion delay clocks and a plurality of non-inversion delay clocks. And a plurality of storage means comprising a plurality of storage elements for outputting the data supplied to the data input terminal from the output terminal in response to the reference clock and the plurality of non-inverted or inverted delayed clocks, A plurality of phase detecting means for comparing the signals output from the output terminals of the storage elements and giving a comparison signal as the comparison result to one of the data input terminals of the adjacent storage elements; A synchronous clock is derived by selecting one of the plurality of inverted or non-inverted delayed clocks according to the output comparison signal. Is constituted by a plurality of selection means that.

A sixth aspect of the synchronous clock according to the present invention is one inverting delay means for sequentially inverting a reference clock by a plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. A plurality of storage means comprising a plurality of storage elements for outputting data supplied to a data input terminal thereof from an output terminal in response to the reference clock and the plurality of non-inverted or inverted delayed clocks, and the adjacent storage elements A plurality of phase detecting means for comparing the signals output from the output terminals of the above and applying a comparison signal as the comparison result to one of the data input terminals of the adjacent storage elements, and the phase detecting means A selected one of the plurality of inverted or non-inverted delayed clocks is selected and selected by the comparison signal. When there are a plurality of clocks, a plurality of selecting means for deriving one of the plurality of inverted or non-inverted delay clocks as a synchronous clock by using the comparison signal in a predetermined priority order are configured. There is.

A seventh aspect of the synchronous clock generating circuit according to the present invention is one inversion delay for sequentially inverting a reference clock by a plurality of inversion delay elements to generate a plurality of inversion delay clocks and a plurality of non-inversion delay clocks. Means, a plurality of storage means composed of a plurality of storage elements for outputting the data supplied to the data input terminals from the output terminals in response to the asynchronous input signal, and output from the output terminals of the adjacent storage elements. One of the plurality of inverted or non-inverted delay clocks is selected by comparing the signals with each other and outputting a comparison signal as a result of the comparison, and the comparison signal output by the phase detection means. And a plurality of selecting means for deriving the synchronous clock.

An eighth aspect of the synchronous clock generating circuit according to the present invention is one inversion delay for sequentially inverting a reference clock by a plurality of inversion delay elements to generate a plurality of inversion delay clocks and a plurality of non-inversion delay clocks. Means, a plurality of storage means composed of a plurality of storage elements for outputting the data supplied to the data input terminals from the output terminals in response to the asynchronous input signal, and output from the output terminals of the adjacent storage elements. One of the plurality of inverted or non-inverted delay clocks is designated by a plurality of phase detection means for comparing signals and outputting a comparison signal as the comparison result and the comparison signal output by the phase detection means. When there are a plurality of selected items, the comparison signal is used to select the plurality of items according to a predetermined priority order. And a plurality of selection means for deriving one of the inverted or non-inverted delay clock as a synchronous clock is configured. .

First of the delay pulse generating circuit according to the present invention
In the aspect, the synchronous clock generating means for generating the synchronous clock synchronized with the input signal, the synchronous clock is counted, and the pulse is set with a predetermined count value,
And a pulse generating means for generating a delayed pulse by performing pulse reset with another predetermined count value.

The second of the delay pulse generating circuit according to the present invention
In this aspect, the input signal is distributed in accordance with the order of the pulses, and the input signal distribution means generates a plurality of distribution input signals, and the plurality of synchronization clocks generate a plurality of synchronization clocks respectively synchronized with the plurality of distribution input signals. A clock generating means and a plurality of synchronous clocks are respectively counted, a pulse is set at a predetermined count value, and a pulse is reset at another predetermined count value to generate a plurality of distributed delay pulses. And a delay pulse synthesizing unit for synthesizing the plurality of distribution delay pulses to generate a delay pulse.

In the latch circuit according to the present invention, an input signal is applied to its input and a positive gate for latching the first gate activated at the first level of the control input and the output signal of the first gate. In a latch circuit having a second gate provided in a feedback loop, activated at a second level of a control input, and having its output signal line connected to the output signal line of the first gate, a second gate Output impedance is lower than the output impedance of the first gate.

[0028]

In the first aspect of the synchronous clock generating circuit according to the present invention, the inverting delay means sequentially inverts the reference clock by the plurality of inverting delay elements to generate the plurality of inverting delay clocks and the plurality of non-inverting delay clocks. Generate,
In response to the reference clock and the plurality of non-inverted or inverted delayed clocks, the storage means composed of a plurality of storage elements outputs the data given to the data input terminal from the output terminal, and the phase detection means outputs the data to the adjacent storage elements. The signals output from the output terminals are compared, the comparison signal as the comparison result is given to one of the data input terminals of the adjacent storage elements, and the selection means outputs the comparison signal output by the phase detection means. Since the synchronous clock is derived by selecting one of a plurality of inverted or non-inverted delayed clocks, the synchronization accuracy of the synchronized clock can be made equal to the delay value of two stages of inverted delay elements.

In the second aspect of the synchronous clock generating circuit according to the present invention, the inverting delay means sequentially inverts the reference clock by the plurality of inverting delay elements to generate the plurality of inverting delay clocks and the plurality of non-inverting delay clocks. In response to the reference clock and the plurality of non-inverted or inverted delayed clocks, the storage means including the plurality of storage elements generates the data and outputs the data provided to the data input terminal from the output terminal. The signals output from the output terminals of the storage elements are compared with each other, the comparison signal as the comparison result is applied to one of the data input terminals of the adjacent storage elements, and the comparison means outputs the phase detection means by the selection means. The signal selects and selects a specified one of multiple inverted or non-inverted delayed clocks. If there are a plurality of clocks that have been synchronized, the comparison signal is used to derive one of a plurality of inverted or non-inverted delay clocks as a synchronization clock by a predetermined priority order, so that the synchronization accuracy of the synchronization clock is improved. It can be made equal to the delay value of two stages of inverting delay elements.

In the third aspect of the synchronous clock generating circuit according to the present invention, the inverting delay means sequentially inverts the reference clock by the plurality of inverting delay elements to generate the plurality of inverting delay clocks and the plurality of non-inverting delay clocks. In response to the asynchronous input signal, the data generated by the storage means including a plurality of storage elements, the data provided to the data input terminal is output from the output terminal, the phase detection means,
The signals output from the output terminals of the adjacent storage elements are compared with each other, the comparison signal as the comparison result is output, and the selection means outputs a plurality of inverted or non-inverted delay clocks according to the comparison signal output from the phase detection means. Since one of these is selected to derive the synchronous clock, the synchronization accuracy of the synchronous clock can be made equal to the delay value of two stages of inverting delay elements.

In the fourth aspect of the synchronous clock generating circuit according to the present invention, the inverting delay means sequentially inverts the reference clock by the plurality of inverting delay elements to generate the plurality of inverting delay clocks and the plurality of non-inverting delay clocks. In response to the asynchronous input signal, the data generated by the storage means including a plurality of storage elements, the data provided to the data input terminal is output from the output terminal, the phase detection means,
The signals output from the output terminals of the adjacent storage elements are compared with each other, the comparison result is output, and the selection means selects one of a plurality of inverted or non-inverted delay clocks according to the comparison signal output by the phase detection means. When there are a plurality of selected ones, a comparison signal is used to derive one of a plurality of inverted or non-inverted delayed clocks as a synchronous clock by a predetermined priority. Therefore, the synchronization accuracy of the synchronization clock can be made equal to the delay value of two stages of inverting delay elements.

In the fifth aspect of the synchronous clock generating circuit according to the present invention, the reference clock is sequentially inverted by the plurality of inverting delay elements by one inverting delay means, and a plurality of inverting delay clocks and a plurality of non-inverting delays are provided. In response to the reference clock and the plurality of non-inverted or inverted delayed clocks, a plurality of storage means that generate a clock and output a data applied to the data input terminal from the output terminal, The phase detection means compares the signals output from the output terminals of the adjacent storage elements with each other, and the comparison signal as the comparison result is applied to one data input terminal of the adjacent storage elements. , One of a plurality of inverted or non-inverted delayed clocks is selected according to the comparison signal output by the phase detection means Since the synchronous clock is derived from the synchronous clock, the synchronous accuracy of the synchronous clock can be made equal to the delay value of two stages of inverting delay elements, and a common inverting delay or non-inverting delay clock from one inverting delay means can be obtained. It is possible to derive a plurality of synchronous clocks by operating based on the above.

In the sixth aspect of the synchronous clock generating circuit according to the present invention, the reference clock is sequentially inverted by a plurality of inverting delay elements by one inverting delay means, and a plurality of inverting delay clocks and a plurality of non-inverting delays are provided. In response to the reference clock and the plurality of non-inverted or inverted delayed clocks, a plurality of storage means that generate a clock and output a data applied to the data input terminal from the output terminal, The phase detection means compares the signals output from the output terminals of the adjacent storage elements with each other, and the comparison signal as the comparison result is applied to one data input terminal of the adjacent storage elements. , A specified one of a plurality of inverted or non-inverted delayed clocks depending on the comparison signal output by the phase detection means. When there are a plurality of selected ones, one of a plurality of inverted or non-inverted delayed clocks is derived as a synchronous clock by a predetermined priority using a comparison signal. The synchronization accuracy of the synchronizing clock can be made equal to the delay value of two stages of inverting delay elements, and a plurality of synchronizing clocks are derived by operating based on a common inverting delay or non-inverting delay clock from one inverting delay means. can do.

In the seventh aspect of the synchronous clock generating circuit according to the present invention, one inversion delay means sequentially inverts the reference clock by a plurality of inversion delay elements, and a plurality of inversion delay clocks and a plurality of non-inversion delays. In response to an asynchronous input signal, a clock is generated by a plurality of storage means composed of a plurality of storage elements, and data provided to its data input terminal is output from an output terminal. Compare the signals output from the output terminal of the element, output the comparison result,
Since the plurality of selecting means selects one of the plurality of inverted or non-inverted delayed clocks to derive the synchronous clock according to the comparison signal output from the phase detection means, the synchronization accuracy of the synchronized clock is inverted. It is possible to equalize the delay values of two stages, and it is possible to derive a plurality of synchronous clocks by operating on the basis of a common inversion delay or non-inversion delay clock from one inversion delay means.

In the eighth aspect of the synchronous clock generating circuit according to the present invention, one inversion delay means sequentially inverts the reference clock by a plurality of inversion delay elements, and a plurality of inversion delay clocks and a plurality of non-inversion delays. In response to an asynchronous input signal, a clock is generated by a plurality of storage means composed of a plurality of storage elements, and data provided to its data input terminal is output from an output terminal. The signals output from the output terminals of the elements are compared with each other, a comparison signal as the comparison result is output, and a plurality of selecting means outputs a plurality of inverted or non-inverted delayed clocks according to the comparison signal output by the phase detection means. If there is more than one selected, the specified one of them will be selected in advance using the comparison signal. Since one of a plurality of inverted or non-inverted delayed clocks is derived as a synchronous clock according to the priority order, the synchronization accuracy of the synchronous clock can be made equal to the delay value of two stages of inverted delay elements, and 1 It is possible to derive a plurality of synchronous clocks by operating on the basis of a common inversion delay or non-inversion delay clock from one inversion delay means.

First of the delay pulse generating circuit according to the present invention
In the above aspect, the synchronous clock generating means generates a synchronous clock synchronized with the input signal, the pulse generating means counts the synchronous clocks, performs pulse setting with a predetermined count value, and another predetermined clock value is set. Since the delayed pulse is generated by resetting the pulse with the count value that has been set, if the count is started after the input signal reaches a certain level, the count value is previously set after the asynchronous signal reaches a certain level. The leading edge of the delay pulse is formed by the delay time until the count value reaches a predetermined count value, and the trailing edge of the delay pulse is formed by the pulse width until the count value reaches another predetermined count value.

The second of the delay pulse generating circuit according to the present invention
In the aspect, the input signal distribution unit distributes the input signal according to the order of the pulses, generates a plurality of distribution input signals, and a plurality of synchronous clock generation units,
A plurality of synchronization clocks that are respectively synchronized with the plurality of distribution input signals are generated, the plurality of distribution delay pulse generating means count the plurality of synchronization clocks, and a pulse is set at a predetermined count value, and another By performing pulse reset with a predetermined count value, a plurality of distribution delay pulses are generated, and the delay pulse synthesizing means synthesizes a plurality of distribution delay pulses to generate delay pulses. If the distribution delay pulse generation circuit starts counting after the input signal has reached a certain level, the count value of the plurality of distribution delay pulse generation circuits is a predetermined count value after the input signal has reached a certain level. The leading edge of the delayed pulse is formed by the delay time until it reaches the value, and the count value is set to another predetermined count value. Trailing edge of the delay pulse in the pulse width until the preparative value is formed a plurality of distribution delay pulse is generated, it is delayed pulse relative to the input signal is generated by being synthesized last.

In the latch circuit according to the present invention, since the output impedance of the second gate is lower than the output impedance of the first gate, both the first gate and the second gate are enabled. At this time, the output potential of the second gate becomes dominant over the output potential of the first gate, which prevents the output potential in the positive feedback loop from holding the intermediate potential.

[0039]

1 and 2 are circuit diagrams showing a first embodiment of a synchronous clock generating circuit according to the present invention. As shown in these figures, the reference clock input terminal 1 is the input terminal of the inverting delay element 101a in the delay clock generation circuit 10, and the output terminal of the inverting delay element 101a is the inverting delay element 101b.
To the input terminal of the reference clock input terminal 1
Are sequentially connected to the inverting delay elements 101a and 108b.

The reference clock input terminal 1 and the output terminals of the inverting delay elements 101b to 108b are the storage circuit 2.
Each of the D type flip-flops 200 to 208 in 0 is connected to the negative logic timing signal input terminal * T. (* T indicates T bar. The bar is indicated by a bar symbol in the figure.) Also, the output terminal Q of the D type flip-flops 200 to 208 is the phase detection circuit 3.
The output terminals Q of the D-type flip-flops 201 to 208 are respectively connected to the negative logic input terminals of the NAND circuits 300 to 308 in 0 in the NAND circuit in the phase detection circuit 30.
It is connected to the positive logic input terminals of each of the circuits 300 to 307. The positive logic input terminal of the NAND circuit 308 is grounded.

Further, NAND circuits 300 to 308 are provided.
The negative logic output terminal of the D-type flip-flop 200
Through 208, respectively, and the output terminals of the NAND circuits 300 through 307 are also connected to the OR circuits 401 through 4 in the clock selection circuit 40.
08 is connected to one negative logic input terminal. (The AND circuit whose inputs and outputs are all negative logic is equivalent to the OR circuit according to De Morgan's law.) The other negative logic input terminals of the OR circuits 401 to 408 are inverted in the delay clock generation circuit 10. Delay element 101a
To 108a output terminals are respectively connected,
The negative logic output terminals of the OR circuits 401 to 408 are connected to the input terminals of an 8-input NAND circuit 411 (OR circuits having all negative logic inputs are equivalent to NAND circuits according to De Morgan's law). There is. Also, NAND
The output terminal of the circuit 411 is connected to the synchronous clock output terminal 3.

Further, the asynchronous signal input terminal 2 has the D type flip-flops 200 to 208 in the memory circuit 20.
Of the reset input terminals R.

Next, the operation will be described. FIG. 3 shows FIG.
3 is a timing chart showing the operation of the circuit of FIG. 2. In the timing chart of FIG. 3, the signals S105a and S108b output by the inverting delay elements 105a and 108b in the delay clock generation circuit 10 and the D type flip-flops 204 and 2 in the memory circuit 20 are shown.
08 signal S204 output from each output terminal Q
Through S208, NAND circuit 3 in the phase detection circuit 30
04 to 308 respectively output signals S304 to S308 and the OR circuit 40 in the clock selection circuit 40.
Signals S405 to S408 output by 5 to 408 are omitted.

First, a reference clock S1 as shown in the figure is input from the reference clock input terminal 1, and the reference clock S1 is supplied to the inverting delay elements 101a to 108b.
Are sequentially delayed by the inversion delay elements 101a to 108a.
108a, and the non-inverted delay clocks S101b and S108b are output from the inverting delay elements 101b and 108b, respectively.

While the asynchronous input signal S2 input from the asynchronous signal input terminal 2 is at the "H" level, the D-type flip-flops 200 to 208 are in the reset state and the signals output from the respective output terminals Q. S20
0 to S208 become "L" level.

Therefore, the levels of the signals applied to the negative logic input terminal and the positive logic input terminal of the NAND circuits 300 to 308 are both "L",
"H" level signals S300 to S308 are output from the output terminals of the NAND circuits 300 to 308, and these are output to the D type flip-flops 200 to 2.
08 data input terminals D, respectively.

Now, assuming that the level of the asynchronous input signal S2 input from the asynchronous signal input terminal 2 falls from "H" to "L" at the timing shown in the figure, the D type flip-flop 200 in the memory circuit 20. Through 208
The reset signal input terminal R of becomes the "L" level and the reset is released.

Therefore, each of the D type flip-flops 200 to 208 receives the reference clock input terminal 1 which is input to the negative logic timing signal input terminal * T.
And the data input terminal D at the fall of the reference clock S1 and the non-inverted delay clocks S101b to S108b which are the outputs of the inverting delay elements 101b to 108b.
NAND circuits 300 to 308 respectively applied to
The signals S300 to S308, which are the outputs of the above, are output from the output terminal Q thereof.

When the falling edges E0 and E1 are generated in the reference clock S1 and the non-inverted delay clock S101b, respectively, the level of the asynchronous input signal S2 is still "H", so that the D type flip-flops 200 and 201 are in the reset state. Then, the levels of the signals S200 and S201 respectively output from the output terminal Q become "L".

On the other hand, falling edges E2 to E4 are applied to the non-inverted delay clocks S102b to S104b, respectively.
Is generated, the level of the asynchronous input signal S2 is already "L", so that the signal S2 output from the output terminals Q of the D type flip-flops 202 and 204 respectively.
The levels of 02 and S204 are "H", which is the same as the levels of S302 to S304 which are output signals of the NAND circuits 302 to 304.

Therefore, the NAN in the phase detection circuit 30 is
NAN in which "L" is input to the negative logic input terminal and "H" is input to the positive logic input terminal of the D circuits 300 to 303
Only the output signal S301 of the D circuit 301 becomes the “L” level, and the output signals S300, S302, S303 of the NAND circuits 300, 302, 303 respectively remain at the “H” level.

Since the output signals S300 to S303 of the NAND circuits 300 to 303 are given to one input terminals of the OR circuits 401 to 404 in the clock selection circuit 40, respectively, the OR circuits 401 and 403, 4 are provided.
04 output signals S401, S403, and S404 are "H".
The output signal S1 of the inverting delay element 102a in the delay clock generation circuit 10 which is “level and the output signal of the OR circuit 402 is given to the other input terminal of the OR circuit 402
02a.

Therefore, from the output of the NAND circuit 411, a signal obtained by inverting the inverted delay clock S102a which is the output signal of the inverting delay element 102a is output, and this signal is given to the synchronous clock output terminal 3 as the synchronous clock S3.

Next, when falling edges E6 to E9 occur again on the reference clock S1 and the non-inverted delay clocks S101b to S104b, respectively, D
Since the reset of the type flip-flops 200 to 203 has already been released, the levels of the signals S200 to S203 output from the output terminals Q of the D type flip-flops 200 to 203 are NAND.
The levels are the same as the levels of the output signals of the circuits 300 to 303, S300 to S303. That is,
The levels of the signals S200 to S203 are "H",
It becomes “L”, “H”, “H”, and the NAND circuits 300 to 3 in the phase detection circuit 30 are the same as described above.
03, only the output signal S301 of the NAND circuit 301 can hold the “L” level, and the output signals S300 of the NAND circuits 300 and 302, 303, respectively.
And, S302 and S303 become "H" level, and from the output of the NAND circuit 411 in the clock selection circuit 40,
A signal obtained by inverting the inverted delay clock S102a which is the output signal of the inverted delay element 102a is continuously supplied to the synchronous clock output terminal 3 as the synchronous clock S3.

In the above configuration, even if the falling timing of the asynchronous input signal S2 varies within the range shown by the broken line in FIG. 3, each D type flip-flop 200
Through 208, the levels of the output signals S200 through S208 do not change, and the synchronous clock S3 comes out at the same timing.

Therefore, since the synchronization accuracy is equal to the phase difference between the delayed clocks input to the adjacent D-type flip-flops, it can be approximately said that the synchronization accuracy = the delay value of two stages of inverting delay elements.

If the inverting delay element is composed of a semiconductor logic element, the delay value for two stages of the inverting delay element can be set to 1 ns or less, and a synchronous clock generating circuit having high synchronization accuracy can be obtained without using a high frequency clock. be able to.

In this embodiment, the phase detection circuit 30
The output terminals of the NAND circuits 300 to 307 in the internal circuit are connected to the OR circuits 401 to 4 in the clock selection circuit 40, respectively.
08 to connect to one terminal of the OR circuits 401 to 40
8 Inversion delay element 1 connected to the other terminal of each
Inversion delay clock S which is the output of 01a to 108a
Among 101a to S108a, the one closest in time to the falling trigger of the asynchronous input signal S2 is selected and output as the synchronous clock S3. However, as shown in FIG. 4, the NAND circuit 300 in the phase detection circuit 30 is selected. To 307 and the one terminal of the OR circuits 401 to 408 in the clock selection circuit 40, the connection is changed to a desired timing different from the one closest in time to the falling trigger of the asynchronous input signal S2. The inverted delay clock may be selected.

Next, the inverting delay elements 101a to 108.
An example in which the output load capacity of b is adjusted to a constant value will be described.

FIG. 5 shows the basic clock input terminal 1 shown in FIGS. 1 and 2, the inverting delay elements 101a and 102b included in the delay clock generation circuit 10, and the clock selection circuit 40.
The OR circuits 401 and 402 included in FIG. 2 and the first-stage inverters 210 and 211 connected to the timing signal input terminals * T of the D type flip-flops 200 and 201 included in the memory circuit 20 are extracted and shown. ..

In order to set the output load capacitances of the inverting delay elements 101a and 102b to a constant value or an approximate value, first stage transistors (not shown) connected to the input terminals of the OR circuits 401 and 402 included in the clock selection circuit 40. ) The size and the transistor size of the first stage inverters 210 and 211 connected to the timing signal input terminals * T of the D type flip-flops 201 and 202 included in the memory circuit 20 are set to the same value or an approximate value. Further, the wiring lengths of the wirings connected to the output terminals of the inverting delay elements 101a and 102b are set to the same value or an approximate value. Therefore, the inverting delay elements 101a and 102b whose output load capacitances have the same value or an approximate value have delay values of the same value or an approximate value, respectively.

FIG. 6 is a timing chart showing the operation of the circuit of FIG. 5 in such a case. The reference clock S1 as shown in the figure input from the reference clock input terminal 1 is sequentially delayed by the inverting delay elements 101a to 102b to generate the inverting delay clocks S101a and 101b and the non-inverting delay clocks S101b and S102b.

Inverted delay clocks S101a and S102a
And the time required for each of the non-inverted delay clocks S101b and S102b to fall from "H" to "L" is A
If the time required for the rising from “L” to “H” is B, the rising edge of the non-inverted delay clock S102b is delayed by 2 (A + B) with respect to the reference clock S1, and the falling edge is 2 (B + A). Delay time.

Therefore, the non-inverted delay clock S102
Delay values of rising and falling of b with respect to the reference clock S1 are equal, and a delay clock such as the non-inverted delay clock S102b having the same duty as the reference clock S1 can be obtained.

On the other hand, the inverting delay elements 101a to 102
If b have different output load capacitances, the inverting delay elements 101a and 102b have different delay values. FIG. 7 is a timing chart showing the operation of the circuit of FIG. 5 in such a case. A reference clock S1 as shown in the figure which is input from the reference clock input terminal 1.
Are sequentially delayed by the inverting delay elements 101a and 102b to generate inverting delay clocks S101a and 101b and non-inverting delay clocks S101b and S102b.

Inverted delay clocks S101a and S102a
Falling to take time each A ₁ to each of the "H" from "L", A _3, and each time required for rising B _1, B ₃ to "L" to "H", the non-inverting delay clock The time required to rise from “L” to “H” of S101b and S102b is B ₂ , respectively.
Assuming that B ₄ and the time required to fall from “H” to “L” are A ₂ and A ₄ , respectively, the non-inverted delay clock S1
02b has a rising edge (A
₁ + B ₂ + A ₃ + B ₄ ) time delay, falling (B
₁ + A ₂ + B ₃ + A ₄ )) Time delay.

Therefore, the non-inverted delay clock S102
Delay values of rising and falling of b with respect to the reference clock S1 are different, and a delay clock such as a non-inverted delay clock S102b having a duty different from that of the reference clock S1 is generated.

As described above, by adjusting the output load capacitances of the inverting delay elements 101a and 102b to a constant value or an approximate value, it is possible to generate a delay clock whose duty is equal to or close to that of the reference clock S1.
The synchronization accuracy can be improved.

In the above embodiment, the inverting delay element 10 is used.
The non-inverted delay clocks output from 1b to 108b are applied to the negative logic timing signal input terminals * T of the D type flip-flops 200 to 208, thereby selecting the inverted delay clocks output from the inversion delay elements 101a to 108a. However, on the contrary, the inverting delay element 1
The inverted delay clocks output from 01a to 108a are applied to the negative logic timing signal input terminals * T of the D type flip-flops 200 to 208, thereby selecting the non-inverted delay clocks output from the inversion delay elements 101b to 108b. May be.

Here, some disadvantages of the circuits of FIGS. 1 and 2 will be described. FIG. 8 is a timing chart showing the operation of the circuit of FIGS. 1 and 2 when the cycle of the reference clock S1 is shortened or when the delay time per stage of the inverting delay elements 101a to 108b is lengthened. is there. In the timing chart of FIG. 8, the inverting delay elements 103b to 105b, 108a and 101a, 103a to 1 in the delay clock generation circuit 10 are shown.
06a and 108a output signals S103b to S105b, S108a and S101a and S103, respectively.
a to S106a, S108a, D in the memory circuit 20
The signals S203 to S205, S208 output from the output terminals Q of the type flip-flops 203 to 205, 208, and the signals S300, S302 to S302 to the NAND circuits 300, 302 to 305, 307, 308 in the phase detection circuit 30, respectively. S305,
S307, S308, and signals S401, S403 to S406, S408 output from the OR circuits 401, 403 to 406, 408 in the clock selection circuit 40, respectively.
Is omitted.

In such a case, the non-inverted delay clock S1
Of 02b to S108b, non-inverted delay clocks of substantially the same phase may be generated. For example, as shown in the timing chart of FIG.
101b and S106b and S102b and S108b correspond to that.

In this state, the asynchronous signal input terminal 2
Assuming that the level of the asynchronous input signal S2 that is input from the device falls from "H" to "L" at the timing shown in the figure, the reference clock S1 and the non-inverted delay clock S101.
b, S106b falling edges E0, E respectively
1 and E6 are generated before the fall of the asynchronous input signal S2, the D-type flip-flops 200 and 20
The output signals S200, S201, and S206 of 1 and 206 become "L" level.

On the other hand, the non-inverted delay clocks S102b, S
Since the falling edges E2 and E7 of 107b are generated after the falling of the asynchronous input signal S2,
Output signal S of D type flip-flops 202 and 207
202 and S207 become "H" level. Therefore,
The output signals S301 and S306 of the NAND circuits 301 and 306 in the phase detection circuit 30 become "L" level, and the OR circuits 402 and 407 in the clock selection circuit 40 output the inverted delay clocks S102a and S107a, respectively. Therefore, when one or both of the inverted delay clocks S102a and S107a are at the "L" level via the NAND circuit 411, it is at the "H" level, and when both of the inverted delay clocks S102a and S107a are at the "H" level, "H" level. A signal of L level is output from the synchronous clock output terminal 3 as the synchronous clock S3.

At this time, as the synchronous clock S3, the "H" level period within one cycle is longer than the reference clock S1 by the shaded portion shown in FIG. 8, and the "L" level period is shown in FIG. The hatched portion is shortened, and the duty of the synchronous clock S3 is different from the duty of the reference clock S1.

FIG. 9 is a circuit diagram showing a second embodiment of the synchronous clock generating circuit according to the present invention. In the clock selecting circuit 40 shown in FIG. 2, OR circuits 401 to 408 are provided.
Inverted delay clock is output from two or more of
(Multiple output) NAND clock 411 to reference clock S1
The synchronous clock S3 having different duty is prevented from being output. The delay clock generation circuit 10, the storage circuit 20, and the phase detection circuit 30 shown in FIG. 1 have the same configuration in this embodiment, and will be omitted.

As shown in the figure, the output terminals of the NAND circuits 300 to 307 in the phase detection circuit 30 shown in FIG. 1 are the OR circuits 40 in the clock selection circuit 41 shown in FIG.
It is connected to one of the input terminals 1 to 408. The output terminals of the inverting delay elements 101a to 108a in the delay clock generation circuit 10 shown in FIG. 1 are connected to the other input terminals of the OR circuits 401 to 408, respectively. Further, the output terminals of the OR circuits 401 to 403 are connected to the input terminals of the 3-input NAND circuit 421 by OR.
The output terminals of the circuits 404 to 406 are connected to the input terminal of the 3-input NAND circuit 422, and the output terminals of the OR circuits 407 and 408 are connected to the input terminal of the 3-input NAND circuit 423. One input terminal of the 3-input NAND circuit 423 which is not connected is connected to the power supply terminal. The reason why the 2-input NAND circuit is not used instead of the 3-input NAND circuit 423 is that the inverted delay clocks S101a to S1
This is for equalizing the time until one of the signals 08a is selected and is output from the synchronous clock output terminal 3.

The 3-input NAND circuits 421 to 4 are also provided.
The respective output terminals of the 23 are connected to the respective one input terminals of the 3-input NAND circuits 441 to 443. The output of the 3-input NAND circuits 441 to 443 is 3
The input terminals of the input NAND circuit 451 are respectively connected, and the output terminal of the 3-input NAND circuit 451 is connected to the synchronous clock output terminal 3.

Further, the output terminals of the NAND circuits 300 to 302 in the phase detection circuit 30 shown in FIG. 1 are connected to the input terminals of the 3-input AND circuit 431 in the clock selection circuit 41 and the NAND circuit 303 in the phase detection circuit 30. Through 3
The output terminal of 05 is a 3-input A in the clock selection circuit 41.
They are connected to the input terminals of the ND circuit 431, respectively.

The output terminal of the 3-input AND circuit 431 is connected to one input terminal of each of the 3-input NAND circuits 442 and 443, and the output terminal of the 3-input AND circuit 432 is connected to one input terminal of the 3-input NAND circuit 443. Has been done. A power supply terminal is connected to two unconnected input terminals of the three-input NAND circuit 441 and one unconnected input terminal of the three-input NAND circuit 442.
An inverter and a 2-input NAND circuit are not used instead of the 3-input NAND circuits 441 and 442, respectively.
One of the inverted delay clocks S101 to S108a
This is to equalize the time until one of them is selected and output from the synchronous clock output terminal 3.

Next, the operation will be described. FIG. 10 is a timing chart showing the operation of the circuits shown in FIGS. In the timing chart of FIG. 10, the inverting delay elements 103b to 10b in the delay clock generation circuit 10 are arranged.
5b, 108a and signals S103b through S105b, S108a output by 101a through 108a, respectively.
And S101a to S108a, D in the memory circuit 20.
The signals S203 to S205, S208 output from the output terminals Q of the respective type flip-flops 203 to 205, 208, and the signals S300, S302 to S302 to the NAND circuits 300, 302 to 305, 307, 308 in the phase detection circuit 30, respectively. S305,
S307 and S308, and signals S401 output from the OR circuits 401 to 408 in the clock selection circuit 40, respectively.
Through S408 are omitted.

First, the reference clock S1 as shown in the figure is input from the reference clock input terminal 1, and the reference clock S1 is input to the inverting delay elements 101a to 108b.
Are sequentially delayed by the inversion delay elements 101a to 108a.
108a, and the non-inverted delay clocks S101b and S108b are output from the inverting delay elements 101b and 108b, respectively.

While the asynchronous input signal S2 input from the asynchronous signal input terminal 2 is at the "H" level, the D-type flip-flops 200 to 208 are in the reset state and the signals output from the respective output terminals Q. Becomes "L" level.

Therefore, the levels of the signals applied to the negative logic input terminals and the positive logic input terminals of the NAND circuits 300 to 308 are both "L",
"H" level signals S300 to S308 are output from the output terminals of the NAND circuits 300 to 308, and these are D type flip-flops 200 to 2.
08 data input terminals D, respectively.

Now, assuming that the level of the asynchronous input signal S2 input from the asynchronous signal input terminal 2 falls from "H" to "L" at the timing shown in the figure, the D type flip-flop 200 in the memory circuit 20. Through 208
The reset signal input terminal R of becomes the "L" level and the reset is released.

Therefore, each of the D-type flip-flops 200 to 208 receives the reference clock input terminal 1 which is input to its negative logic timing signal input terminal * T.
And the data input terminal D at the fall of the reference clock S1 and the non-inverted delay clocks S101b to S108b which are the outputs of the inverting delay elements 101b to 108b.
NAND circuits 300 to 308 respectively applied to
The signals S300 to S308, which are the outputs of the above, are output from the output terminal Q thereof.

Reference clock S1, non-inverted delay clock S
Falling edge E on each of 101b and S106b
When 0, E1 and E6 occur, the level of the asynchronous input signal S2 is still "H", so that the D type flip-flops 200, 201 and 206 are in the reset state, and the signal S200 output from the output terminal Q thereof, respectively. , S20
The levels of 1 and S206 are "L".

On the other hand, the non-inverted delay clocks S102b, S
When the falling edges E2 and E7 are generated at the respective 107b, the asynchronous input signal S2 is already at the "H" level, so the signals S202 and S output from the output terminals Q of the D type flip-flops 202 and 207, respectively.
207 has the same “H” level as the levels of the output signals of the NAND circuits 302 to 307, S302 to S307.

Therefore, the NAN in the phase detection circuit 30 is
Only the D circuits 301 and 306 are inputted with "L" level at their negative logic input terminals and "H" level at their positive logic input terminals, and only the output signals S301 and S306 of the NAND circuits 301 and 306 are "L". "It becomes a level. NAN
Output signals S300 to S of D circuits 300 to 307
Reference numeral 307 denotes an OR circuit 4 in the clock selection circuit 40.
01 to 408, the output signals S401, S403 and S404 to S406 and S408 of the OR circuits 401, 403 and 404 to 406 and 408 become "H" level, and OR
The output signals S402, S407 of the circuits 402, 407 are inverted delay clocks S103a, which are output signals of the inverted delay elements 102a, 107a in the delayed clock generation circuit 10 which are applied to the other input terminals of the OR circuits 402, 407, respectively. It becomes S107a.

Therefore, the inverted delay clock 1 output from the AND circuit 402 is output from the 3-input NAND circuit 421.
The inverted signal of 02a is "L" level from the 3-input NAND circuit 422, and the inverted signal from the 3-input NAND circuit 423 is AN.
A signal obtained by inverting the inverted delay clock 107a that is the output of the D circuit 407 is output.

The outputs S300, S302, S of the NAND circuits 300, 301, 302 in the phase detection circuit 30 are also provided.
The output levels of 303 are "H", "L", and "H", respectively.
Therefore, the output S431 of the 3-input AND circuit 431 in the clock selection circuit 40 becomes "L" level. Similarly, the NAND circuits 303, 30 in the phase detection circuit 30
Since the outputs S303, S304, and S305 of 4,305 are all at the "H" level, the clock selection circuit 4
The output S432 of the 3-input AND circuit 432 in 0 is "H".
It becomes a level.

Since the output signal of the 3-input AND circuit 431 is at the "L" level, the 3-input NAND circuit 44
The output signals S 442 and S 443 of 2, 443 become the “H” level, and the signal obtained by inverting the inverted delay clock S 102 which is the output of the OR circuit 402 from the 3-input NAND circuit 451 is the synchronous clock output terminal as the synchronous clock S 3. It is output from 3.

As described above, in the circuit configurations shown in FIGS. 1 and 9, the OR circuits 401 to 408 in the clock selection circuit 40 are arranged in the first group of the OR circuits 401 to 403 and the second group of the OR circuits 404 to 406. Group and O
When the OR circuit of one of the first groups outputs the inverted delay clock, the inverted delay clocks output from the OR circuits of the second and third groups are divided into the third groups of R circuits 407 and 408. The output from the synchronous clock output terminal as the synchronous clock S3 is prevented, and the inverted delay clock is not output from the OR circuits 401 to 403 of the first group.
When the inverted delay clocks are output from one OR circuit, the inverted delay clocks output from the third group of OR circuits are prevented from being output from the synchronous clock output terminal as the synchronous clock S3, and the synchronous clock S3 is used as a reference. The duty is the same as that of the clock S1.

The clock selection circuit 42 shown in FIG.
As described above, the OR circuits 401 to 408 are connected to the OR circuit 40.
1 to 404 in the first group and OR circuits 405 to 408 in the second group, and when the inverted delay clock is output from one OR circuit in the first group,
Even if the inverted delayed clock output from the OR circuit of the second group is prevented from being output from the synchronous clock output terminal as the synchronous clock S3, the same effect can be obtained.

As described above, the number of OR circuits belonging to the same group may be any, but in consideration of the cycle of the reference clock S1 and the delay time of each of the inverting delay elements 101a to 108b, a plurality of OR circuits in the same group are considered. It is necessary to prevent the inverted delay clock from being output from the OR circuit.

Further, the inverting delay elements 101a to 108b in the delay clock generation circuit 10 shown in FIG. 1 and the D type flip-flops 200 to 20 in the storage circuit 20.
8 and the NAND circuits 300 to 307 in the phase detection circuit 30 are connected as shown in FIG. 12, the same effect as the first and second embodiments can be obtained. That is, the reference clock input terminal 1 is connected to the data signal input terminal D of the D type flip-flop 200, and the asynchronous signal input terminal 2 is passed through the buffer to the negative logic timing signal input terminal * T of the D type flip-flops 200 to 208. And inverting delay elements 101b, 102b, 103
b, 104b, 105b, 106b, 107b, 108
Each output of b is connected to a D-type flip-flop 201.
Or 208 to the data signal input terminal D.
Other configurations are similar to those of the circuit shown in FIG.

Only the points different from the operation of the circuit shown in FIG. 1 will be described below with reference to the timing chart shown in FIG. Due to the occurrence of the falling edge S2b of the asynchronous input signal S2b via the buffer, the D type flip-flops 200 to 208 hold the signals S1 and S101b to S108b to the data input terminal D at that time and output from the output terminal Q. To do. Therefore, at the time when the falling edge S2b of the asynchronous input signal S2b occurs, the signals S200 to S203 are "L", respectively.
It becomes "L", "H", "H". As a result, at this time, the signals S300 to S303 are respectively "H", "L",
It becomes "H" and "H". And like the one shown in FIG.
Inverted delay clock S102 by "L" of signal S301
a is selected and becomes a signal S402, which is output as the synchronization clock S3. In this embodiment, since the asynchronous input signal S2b via the buffer is input to the timing signal input terminal * T, the signal is generated in response to the falling edge E10 of the reference clock S1 as shown in FIG. S200 does not stand up.

Rising edge E of asynchronous input signal S2
In response to S22, all D-type flip-flops 200 to 208 are reset. Therefore, at this time, the signals S202 and S203 become "L". In response to "L" of the signal S202, the signal S301 becomes "L", and the signal S
The clock at 402 is stopped. Then, the next asynchronous input signal S2 (the asynchronous input signal S2 via the buffer
Waiting for the falling edge of b) to arrive. Even with such a configuration, the same synchronization clock S3 as that shown in FIG.
Is obtained.

FIG. 14 is a circuit diagram showing a third embodiment of the synchronous clock generating circuit according to the present invention. This example
By configuring the synchronous clock generating circuit X using a plurality of the synchronous clock generating circuits shown in FIGS. 1 and 2, a plurality of synchronous clock outputs are obtained for a plurality of asynchronous input signals. As shown in the figure, the delay clock generation circuit 10 is shared and only one is provided. n
Storage circuits 20a to 20n and n phase detection circuits 30
a to 30n and n clock selection circuits 40a to 40
n is provided. The configurations of the storage circuits and the phase detection circuits are the same as those of the storage circuit 20 and the phase detection circuit 30 shown in FIG. 1, and the configurations of the clock selection circuits are the same as the configuration of the clock selection circuit 40 shown in FIG. Storage circuit 20a, phase detection circuit 30a and clock selection circuit 40a set, storage circuit 20b, phase detection circuit 30b and clock selection circuit 40b set, ... Storage circuit 20n, phase detection circuit 30n
Each of the sets of the clock selection circuit 40n and the clock selection circuit 40n corresponds to the storage circuit 20, the phase detection circuit 30, and the clock selection circuit 40 of FIGS.

Next, the operation will be described with reference to FIG. FIG. 15 is a timing chart for explaining the operation of the circuit shown in FIG. Reference clock input terminal 1
When the reference clock S1 as shown in FIG. 15 and the asynchronous signals S2a to S2n as shown in FIG. 15 are input to the asynchronous signal input terminals 2a to 2n, respectively, the synchronization is performed by the operation described in FIGS. The signal output terminals 3a to 3n are shown in FIG.
The n synchronization clocks S3a to S3n as shown in FIG. Since the delay clock generation circuit 10 is commonly used as one, a plurality of synchronization clocks S3 are generated using the common delay clock generated from the delay clock generation circuit 10.
a to S3n can be generated. Therefore, compared with the case where a plurality of delay clock generation circuits 10 are used to generate a plurality of synchronous clocks, the delay clocks due to variations between the delay clock generation circuits (for example, variations in delay values of delay elements inside the delay clock generation circuit 10) It is possible to suppress the duty change and the like.

Further, by making the delay clock generation circuit 10 common, the circuit scale can be reduced as compared with the case where a plurality of delay clock generation circuits are used, and the size of the semiconductor integrated circuit can be reduced when integrated. Due to such size reduction, the storage circuits 20a to 20n and the phase detection circuit 3
By forming the 0a to 30n and the clock selection circuits 40a to 40n on a small area, it is possible to suppress delay time variations and reduce costs. In particular, the suppression of the delay time variation suppresses the variation of the delay times T3a to T3n between the synchronous clocks S3a to S3n shown in FIG. 15, and the variation of the synchronous clocks generated by each of the plurality of synchronous clock generation circuits can be prevented.

Further, in the synchronous clock generation circuit of FIGS. 1 and 2, when the first asynchronous input signal S2 is input to the asynchronous signal input terminal 2, the first synchronous clock S3 is output in response to this. Then, when the second asynchronous signal S2 is input, the second asynchronous input signal S is replaced with the first asynchronous clock S3 from the synchronous clock output terminal 3.
2nd synchronous clock S3 corresponding to 2 is output,
Cannot hold the synchronous clock S3. With the above configuration, the synchronous clock S3a is provided for the asynchronous input signal S2a, the synchronous clock S3b is provided for the asynchronous input signal S2b, and so on. Synchronous clock output terminal 3a
Can be maintained at ~ 3n.

FIG. 16 is a circuit diagram showing a fourth embodiment of the synchronous clock generating circuit according to the present invention. FIG. 17 shows FIG.
3 is a timing chart for explaining the operation of the circuit shown in FIG. In this embodiment, a distributor 60 is newly added to the embodiment shown in FIG. A plurality of asynchronous signals are input to the distributor 60 from the asynchronous signal input terminal 2.
The distributor 60 distributes this signal to the respective asynchronous input signals S2a to S2n in the order of input as shown in FIG. Each of the distributed signals is input to the asynchronous signal input terminals 2a to 2n of the synchronous clock generation circuit X. The subsequent operation is shown in Figure 1.
The operation is similar to that of the circuit shown in FIG. With such a configuration, even when there is one asynchronous signal input terminal, the same effect as that of the embodiment shown in FIG. 14 can be obtained.

FIG. 18 is a block diagram showing a first embodiment of a delay pulse generating circuit according to the present invention, which uses the above-described synchronous clock generating circuit. As shown in the figure, the reference clock input terminal 1 is connected to one input terminal of the synchronous clock generating circuit X. Also, the asynchronous signal input terminal 2
Is connected to the other input terminal of the synchronous clock generation circuit X and the reset signal input terminal 9 of the pulse generation circuit 5.
Further, the synchronous clock S3, which is the output of the synchronous clock generating circuit X, is given to the pulse generating circuit 5. Also,
Pulse set / reset value input terminal 7, pulse set /
The reset value clock input terminal 8 is connected to the pulse generation circuit 5.

The structure of the synchronous clock generating circuit X shown in FIG. 18 is the same as that of the synchronous clock generating circuit shown in FIGS. The operation of the synchronous clock generation circuit X in this case is similar to the operation described with reference to FIGS. 1 and 2 (see FIG. 3).

FIG. 19 is a block diagram showing details of the pulse generating circuit 5 shown in FIG. As shown in the figure, the synchronous clock input terminal 3 is connected to the count input terminal of the counter 50. Further, the reset signal input terminal 9 is connected to the reset input terminal R of the counter 50. Further, the pulse set / reset value input terminal 7 and the pulse set / reset value clock input terminal 8 are connected to the data input terminal D and the clock input terminal CLK of the shift register 51, respectively.

The output terminal of the counter 50 is the coincidence detection circuit 5
It is connected to one of the input terminals of 2, 53. The shift register 5 is connected to the other input terminals of the coincidence detection circuits 52 and 53.
1 set value register 51a, reset value register 5
Output terminals 1b are connected to each other. The output terminals of the coincidence detection circuits 52 and 53 are the selector 5 respectively.
It is connected to 4, 55 select input terminals S. The output terminals of the selectors 54 and 55 are connected to the data input terminals D of the D flip-flops 56 and 57, respectively.
The output terminals Q of the D flip-flops 56 and 57 are connected to the input terminals 0 of the selectors 54 and 55, respectively. The input terminal 1 of the selectors 54 and 55 is connected to the power supply terminal. Further, the synchronous clock input terminal 3 is connected to the negative logic trigger signal input terminals * T of the D flip-flops 56 and 57. Furthermore, D flip-flops 56 and 57
The reset input terminal R is connected to the reset signal input terminal 9. The output terminal Q of the D flip-flop 56 is connected to one input terminal of the AND circuit 58, and the output terminal Q of the D flip-flop 57 is inverted and connected to the other input terminal of the AND circuit 58. Furthermore, AND circuit 5
8 output terminals are connected to the delayed pulse output terminal 6.

Next, the operation of the pulse generating circuit 5 shown in FIG. 19 will be described. FIG. 20 is a timing chart showing the operation of the pulse generation circuit 5 of FIG. First, the pulse set value and the pulse reset value are input from the pulse set / reset value input terminal 7 to the data input terminal D of the shift register 51 as serial data. The shift register 51 has a pulse set / reset value clock input terminal 8 supplied to its clock input terminal CLK.
The pulse set value and the pulse reset value are shifted by the clock input from the set value register 51a and the reset value register 51b as parallel data, respectively.
Set to.

To simplify the explanation, it is now assumed that "3" is preset in the set value register 51a and "5" (both decimal numbers) in the reset value register 51b in the shift register 51.

While the reset signal S9 supplied from the reset signal input terminal 9 is at "H" level, the counters 50, D
The flip-flops 56 and 57 are in the reset state, the count value of the counter 50 is 0, and the D flip-flops 56 and 5 are
Signals S56 and S respectively output from the output terminal Q of 7
57 is at "L" level. Next, the reset signal S9 goes to "L" level, and the reset of the counter 50 and the D flip-flops 56, 57 is released. At this time, when the synchronous clock S3 is input from the synchronous clock output terminal 3, the counter 50 starts counting the synchronous clock S3. This count value is the coincidence detection circuit 5
2 and 53, and the match detection circuits 52 and 53 are set value register 51a and reset value register 51, respectively.
When the set value or reset value preset in b matches the count value of the counter 50, an "H" level signal is generated from its output terminal. Set value register 51
a, the reset value register 51b has "3",
Since "5" is set, the output S52 of the coincidence detection circuit 52 is at "H" level when the count value of the counter 50 is "3", and the output S53 of the coincidence detection circuit 53 is at the count value of the counter 50. When it is 5 ", it becomes" H "level.

The selectors 54 and 55 change the signals applied to the input terminal 1 when the outputs S52 and S53 of the coincidence detection circuits 52 and 53 applied to the set input terminal S are "H" level, that is, "H" level. Output from the output terminal. Input terminal 0 when S52 and S53 are at "L" level.
The signal given to is output from the output terminal.

Therefore, the signal S56 output from the output terminal Q of the D flip-flop 56 is the reset signal S applied from the reset input terminal 9 as shown in the figure.
9 is at the "H" level, and is at the "L" level until the falling of the synchronous clock S3 immediately before the count value of the counter 50 becomes "3" after the reset signal S9 becomes the "L" level. Further, it goes to "H" level from the fall of the synchronous clock S3 immediately after the count value of the counter 50 reaches "3" until the reset signal S9 goes to "L" level again. Similarly, the signal S57 output from the output terminal Q of the D flip-flop 57 is, as shown in the figure, when the reset signal S9 supplied from the reset input terminal 9 is at "H" level and when the reset signal S9 is reset.
Becomes "L" level until the falling edge of the synchronous clock S3 immediately before the count value of the counter 50 becomes "5". Further, it goes to "H" level from the fall of the synchronous clock S3 immediately after the count value of the counter 50 reaches "5" until the reset signal S9 goes to "L" level again.

The signal S56 from the AND circuit 58 is "H".
When the level and the signal S57 are "L" level, a signal of "H" level is output, so that the delay pulse output terminal 6 outputs the delay pulse S6 as shown in the figure.

The synchronous clock generating circuit X shown in FIG. 3 (operation timing chart of the synchronous clock generating circuit shown in FIGS. 1 and 2) and the synchronous clock generating circuit X shown in FIG. 20 (circuits shown in FIGS. 1 and 2) is used. ), Considering the operation of the pulse generation circuit 5, the operation of the delayed pulse generation circuit shown in FIG. 18 will be described. FIG. 21 is a timing chart showing the operation of the delay pulse generating circuit shown in FIG. The synchronous clock S3 generated from the reference clock S1 is at "L" level while the asynchronous signal S2 is at "H" level, and is synchronized with the asynchronous signal S2 with high accuracy when the asynchronous signal S2 is at "H" level.

The delay pulse S6 output from the delay pulse output terminal 6 is synchronized with the falling edge of the synchronization clock S3, depending on the pulse set value input from the pulse set / reset value input terminal 7, for example, the synchronization clock S6.
It is set at the third pulse of the pulse No. 3 (becomes "H" level), and the pulse reset value input from the pulse set / reset value input terminal 7 causes
It is reset at the 5th shot of the 3rd pulse. (It becomes "L" level.) Since the edge precision of the delay pulse S6 is equal to that of the synchronizing clock S3, a very high precision delay pulse can be obtained.

Further, only by changing the pulse set value and the pulse reset value input from the pulse set / reset value input terminal 6, the set timing of the delay pulse S6 for the asynchronous signal S2 (that is, the delay value for the asynchronous signal S2) and Each reset timing (that is, the pulse width of the delay pulse S6 from the set timing) can be controlled.

As described above, according to the first embodiment of the delay pulse generating circuit shown in FIG. 18, the synchronous clock generating circuit X generates the synchronous clock S3 synchronized with the falling edge of the asynchronous signal S2 with high precision. Occur. The pulse generator 5 delays the falling edge of the asynchronous signal S2 by the same number of pulses of the synchronous clock S3 as the pulse set value input from the pulse set / reset value input terminal 7, and then sets the delayed pulse S6. The pulse resetting of the delay pulse S6 is performed after delaying by the same number of pulses of the synchronization clock S3 as the pulse reset value input from the pulse set / reset value input terminal 7.

However, in the delay pulse generating circuit shown in FIG. 18, the synchronous clock S3 synchronized with the asynchronous signal S2 in the timing chart shown in FIG. 21 stops at the next rising edge E20 of the asynchronous signal S2. Therefore, the delay pulse S6 is set or reset in time after the rising edge E20 of the asynchronous signal S2, that is, the rising edge E2 of the asynchronous signal S2.
Even if the delay pulse S6 is delayed until the timing after 0, or even if the leading edge of the delay pulse S6 is formed at the timing before the rising edge E20 of the asynchronous signal S2, the trailing edge is after the rising edge E20 of the asynchronous signal S2. Could not be set.

FIG. 22 is a block diagram showing a second embodiment of the delay pulse generating circuit according to the present invention for solving such a problem. As shown in the figure, the asynchronous signal input terminal 2 is connected to the asynchronous signal distribution circuit 60. Further, the first and second output terminals of the asynchronous signal distribution means 60 are connected to one input terminals of the synchronous clock generation circuits Xa and Xb, respectively. The reference clock input terminal 1 is connected to the other input terminals of the synchronous clock generation circuits Xa and Xb. Synchronous clock generation circuit Xa, X
The output terminals of b are connected to the input terminals of the pulse generating circuits 5a and 5b, respectively. Pulse generation circuits 5a and 5b
Each pulse set / reset value input terminal 7a. 7
A pulse set / reset value input terminal 7 is connected to b. The pulse set / reset value clock input terminals 8a. A pulse set / reset value clock input terminal 8 is connected to 8b. Further, the asynchronous signal input terminal 2 is connected to the reset signal input terminal 9 of each of the pulse generation circuits 5a and 5b.

The output terminals of the pulse generation circuits 5a and 5b are O.
The OR circuit 63 is connected to the input terminal of the R circuit 63.
Is connected to the delayed pulse output terminal 6.
The synchronous clock generating circuits Xa and Xb and the pulse generating circuits 5a and 5b have the same configurations as the synchronous clock generating circuit X and the pulse generating circuit 5 shown in FIG. 18, respectively.

FIG. 23 is a timing chart showing the operation of the delay pulse generating circuit shown in FIG. The asynchronous signal S2 input from the asynchronous signal input terminal 2 is distributed to the odd-numbered and even-numbered pulses of the pulse by the asynchronous signal distribution circuit 60, and as signals S60a and S60b, respectively,
It is applied to the synchronous clock generation circuits Xa and Xb. The synchronous clock generation circuits Xa and Xb independently generate the synchronous clocks S3a and S3b which are highly accurately synchronized with the odd-numbered and even-numbered pulses of the asynchronous signal distribution circuit 60.

The pulse generating circuit 5a is set by the pulse set value input from the pulse set / reset value input terminal 7a, for example, at the third shot of the synchronous clock S3a, and input from the pulse set / reset value input terminal 7a. Depending on the pulse reset value, the delay pulse S5a that is reset at the fifth generation is generated, for example. Similarly, the pulse generation circuit 5b has a pulse set / reset value input terminal 7
In response to the pulse set value input from b, the synchronization clock S3b is set at the third pulse, for example, and at the fifth pulse corresponding to the pulse reset value input from the pulse set / reset value input terminal 8a. A delayed pulse S5b to be reset is generated.

Since the delay pulses 5a and 5b are given to the OR circuit 63, respectively, the OR circuit 63 outputs the delay pulse S6 as shown in the figure.

In this embodiment, the synchronous clocks S3a, S3
Since 3b is output over two cycles of the asynchronous signal S2, the timing of setting or resetting the delay pulse can be set to be twice as large as that of the first embodiment.

Note that, although FIG. 22 shows an example in which the asynchronous signal S2 is divided into two by the asynchronous signal distribution circuit 60, if the asynchronous signal S2 is divided into n, the delay amount of the delay pulse or the reset thereof can be calculated. It can be set up to be about n times larger than that of the first embodiment.

The synchronous clock generating circuit is not limited to the configuration shown in FIGS. 1 and 2 as long as it generates the synchronous clock S3 in synchronization with the edge of the input signal such as the asynchronous signal S2.

Further, the pulse generation circuit uses the asynchronous signal S
Synchronous clock S in synchronization with the edge of the input signal such as 2
3 is counted, the delay pulse is set when the count number reaches a predetermined value, and the delay pulse is reset when the count number reaches another predetermined value. However, the configuration is not limited to that shown in FIG.

Next, a latch circuit suitable for use as the D type flip-flops 200 to 208 of the synchronous clock generating circuit shown in FIGS. 1 and 2 will be described. First, FIG. 24 shows a general latch circuit with reset as a background of the latch circuit according to the present invention.

As shown in the figure, the input signal terminal 100 is connected to the input terminal of the reading gate 500 constituted by the transmission gate, and the output signal line of the reading gate 500 and the latch constituted by the transmission gate. The output signal line of the gate 700 is connected to one input terminal of the NAND circuit 800.

The control signal terminal 2000 is connected to the N-channel gate of the read gate 500 and the P-channel gate of the latch gate 700.

The control signal terminal 2000 is connected to the input terminal of the inverter 600, and the output of the inverter 600 is given to the P channel gate of the read gate 500 and the N channel gate of the latch gate 700.

The reset input terminal 3000 is set to NAN.
It is connected to the other input terminal of the D circuit 800 and has an NA
The output of the ND circuit 800 is given to the input of the inverter 900.

Further, the output of the inverter 900 is given to the latch output terminal 400 and the input of the latch gate 700.

The latch gate 700, the NAND circuit 800 and the inverter 900 are the positive feedback loop 1000.
Are configured.

FIG. 25 is a circuit diagram showing a general master / slave flip-flop with reset, which is the background of the latch circuit according to the present invention.

As shown in the figure, the input signal terminal 100 is connected to the input terminal of the master side reading gate 500m constituted by a transmission gate,
The output signal line of the master side reading gate 500m and the output signal line of the master side latching gate 700m formed by a transmission gate are connected to each other and connected to one input terminal of the master side NAND circuit 800m.

The master side reading gate 500 m
N channel gate and master side latch gate 700m
Control signal terminal 2000 on the P channel gate of
Are connected.

The control signal terminal 2000 is connected to the input terminal of the master side inverter 600m, and the output of this master side inverter 600m is the P channel gate of the master side reading gate 500m and the N side gate of the master side latching gate 700m. Is given to.

Further, the reset input terminal 3000 is connected to the other input terminal of the master side NAND circuit 800m, and the output of the master side NAND circuit 800m is given to the input of the master side inverter 900m.

Further, the output of the master-side inverter 900m is provided to the input of the master-side latch gate 700m and the transmission gate, but is given to the input of the slave-side read gate 500s.

Further, the slave side reading gate 500
The output signal line of s and the output signal line of the slave side latch gate 700s configured by the transmission gate are connected to one input terminal of the slave side NAND circuit 800s.

Further, the slave side reading gate 500
s P channel gate and slave side latch gate 70
A control signal terminal 20 is provided for the 0s N-channel gate.
00 is connected.

The control signal terminal 2000 is connected to the input terminal of the slave side inverter 600s, and the output of this slave side inverter 600s is the N channel gate of the slave side read gate 500s and the P channel gate of the slave side latch gate 700s. Is given to.

Further, the reset input terminal 3000 is connected to the other input terminal of the slave side NAND circuit 800s, and the output of the slave side NAND circuit 800s is given to the input of the slave side inverter 900s.

Further, the output of the slave side inverter 900s is given to the input of the slave side latch gate 700s and the latch output terminal 400.

The master side latch gate 700m,
The master side NAND circuit 800m and the master side inverter 900m include a master positive feedback loop 1000m, a slave side latch gate 700s, and a slave side NAND circuit 8m.
00s and the slave-side inverter 900s constitute a slave positive feedback loop 1000s, and the master-side reading gate 500m, the master-side inverter 600m, and the master positive-feedback loop 1000m are the master latch circuit 1
100 is a slave side reading gate 500s, a slave side inverter 600s, and a slave positive feedback loop 1
000s constitutes a slave latch circuit 1200.

Next, the operation will be described.

Since the latch circuit with reset in FIG. 24 has the same circuit configuration as the master latch circuit 1100 in the master / slave flip-flop with reset in FIG. 25, the master / slave flip-flop with reset in FIG. 25 will be described below. To do. Also, since the master latch circuit 1100 and the slave latch circuit 1200 have almost the same circuit configuration, the master latch circuit 1100 is mainly used.
However, the slave latch circuit 1200 also performs the same operation except that the timing is different.

When the control signal applied to the control signal terminal 2000 is at the "H" level, the master side read gate 500m and the slave side latch gate 700s are enabled, and the master side latch gate 700m and the slave side read gate 700m. Gate 500
s is disabled.

The level of the reset signal applied to reset signal terminal 3000 is "H".

At this time, the data supplied to the input signal terminal 100 is output from the master side inverter 900m via the master side reading gate 500m and the master side NAND circuit 800m.

In the slave latch circuit 1200, before the control signal becomes "H", the input signal terminal 10
Data given from 0 is slave positive feedback loop 100
Latched within 0s.

Next, when the control signal applied to the control signal terminal 2000 is inverted to the "L" level, the master side read gate 500m and the slave side latch gate 700s are disabled and the master side latch The gate 700m for reading and the gate 500s for reading on the slave side are enabled.

In this state, the master latch circuit 1100 latches the output signal of the master side inverter 900m before the output of the control signal terminal 2000 becomes "L" in the master positive feedback loop 1000m.

In the slave latch circuit 1200, the signal latched by the master positive feedback loop 1000m, that is, the output signal of the master-side inverter 900m is supplied to the slave-side reading gate 500s and the slave-side NAN.
The data is output from the latch output terminal 400 via the D circuit 800s and the slave-side inverter 900s.

In the conventional master / slave flip-flop with reset, the master side reading gate 500 m
In order to shorten the propagation delay time until the signal input to the master side inverter 900m is output and the output signal of the master side inverter 900m is input to the slave side reading gate 500s and output from the latch output terminal 400, The master-side read gate 500m and the slave-side read gate 500s are increased in transistor size, and the master-side latch gate 700m and the slave-side latch gate are prevented from increasing the chip size of a semiconductor integrated circuit or the like. 7
The transistor size of 00s is set small.

Therefore, the master side reading gate 50
The relationship of (output impedance of master side reading gate 500m) <(output impedance of master side latching gate 700m) is established between the output impedance of 0m and the master side latching gate 700m, and the slave side reading gate 500
The relationship of (output impedance of slave side reading gate 500s) <(output impedance of slave side latching gate 700s) is established between the output impedances of s and the slave side latching gate 700s.

Therefore, "H" is applied to the input signal terminal 100 to release the reset signal applied from the reset input terminal 3000 and to shift the control signal applied from the control signal terminal 2000 from "H" to "L". It occurs almost at the same time, and the master side reading gate is 500m
When the master side latch gate 700m and the master side latch gate 700m are momentarily simultaneously enabled, the master side read gate 5
00m output signal line and master side latch gate 700m
At the connection point 1300m with the output signal line of the above, the output of the master side reading gate 500m collides with the output of the master side latching gate 700m having the opposite polarity.

Here, the master side latch gate 700 m
Output impedance of the master side reading gate 50
Since it is larger than the output impedance of 0 m, the master side latch gate 700 m has a small ability to change the potential of the connection point 1300 m to “H”, and the potential of the connection point 1300 m holds the intermediate potential for a long time.

Therefore, it has been specified that a sufficient recovery time is provided between the release of the reset signal and the transition of the control signal from "H" to "L". The standard value of the 74HC series, which is the standard logic, is 5 ns.

FIG. 26 shows such a master with reset.
FIG. 3 is a circuit diagram using a D-type flip-flop showing an application example of a slave flip-flop, and this D-type flip-flop is the D flip-flop 2 shown in FIG. 1.
Conventionally used for 00-208.

Each D type flip-flop 25a to 2
5e is the master / slave flip-flop with reset of FIG. 25, the clock terminal 24 is the control signal terminal 2000 of FIG. 25, the reset terminal 23 is the reset input terminal 3000 of FIG. 25, and each D-type flip-flop 2 is connected.
The data input terminal D of 5a to 25e corresponds to the input signal terminal 100 of FIG. 25, and the data output terminal Q corresponds to the latch output terminal 400 of FIG.

The clock signal supplied from the clock terminal 24 is delayed by the delay elements 26a, 26b, 26c, 26d and 2.
Delayed by 6e. The clock signal itself supplied from the clock terminal 24 is input to the clock input terminal T of the D-type flip-flop 25a, the output of the delay element 26a is input to the clock input terminal T of the D-type flip-flop 25b, and the output of the delay element 26b is output to the D-type flip-flop. The output of the delay element 26c is applied to the clock input terminal T of the D-type flip-flop 25d, the output of the delay element 26d is applied to the clock input terminal T of the D-type flip-flop 25e, to the clock input terminal T of 25c.

Further, the reset terminal 23 is connected to the reset terminals R of the D type flip-flops 25a to 25e.

In the initial state, the reset signal applied from the reset terminal 23 is at "L" level, and the D type flip-flops 25a to 25e are in the reset state.

The clock signal is input to the clock terminal 24, the delay clocks are generated by the delay elements 26a to 26e, and the delay clocks having different phases are input to the clock input terminals T of the flip-flops 25a to 25e. Has been done.

The reset is released by changing the reset terminal 23 from the "L" level to the "H" level, and the outputs of the D type flip-flops 25a to 25e are closest to each other in time when the reset is released. The data output terminal Q of the D type flip-flop input at the falling edge of is first set to the “H” level, which detects which delay element corresponds to which falling element of the clock signal when the reset signal is released. can do.

In such a specification, close or simultaneous occurrence of the reset signal release and the clock signal transition from "H" to "L" may occur in any D type flip-flop.

In the conventional master / slave flip-flop with reset having the transistor size, when the release of the reset signal and the transition of the control signal from "H" to "L" are input closely, the control signal terminal The propagation delay time from the transition of the signal applied to 2000 from “H” to “L” to the signal output to the latch output terminal 400 becomes long.

FIG. 27 is a timing chart showing simulation results of the master / slave flip-flop with reset shown in FIG.

In the state where the “H” is given to the input signal terminal 100, the reset signal release and the control signal transition from “H” to “L” are input closely, so that the master latch circuit 1100 Positive feedback loop 100
Master side NAND circuit 800m constituting 0m, master side inverter 900m, master side latch gate 700
There is a long period in which the output potentials Ve, Vf, and Vd of m are at intermediate voltages of 2.0 V to 2.5 V near the threshold voltage. This is the control signal terminal 200
This causes the propagation delay from the transition of the control signal from 0 from “H” to “L” to the output of the latch signal from the latch output terminal 400 to be long.

Since the conventional latch circuit is configured as described above, when the release of the reset signal and the transition of the control signal from "H" to "L" occur close in time, the control signal of the control signal is changed. There is a problem that it is difficult to realize a high-speed latch operation because the propagation delay time from the transition to the output of the latch signal becomes long. for that reason,
When the D-type flip-flops to which the master / slave flip-flops using this latch circuit are applied are used for the D-type flip-flops 200 to 208 shown in FIG. 1, there is a problem that a high-speed synchronous clock generating operation cannot be performed. In order to solve this problem, the present invention improves the latch circuit as described below.

FIG. 24 is a circuit diagram showing a general latch circuit with a reset which is the background of the latch circuit according to the present invention as described above, and FIG. 25 is a general background of the latch circuit according to the present invention as described above. Master with automatic reset
It is a circuit diagram which shows a slave flip-flop.

Since the circuits of FIGS. 24 and 25 have already been described, the description thereof will be omitted here.

In the present embodiment, in the circuit of FIG. 24, the output impedance between the read gate 500 and the latch gate 700 is different from the conventional one (the output impedance of the read gate 500)>
(Output impedance of the latch gate 700) is set so as to hold. In the circuit of FIG. 25, between the output impedances of the master side reading gate 500m and the master side latching gate 700m, (the output impedance of the master side reading gate 500m)> (the output of the master side latching gate 700m (Impedance) relationship holds, and slave side reading gate 500
s and the output impedance of the slave side latch gate 700s are set so that the same relationship as the conventional one (output impedance of the slave side read gate 500s) <(output impedance of the slave side latch gate 700s) is established. To do.

Since the latch circuit with reset in FIG. 24 has the same circuit configuration as the master latch circuit 1100 in the master / slave flip-flop with reset in FIG. 25, the master / slave flip-flop with reset in FIG. 25 will be described below. To do.

The output impedance of the master side reading gate 500m is the same as the master side reading gate 500m.
The output impedance of the master-side latch gate 700m is determined by the transistor size of the driver that gives an input signal to the input signal terminal 1 connected to the And the transistor size of the master-side latch gate 700m.

Similarly, the slave side reading gate 50
The output impedance of 0 s is determined by the transistor size of the master-side inverter 900 m and the transistor size of the slave-side read gate 500 s connected to the input of the slave-side read gate 500 s, and the output impedance of the slave-side latch gate 700 s is , The transistor size of the slave-side inverter 900s and the transistor size of the slave-side latch gate 700s.

By setting the output impedance as described above, when the master-side latch gate 700m and the master-side read gate 500m are momentarily simultaneously enabled, the master-side latch gate 70
The output potential of 0 m becomes superior to the output potential of the master side reading gate 500 m, and the potential of the connection point 1300 m of the output signal line between the master side latching gate 700 m and the master side reading gate 500 m becomes the intermediate potential. Can be prevented.

FIG. 28 is a timing chart showing the circuit simulation result of the master / slave flip-flop with reset under such a condition.

First, in the initial state, the reset input terminal 3
The level of the reset signal given from 000 is "L",
The level of the control signal supplied from the control signal terminal 2000 is "H", and the input signal terminal 1
The level of the input signal supplied from 00 is fixed to "H".

At this time, the master / slave flip-flop with reset is in the reset state, and the potential Vc of the latch output signal output from the latch output terminal 400 is "L".

The master side reading gate 500 m
Is in an enabled state, and the master side latch gate 700m is in a disabled state. Therefore, the potential Vd at the connection point 1300m of the output signals of the master side read gate 500m and the master side latch gate 700m is “H”, and the master side inverter is The potential Vf of the output of 900 m is "L".

Next, when the operation is started, first, the potential Va of the reset signal applied from the reset input terminal 3000 changes from "L" to "H", and at the same time, the signal output from the master side NAND circuit 800m. Of the signal Ve from the master side inverter 900m starts to change from "L" to "H".

Here, at almost the same time when the potential Va of the reset signal changes from "L" to "H", the control signal terminal 2
If the potential Vb of the control signal given from 000 changes from "H" to "L", the master side reading gate 500m changes from the enable state to the disable state, and the master side latching gate 700m changes from the disable state to the enable state. Begins to change to.

As a result, the potential Vf of the output signal of the master-side inverter 900m in the initial state, that is, "L", is output via the master-side latch gate 700m to the output signal line of the master-side read gate 500m and the master-side latch gate. It is transmitted to the connection point 1300m with the 700m output signal line.

At this connection point 1300m, the "L" level output from the master-side inverter 900m supplied via the master-side latch gate 700m and the input signal terminal 100 supplied via the master-side read gate 500m. It collides with the "H" level input to and the connection point 1
The potential Vd of 300 m becomes an intermediate potential.

After that, the master side reading gate 500
The “H” level that is the output of m is the inverter 90 on the master side.
It reaches the output of 0m and the master side latch gate 700
The potential Vd of the connection point 1300m becomes “H” via m.

Here, the master side latch gate 700 m
Output impedance of the master side reading gate 50
When the output impedance is larger than 0 m, the master side latch gate 700 m has a small ability to change the potential Vd at the connection point 1300 m to “H”, and as described in the prior art, the master side read gate 500 m is disconnected. Master positive feedback loop 100 even after the enable state
The potentials Vd, Ve and Vf within 0m all hold the intermediate potential for a long period of time.

In this embodiment, since the output impedance of the master side latch gate 700m is made smaller than the output impedance of the master side read gate 500m, the potential Vf of the output signal of the master side inverter 900m.
Can shorten the time required to become "H",
As a result, each potential V in the master positive feedback loop 1000m
The levels of d, Ve and Vf are determined more quickly.

As described above, in this embodiment, the output impedance of the master-side latch gate 700m is made smaller than the output impedance of the master-side read gate 500m.
m output signal and master side reading gate 500m of the opposite polarity to the output signal of the master side latch gate 500
0m output signal line and master side reading gate 500m
When a collision occurs at the connection point 1300m of the output signal line of, the level of the output signal of the master side latch gate 700m becomes the potential of the connection point 1300m, which shortens the propagation delay time from the transition of the control signal to the output of the latch signal. can do.

The output impedance of the slave side reading gate 500s is the slave side latching gate 700s.
Is smaller than the output impedance of
This is because the latch data of the master latch circuit 1100 is output from the latch output terminal 400 with a short propagation delay time when the slave side read gate 500s and the slave side latch gate 700s are simultaneously enabled.

Due to the synergistic effect of this and the relationship of the output impedances of the master side reading gate 500m and the master side latching gate 700m described above, the reset signal is released and the control signal when the control signal is input close to each other. The propagation delay time of the latch output can be shortened. High-speed synchronous clock generation can be achieved by using the D flip-flop to which the master / slave flip-flop using the latch circuit in this embodiment is applied in the synchronous clock generating circuit of FIGS.

In this embodiment, the master / slave flip-flop with reset is shown. However, the master / slave flip-flop with set, the JK flip-flop with reset or the set, the T flip-flop with set or the other latch. The same effect is obtained in the circuit.

[0194]

According to the synchronous clock generating circuit of the present invention, the reference clock is sequentially inverted by the plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. And a storage means comprising a plurality of storage elements for outputting the data supplied to the data input terminal from the output terminal in response to the reference clock and the plurality of non-inverted or inverted delayed clocks, and the output terminals of the adjacent storage elements. A plurality of non-inverted signals are compared by comparing the output signals with each other and applying the comparison signal as the comparison result to one data input terminal of one of the adjacent storage elements and the comparison signal output by the phase detection means. Alternatively, since the selecting means for deriving the synchronous clock by selecting one of the inverted delay clocks is provided,
There is an effect that a highly accurate synchronous clock can be generated without requiring a high frequency clock generation circuit.

According to another aspect of the synchronous clock generation circuit of the present invention, the reference clock is sequentially inverted by the plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. In response to a reference clock and multiple non-inverted or inverted delayed clocks,
Comparing the storage means composed of a plurality of storage elements for outputting the data given to the data input terminal from the output terminal and the signals output from the output terminals of the adjacent storage elements,
One of a plurality of inverted or non-inverted delay clocks is designated by the phase detection means for giving the comparison signal as the comparison result to one data input terminal of the adjacent storage element and the comparison signal output by the phase detection means. Selecting means for selecting one of the plurality of inverted or non-inverted delayed clocks as a synchronous clock according to a predetermined priority by using a comparison signal when there are a plurality of selected ones. Since the and are provided, a high-precision synchronous clock can be generated without the need for a high-frequency clock generation circuit, and a plurality of designated inverted or non-inverted delayed clocks can be prevented from being multiplexed and output as a synchronous clock. This has the effect of making the duty of the synchronous clock equal to the duty of the reference clock.

According to another aspect of the synchronous clock generation circuit of the present invention, the reference clock is sequentially inverted by the plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. In response to the non-identical input signal, the storage means composed of a plurality of storage elements for outputting the data given to the data input terminal from the output terminal is compared with the signals output from the output terminals of the adjacent storage elements. A phase detection means for outputting a comparison signal as the comparison result, and a selection means for selecting one of a plurality of inverted or non-inverted delayed clocks to derive a synchronous clock according to the comparison signal output by the phase detection means. Therefore, there is an effect that a highly accurate synchronous clock can be generated without requiring a high frequency clock generation circuit.

According to another aspect of the synchronous clock generating circuit of the present invention, the reference clock is sequentially inverted by the plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. In response to the asynchronous input signal, the storage means composed of a plurality of storage elements for outputting the data supplied to the data input terminal from the output terminal and the signals output from the output terminals of the adjacent storage elements are compared with each other. Phase detection means for outputting the comparison result,
According to the comparison signal output from the phase detection means, a designated one of the plurality of inverted or non-inverted delay clocks is selected, and when there are a plurality of selected ones, the comparison signal is used to give a predetermined priority. Since the selection means for deriving according to the order is provided, a high-precision synchronous clock can be generated without the need for a high-frequency clock generation circuit, and a plurality of designated inverted or non-inverted delayed clocks are multiplexed as a synchronous clock. By preventing the output, the duty of the synchronous clock can be made equal to the duty of the reference clock.

According to the synchronous clock generating circuit of the fifth aspect, one inverting delay means for sequentially inverting the reference clock by the plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. And a plurality of storage means composed of a plurality of storage elements for outputting the data supplied to the data input terminal from the output terminal in response to the reference clock and the plurality of non-inverted or inverted delayed clocks, and the outputs of the adjacent storage elements. By comparing the signals output from the terminals, a plurality of phase detection means for giving the comparison signal as the comparison result to one of the data input terminals of the adjacent storage elements, and the comparison signal output by the phase detection means, Since a plurality of selecting means for selecting one of a plurality of inverted or non-inverted delayed clocks to derive a synchronous clock is provided. It is possible to produce a highly accurate synchronous clock without requiring a high-frequency clock generating circuit, there is an effect that it is possible to suppress the variation among the plurality of synchronous clock generated. Further, the synchronization accuracy of the synchronization clock can be made equal to the delay value of two stages of inverting delay elements, and the operation can be performed based on a common inverting or non-inverting delay clock from one inverting delay means, and one inverting delay means can be operated. It is possible to derive a plurality of synchronous clocks by operating on the basis of a common inverted or non-inverted delayed clock from

According to the synchronous clock generating circuit of the sixth aspect, one inverting delay means for sequentially inverting the reference clock by the plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks. And a plurality of storage means composed of a plurality of storage elements for outputting the data supplied to the data input terminal from the output terminal in response to the reference clock and the plurality of non-inverted or inverted delayed clocks, and the outputs of the adjacent storage elements. By comparing the signals output from the terminals, a plurality of phase detection means for giving the comparison signal as the comparison result to one of the data input terminals of the adjacent storage elements, and the comparison signal output by the phase detection means, Selects the specified one of multiple inverted or non-inverted delayed clocks, and if there are multiple selected ones, Since a plurality of selecting means for deriving one of a plurality of inverted or non-inverted delayed clocks as a synchronous clock according to a predetermined priority using a signal is provided, a high frequency clock generation circuit is not required. High-precision synchronous clock can be generated, and the synchronous clock duty is made equal to the reference clock duty by preventing multiple specified inverted or non-inverted delayed clocks from being multiplexed and output as the synchronous clock. In addition to the effect that it is possible, it is possible to suppress the variation between the plurality of generated synchronous clocks. Further, the synchronization accuracy of the synchronization clock can be made equal to the delay value of two stages of the inversion delay element, and the plurality of synchronization clocks can be operated by operating on the common inversion or non-inversion delay clock from one inversion delay means. Can be derived.

According to the seventh aspect of the present invention, there is provided one inversion delay means for sequentially inverting the reference clock by the plurality of inversion delay elements to generate a plurality of inversion delay clocks and a plurality of non-inversion delay clocks. And a plurality of storage means composed of a plurality of storage elements for outputting the data supplied to the data input terminal from the output terminal in response to the asynchronous input signal, and signals output from the output terminals of the adjacent storage elements. A plurality of phase detection means for comparing and outputting the comparison result, and a plurality of selections for deriving a synchronous clock by selecting one of a plurality of inverted or non-inverted delayed clocks by the comparison signal output by the phase detection means. Since the means is provided, it is possible to generate a highly accurate synchronous clock without the need for a high frequency clock generation circuit, and There is an effect that it is possible to suppress the variation among the plurality of synchronous clock. Further, the synchronization accuracy of the synchronization clock can be made equal to the delay value of two stages of the inversion delay element, and the plurality of synchronization clocks can be operated by operating on the common inversion or non-inversion delay clock from one inversion delay means. Can be derived.

According to the eighth aspect of the present invention, in the synchronous clock generating circuit, one inverting delay means for sequentially inverting the reference clock by the plurality of inverting delay elements to generate a plurality of inverting delay clocks and a plurality of non-inverting delay clocks is provided. , Comparing a signal output from an output terminal of an adjacent storage element with a plurality of storage means composed of a plurality of storage elements that outputs data supplied to the data input terminal from an output terminal in response to an asynchronous input signal A plurality of phase detecting means for outputting a comparison signal as the comparison result and a comparison signal output by the phase detecting means are used to select and select a designated one of the plurality of inverted or non-inverted delay clocks. If there are multiple clocks, use the comparison signal to output multiple inverted or non-inverted delayed clocks according to a predetermined priority. Since a plurality of selection means for deriving one of them as a synchronous clock are provided, a highly accurate synchronous clock can be generated without the need for a high frequency clock generation circuit, and a plurality of designated inversion or non-synchronization clocks can be generated. By preventing the inverted delay clock from being multiplexed and output as the synchronous clock, it is possible to make the duty of the synchronous clock equal to the duty of the reference clock, and it is possible to suppress the variation among the generated plural synchronous clocks. There is an effect. Further, the synchronization accuracy of the synchronization clock can be made equal to the delay value of two stages of the inversion delay element, and the plurality of synchronization clocks can be operated by operating on the common inversion or non-inversion delay clock from one inversion delay means. Can be derived.

According to the delay pulse generating circuit of the ninth aspect, the synchronous clock generating means for generating the synchronous clock synchronized with the input signal and the synchronous clock are counted, and the pulse set is set at a predetermined count value. Since it is provided with a pulse generating means for generating a delayed pulse by performing a pulse reset with another predetermined count value, the delay amount and pulse width are synchronized with the reference clock with high accuracy and the delay is stable. There is an effect that it is possible to obtain a delayed pulse generation circuit having a large degree of freedom in setting the amount and pulse width.

According to the delay pulse generating circuit of the tenth aspect, the input signal is distributed according to the order of the pulses,
Input signal distribution means for generating a plurality of distribution input signals, a plurality of synchronization clock generation means for generating a plurality of synchronization clocks respectively synchronized with the plurality of distribution input signals, and a plurality of synchronization clocks are respectively counted and determined in advance. A plurality of distribution delay pulse generating means for generating a plurality of distribution delay pulses and a plurality of distribution delay pulses are synthesized by performing pulse setting with a predetermined count value and pulse resetting with another predetermined count value. Then, since the delay pulse synthesizing means for generating the delay pulse is provided, the delay amount and the pulse width are stable in synchronization with the reference clock with high accuracy.
There is an effect that it is possible to obtain a delayed pulse generation circuit having a greater degree of freedom in setting the delay amount and the pulse width.

According to the latch circuit of the eleventh aspect,
An input signal is provided to the input and is provided in a positive feedback loop for latching an output signal of the first gate and a first gate activated at a first level of the control input. It is activated at two levels and its output signal line is the first
In the latch circuit having the second gate connected to the output signal line of the first gate, the output impedance of the second gate is set to be lower than the output impedance of the first gate. When both gates are enabled, the output potential of the second gate becomes dominant over the output potential of the first gate, preventing the output potential in the positive feedback loop from holding the intermediate potential. ..
Further, there is an effect that it is possible to obtain a latch circuit capable of a high-speed latch operation even when the set signal is released or the reset signal is released and the control signal is input in close proximity.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a synchronous clock generating circuit according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of a synchronous clock generating circuit according to the present invention.

FIG. 3 is a timing chart showing the operation of the circuits of FIGS.

FIG. 4 is a circuit diagram showing a modified example of the circuit shown in FIGS. 1 and 2.

5 is a circuit diagram showing an excerpt of the circuits of FIGS. 1 and 2. FIG.

6 is a timing chart showing the operation of the circuit of FIG.

7 is a timing chart showing the operation of the circuit of FIG.

FIG. 8 is a timing chart showing the operation of the circuits of FIGS. 1 and 2 under certain conditions.

FIG. 9 is a circuit diagram showing a second embodiment of the synchronous clock generating circuit according to the present invention.

10 is a timing chart showing an operation of the circuits of FIGS. 1 and 9. FIG.

FIG. 11 is a third diagram of the synchronous clock generating circuit according to the present invention.
It is a circuit diagram which shows an Example.

FIG. 12 is a circuit diagram showing a modified example of the circuit shown in FIG.

FIG. 13 is a timing chart showing the operation of the circuits of FIGS. 1 and 12.

FIG. 14 is a third diagram of the synchronous clock generating circuit according to the present invention.
It is a circuit diagram which shows an Example.

15 is a timing chart showing the operation of the circuit of FIG.

FIG. 16 is a fourth diagram of the synchronous clock generating circuit according to the present invention.
It is a circuit diagram which shows an Example.

17 is a timing chart showing the operation of the circuit of FIG.

FIG. 18 is a circuit diagram showing a first embodiment of a delay pulse generating circuit according to the present invention.

19 is a block diagram showing details of the pulse generation circuit shown in FIG. 18. FIG.

20 is a timing chart showing an operation of the pulse generation circuit of FIG.

FIG. 21 is a timing chart showing the operation of the delay pulse generation circuit shown in FIG.

FIG. 22 is a circuit diagram showing a second embodiment of the delay pulse generating circuit according to the present invention.

23 is a timing chart showing the operation of the delay pulse generating circuit shown in FIG.

FIG. 24 is a circuit diagram showing a latch circuit with reset as a background of the latch circuit according to the present invention.

FIG. 25 is a circuit diagram showing a master / slave flip-flop with reset, which is a background of the latch circuit according to the present invention.

FIG. 26 is a circuit diagram using a D flip-flop showing an application example of a conventional master / slave flip-flop with reset.

FIG. 27 is a timing chart showing a simulation result of a conventional master / slave flip-flop with reset.

FIG. 28 is a timing chart showing simulation results of a master latch circuit of a master / slave flip-flop with reset using the latch circuit according to the present invention.

FIG. 29 is a circuit diagram showing a conventional synchronous clock generation circuit.

30 is a timing chart showing the operation of the circuit shown in FIG. 29. FIG.

FIG. 31 is a circuit diagram showing a conventional delay pulse generation circuit.

32 is a timing chart showing an operation of the circuit of FIG. 31. FIG.

[Explanation of symbols]

1 Reference clock input terminal 2, 2a to 2n Asynchronous signal input terminal 3, 3a to 3n Synchronous clock output terminal 6 Delay pulse output terminal 7, 7a, 7b Pulse set / reset value input terminal 8, 8a, 8b Pulse set / reset value Clock input terminal 9 Reset signal input terminal 10 Delayed clock generation circuit 20, 20a to 20n Storage circuit 30, 30a to 30n Phase detection circuit 40, 40a to 40n, 41, 42 Clock selection circuit X Synchronous clock generation circuit 101a to 108b Inversion delay Elements 200 to 208 D type flip-flops 210, 211 D type flip-flops 200,
First stage inverter connected to the timing signal input terminal * T of 201 300 to 308 NAND circuit 401 to 408 OR circuit 411 NAND circuit S3 Synchronous clock 100 Input signal terminal 2000 Control signal terminal 3000 Reset input terminal 400 Latch output terminal 500 For reading Gate 600,900 Inverter 1000 Positive feedback loop 800 NAND circuit 1100 Master latch circuit 1200 Slave latch circuit 1000m Master positive feedback loop 1000s Slave positive feedback loop

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese Patent Application No. 3-209267 (32) Priority date Hei 3 (1991) August 21 (33) Priority claim country Japan (JP)

Claims (11)

[Claims] 1. A synchronous clock generation circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. An inversion delay means for generating; a storage means composed of a plurality of storage elements for outputting data given to a data input terminal thereof from an output terminal in response to the reference clock and the plurality of non-inverted or inverted delay clocks; Comparing the signals output from the output terminal of the storage element, the phase detection means for giving a comparison signal as the comparison result to one data input terminal of the adjacent storage elements, and the phase detection means According to the output comparison signal, one of the plurality of inverted or non-inverted delay clocks is selected and the synchronization clock is selected. Synchronizing signal generating circuit and a selection means for deriving a click. 2. A synchronous clock generating circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. An inversion delay means for generating; a storage means composed of a plurality of storage elements for outputting data given to a data input terminal thereof from an output terminal in response to the reference clock and the plurality of non-inverted or inverted delay clocks; Comparing the signals output from the output terminal of the storage element, the phase detection means for giving a comparison signal as the comparison result to one data input terminal of the adjacent storage elements, and the phase detection means A designated one of the plurality of inverted or non-inverted delayed clocks is selected according to the output comparison signal. In addition, when there are a plurality of selected ones, there is provided a selecting means for using the comparison signal to derive one of the plurality of inverted or non-inverted delayed clocks as a synchronous clock in a predetermined priority order. Synchronous clock generation circuit. 3. A synchronous clock generation circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. Inversion delay means for generating, storage means composed of a plurality of storage elements for outputting data given to its data input terminal from an output terminal in response to the asynchronous input signal, and output from an output terminal of the adjacent storage element Selected signals among the plurality of inverted or non-inverted delay clocks are selected by the phase detection means that outputs the comparison signal as the comparison result and the comparison signal that the phase detection means outputs. And a selecting means for deriving a synchronous clock. 4. A synchronous clock generation circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. Inversion delay means for generating, storage means composed of a plurality of storage elements for outputting data given to its data input terminal from an output terminal in response to the asynchronous input signal, and output from an output terminal of the adjacent storage element Of the plurality of inverted or non-inverted delay clocks specified by the phase detection means that outputs the comparison signal as the comparison result and the comparison signal that the phase detection means outputs. In addition to selecting one, when there are multiple selected ones, the comparison signal is used to determine the priority according to a predetermined priority. Synchronizing signal generating circuit and a selection means for deriving one of said plurality of inverting or non-inverting delay clock as a synchronous clock Te. 5. A synchronous clock generation circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. A plurality of storages each including one inversion delay means for generating, and a plurality of storage elements for outputting data supplied to a data input terminal thereof from an output terminal in response to the reference clock and the plurality of non-inverted or inverted delay clocks. Means and a plurality of phase detection means for comparing signals output from the output terminals of the adjacent storage elements and applying a comparison signal as a comparison result to one data input terminal of the adjacent storage elements, , One of the plurality of inverted or non-inverted delayed clocks depending on the comparison signal output by the phase detection means. Synchronizing signal generating circuit that includes a plurality of selection means for deriving the selected synchronization clock. 6. A synchronous clock generation circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. A plurality of storages each including one inversion delay means for generating, and a plurality of storage elements for outputting data supplied to a data input terminal thereof from an output terminal in response to the reference clock and the plurality of non-inverted or inverted delay clocks. Means and a plurality of phase detection means for comparing signals output from the output terminals of the adjacent storage elements and applying a comparison signal as a comparison result to one data input terminal of the adjacent storage elements, , Among the plurality of inverted or non-inverted delay clocks, designated by the comparison signal output from the phase detection means The selected one is selected, and when there are a plurality of selected ones, one of the plurality of inverted or non-inverted delayed clocks is derived as a synchronous clock according to a predetermined priority using the comparison signal. A synchronous clock generation circuit having a plurality of selection means. 7. A synchronous clock generation circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. One inversion delay means for generating, a plurality of storage means composed of a plurality of storage elements for outputting data given to its data input terminal from an output terminal in response to the asynchronous input signal; The plurality of inverted or non-inverted delayed clocks are compared by comparing a plurality of signals output from the output terminals with each other and outputting a comparison signal as a result of the comparison, and a plurality of comparison signals output by the phase detection means. And a plurality of selecting means for deriving a synchronous clock by selecting one of them. 8. A synchronous clock generating circuit for generating a synchronous clock synchronized with an asynchronous input signal, wherein a reference clock is sequentially inverted by a plurality of inverting delay elements, and a plurality of inverting delay clocks and a plurality of non-inverting delay clocks are generated. One inversion delay means for generating, a plurality of storage means composed of a plurality of storage elements for outputting data given to its data input terminal from an output terminal in response to the asynchronous input signal; The plurality of inverted or non-inverted delayed clocks are compared by comparing a plurality of signals output from the output terminals with each other and outputting a comparison signal as a result of the comparison, and a plurality of comparison signals output by the phase detection means. In addition to selecting the specified one of them, if there are a plurality of selected ones, it is determined in advance by using the comparison signal. Synchronizing signal generating circuit that includes a plurality of selection means for deriving one as the synchronous clock of the plurality of inverting or non-inverting delay clock by priority order. 9. A synchronous clock generating means for generating a synchronous clock synchronized with an input signal, counting the synchronous clock, performing pulse setting with a predetermined count value, and using another predetermined count value. A delay pulse generation circuit comprising pulse generation means for generating a delay pulse by performing pulse reset. 10. An input signal distribution means for distributing an input signal according to the order of its pulses to generate a plurality of distribution input signals, and a plurality of means for generating a plurality of synchronization clocks respectively synchronized with the plurality of distribution input signals. A plurality of distribution delays by counting each of the plurality of synchronization clocks, performing pulse setting with a predetermined count value, and performing pulse reset with another predetermined count value. A delay pulse generation circuit comprising: a plurality of distributed delay pulse generating means for generating a pulse; and a delay pulse combining means for combining the plurality of distributed delay pulses to generate a delay pulse. 11. A first gate provided with an input signal at its input and activated at a first level of a control input, and a positive feedback loop for latching an output signal of said first gate. And a second gate which is activated at a second level of the control input and has an output signal line connected to the output signal line of the first gate, the second gate Of the latch circuit is lower than the output impedance of the first gate.