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JPH05129251A - Resist pattern formation - Google Patents

Resist pattern formation

Info

Publication number
JPH05129251A
JPH05129251A JP28872391A JP28872391A JPH05129251A JP H05129251 A JPH05129251 A JP H05129251A JP 28872391 A JP28872391 A JP 28872391A JP 28872391 A JP28872391 A JP 28872391A JP H05129251 A JPH05129251 A JP H05129251A
Authority
JP
Japan
Prior art keywords
resist
substrate
layer resist
etching
lower layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28872391A
Other languages
Japanese (ja)
Inventor
Hiroyuki Endo
裕之 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP28872391A priority Critical patent/JPH05129251A/en
Publication of JPH05129251A publication Critical patent/JPH05129251A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To provide a method, which prevents bottom layer resist residue at the recessed part on a substrate without excessively overetching the bottom layer resist when the substrate has a recessed part, for pattern formation using multi-layer resist in semiconductor device production. CONSTITUTION:The bottom layer resist of multi-layer resist has poly methyl methacrylate 2 as the first layer, the film of novolak resist 3 as the second layer, and top layer resist 4 is formed on the bottom layer resist for patterning and etching.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置の製造に
おける多層レジストによるパターン形成方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method using a multilayer resist in the manufacture of semiconductor devices.

【0002】[0002]

【従来の技術】従来の多層レジストパターン形成工程に
ついて図2に例を示す。
2. Description of the Related Art FIG. 2 shows an example of a conventional multilayer resist pattern forming process.

【0003】同図(a)〜(e)は工程の概略である。
図2において、1は被加工基板を、2は下層レジスト
を、3は上層レジストを表わす。
FIGS. 3A to 3E are schematic views of the steps.
In FIG. 2, 1 is a substrate to be processed, 2 is a lower layer resist, and 3 is an upper layer resist.

【0004】まず図2(a)において、被加工基板1上
に該基板1の有する段差を被覆しうる厚さの下層レジス
ト2を塗布し、熱板若しくは高温雰囲気中で200〜2
50℃の加熱を施す。
First, in FIG. 2 (a), a lower resist 2 having a thickness capable of covering the steps of the substrate 1 is applied onto a substrate 1 to be processed, and then a hot plate or a high temperature atmosphere is used for 200-2.
Heat at 50 ° C.

【0005】次に図2(b)のように、平坦化された基
板上に上層レジスト3を塗布及び加熱し、多層レジスト
構造を形成する。この後図2(c)において、所望のパ
ターン通りにエネルギー線4を照射し、図2(d)の現
像工程により上層レジストパターン3を得る。
Next, as shown in FIG. 2B, an upper layer resist 3 is applied and heated on the flattened substrate to form a multilayer resist structure. After that, in FIG. 2C, the energy beam 4 is irradiated according to a desired pattern, and the upper layer resist pattern 3 is obtained by the developing process of FIG. 2D.

【0006】最後に図2(e)のように、図2(d)で
得られた上層レジストパターン3をマスクとして、反応
性イオンエッチング等により下層レジストをパターニン
グし、工程を終了する。
Finally, as shown in FIG. 2E, the lower layer resist is patterned by reactive ion etching or the like using the upper layer resist pattern 3 obtained in FIG. 2D as a mask, and the process is completed.

【0007】[0007]

【発明が解決しようとする課題】しかし以上述べた工程
において、下層レジストエッチング後の被加工基板露出
領域に凹部が存在する場合、該凹部の内部に下層レジス
トが残留し、後の工程で欠陥が生じるという問題があっ
た。また該凹部を十分にエッチングし得る様なオーバー
エッチングを施した場合、レジストパターニングの寸法
が減少したり、早期に露出した基板段差上部の表面が、
過剰にスパッタされ、レジストパターン側壁に付着し、
後のレジスト剥離工程で除去不能となるなどの問題があ
った。
However, in the steps described above, when a concave portion exists in the exposed region of the substrate after etching the lower layer resist, the lower layer resist remains inside the concave portion and a defect is generated in a later step. There was a problem that it would occur. In addition, when over-etching is performed to sufficiently etch the recesses, the dimension of resist patterning is reduced, and the surface of the substrate step upper portion exposed earlier is
Excessively sputtered and adhered to the sidewall of the resist pattern,
There is a problem that the resist cannot be removed in the subsequent resist stripping process.

【0008】この発明は以上述べた様に、段差を有する
被加工基板上の下層レジストを反応性イオンエッチング
等でパターニングする場合、過剰なオーバーエッチング
を施すことなしに、被加工基板上凹部における該下層レ
ジストの残留を防ぎ得る下層レジスト構造を提供するこ
とを目的とする。
As described above, according to the present invention, when the lower layer resist having a step on the substrate to be processed is patterned by reactive ion etching or the like, it is possible to form the resist in the recess on the substrate to be processed without excessive overetching. It is an object of the present invention to provide a lower layer resist structure capable of preventing the lower layer resist from remaining.

【0009】[0009]

【課題を解決するための手段】この発明は被加工基板上
にレジストパターンを形成する工程において、該被加工
基板上にポリメチルメタクリレート(以下PMMA)を
塗布し、その上部にノボラックレジストを塗布した2層
構造を下層レジストとして使用する様にしたものであ
る。
According to the present invention, in a step of forming a resist pattern on a substrate to be processed, polymethylmethacrylate (hereinafter referred to as PMMA) is coated on the substrate to be processed, and a novolac resist is coated on the upper portion thereof. The two-layer structure is used as a lower layer resist.

【0010】[0010]

【作用】前述したようにこの発明では、下層レジスト底
部にエッチングレートの早いPMMAの膜を設けるよう
にしたので、被加工基板の有する凹部をエッチングする
為に必要となる過剰なオーバーエッチングを低減するこ
とが出来る。これによってレジストパターンの寸法制御
性が向上すると共に、被加工基板がスパッタされること
によってレジストパターンの側壁に剥離の困難な膜が生
じることを防ぐことが出来る。
As described above, in the present invention, since the PMMA film having a high etching rate is provided on the bottom of the lower resist, excessive over-etching required for etching the concave portion of the substrate to be processed is reduced. You can As a result, the dimensional controllability of the resist pattern is improved, and it is possible to prevent a film that is difficult to peel off from being formed on the sidewall of the resist pattern due to sputtering of the substrate to be processed.

【0011】[0011]

【実施例】図1に本発明の実施例の工程を示し、以下順
に説明する。
EXAMPLE FIG. 1 shows a process of an example of the present invention, which will be described in order below.

【0012】図1(a)において、被加工基板1上にP
MMA2を回転塗布する。PMMAの膜厚は被加工基板
1の凹部の深さにより、それを埋めることが出来る様に
決定される。塗布後、熱板若しくは高温雰囲気中で18
0℃の加熱を行う。
In FIG. 1 (a), P is formed on the substrate 1 to be processed.
Spin-apply MMA2. The film thickness of PMMA is determined by the depth of the concave portion of the substrate 1 to be processed so that it can be filled. 18 after application in a hot plate or high temperature atmosphere
Heat at 0 ° C.

【0013】次に図1(b)で、例えばHPR204
(富士ハント社製)の様なノボラックレジスト3を該レ
ジスト3の表面が完全に平坦化されうる程度の膜厚で回
転塗布し、その後熱板若しくは高温雰囲気中で200℃
〜250℃の加熱を行うこの2層、2と3をもって下層
レジストとする。次に図1(c)のように、ノボラック
レジスト3の上に上層レジスト4を直接回転塗布する
(図1(c)左図)か、又は中間膜5を成膜した後、該
中間膜5の上に上層レジスト4を回転塗布し(図1
(c)右図)、熱板若しくは高温雰囲気中で加熱し、成
膜工程全体を終了する。
Next, referring to FIG. 1B, for example, HPR204
A novolak resist 3 such as that manufactured by Fuji Hunt Co., Ltd. is spin-coated at a film thickness such that the surface of the resist 3 can be completely flattened, and then 200 ° C. in a hot plate or a high temperature atmosphere.
These two layers 2 and 3 which are heated to 250 ° C. are used as a lower layer resist. Next, as shown in FIG. 1C, the upper layer resist 4 is directly spin-coated on the novolac resist 3 (FIG. 1C left view) or the intermediate film 5 is formed and then the intermediate film 5 is formed. The upper layer resist 4 is spin coated on the top surface (see FIG.
(C) Right diagram), heating is performed in a hot plate or a high temperature atmosphere, and the entire film forming process is completed.

【0014】次に図1(d)のように、露光、現像、若
しくはさらにエッチング等既知の方法により所望のパタ
ーンを得る。この後、図1(e)のように、下層レジス
トである2と3を酸素系の反応性イオンエッチングによ
りパターニングする。ここでエッチングが進行し、基板
1の表面が露出した時点から被加工基板1上の凹部内に
あるPMMA2のエッチングが開始される。酸素98s
ccm,窒素98sccm,RF1.5KW,圧力10
mTorrの条件でエッチングを行った場合、ノボラッ
クレジスト(例えばHPR204)3のエッチングレー
トが10000Å/min であるのに対し、PMMA2の
エッチングレートは18500Å/minと約1.9倍大
きい。したがってPMMA2が形成されている被加工基
板1の凹部のエッチングを行っている間に、おもにノボ
ラックレジスト3から成るマスクパターンに生じる膜減
りや寸法の減少はそのレジスト3のみを下層レジストと
して用いた場合よりも低減することが出来る。また、こ
の後被加工基板1にエッチングを施すに際しても異方性
の強い条件を用いれば、エッチング耐性の強いノボラッ
クレジストをその上部に有するマスクパターンによって
良好な加工が可能である。
Next, as shown in FIG. 1D, a desired pattern is obtained by a known method such as exposure, development, or etching. Thereafter, as shown in FIG. 1E, the lower layer resists 2 and 3 are patterned by oxygen-based reactive ion etching. Here, the etching progresses, and when the surface of the substrate 1 is exposed, the etching of the PMMA 2 in the concave portion on the substrate 1 to be processed is started. Oxygen 98s
ccm, nitrogen 98sccm, RF1.5KW, pressure 10
When etching is performed under the condition of mTorr, the etching rate of the novolac resist (eg, HPR204) 3 is 10,000 Å / min, whereas the etching rate of PMMA2 is 18500 Å / min, which is about 1.9 times larger. Therefore, while etching the concave portion of the substrate 1 on which the PMMA 2 is formed, the film reduction and the size reduction mainly occurring in the mask pattern made of the novolac resist 3 are caused when only the resist 3 is used as the lower layer resist. Can be further reduced. Further, when the substrate 1 to be processed is subsequently subjected to etching, if conditions with strong anisotropy are used, good processing can be performed with a mask pattern having a novolac resist having strong etching resistance on the upper part thereof.

【0015】[0015]

【発明の効果】以上説明したようにこの発明によれば、
下層レジスト底部にエッチングレートの早いPMMAの
膜を設けるようにしたので、被加工基板の有する凹部を
エッチングする為に必要となる過剰なオーバーエッチン
グを低減することが出来る。これによってレジストパタ
ーンの寸法制御性が向上すると共に、被加工基板がスパ
ッタされることによってレジストパターンの側壁に剥離
の困難な膜が生じることを防ぐことが出来る。
As described above, according to the present invention,
Since the PMMA film having a high etching rate is provided on the bottom of the lower resist layer, it is possible to reduce the excessive over-etching required for etching the recesses of the substrate to be processed. As a result, the dimensional controllability of the resist pattern is improved, and it is possible to prevent a film that is difficult to peel off from being formed on the sidewall of the resist pattern due to sputtering of the substrate to be processed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例FIG. 1 Example of the present invention

【図2】従来例FIG. 2 Conventional example

【符号の説明】[Explanation of symbols]

1 基板 2 PMMA 3 ノボラックレジスト 4 上層レジスト 5 中間膜 1 substrate 2 PMMA 3 novolac resist 4 upper layer resist 5 intermediate film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置の製造における多層レジスト
パターンの形成において、 半導体基板上に、下層レジストの第1の層としてポリメ
チルメタクリレートを成膜する工程と、前記下層レジス
トの第2の層としてノボラックレジストを成膜する工程
と、前記下層レジストのマスクとなる上層レジストの塗
布及びパターニングを行う工程と、酸素系の反応性イオ
ンエッチングにより前記下層レジストの第1及び第2の
層のエッチングを行う工程より成ることを特徴とするレ
ジストパターン形成方法。
1. A method of forming a multi-layered resist pattern in the manufacture of a semiconductor device, the step of depositing polymethylmethacrylate as a first layer of a lower layer resist on a semiconductor substrate, and novolak as a second layer of the lower layer resist. A step of forming a resist, a step of applying and patterning an upper layer resist that serves as a mask of the lower layer resist, and a step of etching the first and second layers of the lower layer resist by oxygen-based reactive ion etching A resist pattern forming method comprising:
JP28872391A 1991-11-05 1991-11-05 Resist pattern formation Pending JPH05129251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28872391A JPH05129251A (en) 1991-11-05 1991-11-05 Resist pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28872391A JPH05129251A (en) 1991-11-05 1991-11-05 Resist pattern formation

Publications (1)

Publication Number Publication Date
JPH05129251A true JPH05129251A (en) 1993-05-25

Family

ID=17733857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28872391A Pending JPH05129251A (en) 1991-11-05 1991-11-05 Resist pattern formation

Country Status (1)

Country Link
JP (1) JPH05129251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7030007B2 (en) 2002-09-20 2006-04-18 Mitsubishi Denki Kabushiki Kaisha Via-filling material and process for fabricating semiconductor integrated circuit using the material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7030007B2 (en) 2002-09-20 2006-04-18 Mitsubishi Denki Kabushiki Kaisha Via-filling material and process for fabricating semiconductor integrated circuit using the material

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