JPH05129419A - Method of relieving defects in semiconductor integrated circuit device and apparatus for implementing the same - Google Patents

Abstract

(57) [Abstract] [Purpose] In defect repair technology for semiconductor integrated circuit devices,
Defects when the defect relief circuit block 3B ′ is buried are reduced, and the yield in the manufacturing process of the semiconductor integrated circuit device is improved. In a defect relief method for a semiconductor integrated circuit device,
Area 11 in which defective circuit block 3B of substrate 1 is removed
The defect relieving circuit block 3B ′ having the magnetic layer 13 formed on its back surface is arranged in the
While applying a magnetic field to B ′, the placement position of the defect relief circuit block 3B ′ is determined with respect to the placement position of at least one of the plurality of circuit blocks 3A and 3C on the main surface of the substrate 1, and the placement position is In the determined state, the defect relief circuit block 3B ′ is fixed to the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect relief technique,
In particular, the present invention relates to a technique effectively applied to a defect relief technique for a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art As a defect relief technique for a wafer scale semiconductor integrated circuit device (wafer scale integration), the applicant of the present application filed Japanese Patent Application No. 2-332604 (filing date: November 29, 1990). ing. This defect relief technique removes a defective circuit block having a defect from a plurality of circuit blocks mounted on a circuit formation surface of the semiconductor wafer from the semiconductor wafer, and removes a defect in a region of the semiconductor wafer from which the defective circuit block is removed. This is a technique for embedding a relief circuit block.

Mounted on the circuit forming surface of a semiconductor wafer
Each of the plurality of circuit blocks is a functional circuit block or a
Also called cross cell, shift register circuit, ROM
(ReadOnlyMemory), RAM (RandomAccess
Memory), etc., as one functional unit at the design stage
Design and development is done. The defect relief circuit block
Is SDI (SuperDeviceIntegration) chip
Called and converted to a bad circuit block
It is a normal circuit block.

Further, the above-mentioned defect relief technique is applied not only to a semiconductor integrated circuit device of a wafer scale but also to a semiconductor integrated circuit device of a large pellet size obtained by cutting a plurality of semiconductor wafers. That is, the defect relief technique embeds a defect relief circuit block in place of a circuit block having a defect among a plurality of circuit blocks mounted on this semiconductor integrated circuit device.

This type of defect relief technique is characterized in that the yield in the manufacturing process of the semiconductor integrated circuit device can be prevented from lowering as the size of the semiconductor integrated circuit device increases, and the yield in the manufacturing process of the semiconductor integrated circuit device can be improved.

[0006]

However, the inventor of the present invention has found the following problems in the above-mentioned defect relief technique.

The above-mentioned defect repair technique is designed to remove a defective circuit block having a defect from a plurality of circuit blocks mounted on a semiconductor wafer (or a semiconductor pellet), and repair the defect in the removed region of the semiconductor wafer. Place the circuit block. The defect-relieving circuit block is transferred to a region where the defective circuit block of the semiconductor wafer loaded on the surface of the table such as the preliminary XY stage is removed by a mechanical means such as a vacuum suction pad, and the alignment is performed. After that, the semiconductor wafer is fixed to the semiconductor wafer.
Therefore, when embedding the defect relief circuit block in the semiconductor wafer, especially during alignment, external pressure based on mechanical means is applied to the defect relief circuit block, and damage or destruction occurs in the defect relief circuit block. The yield in the manufacturing process of semiconductor wafers decreases.

An object of the present invention is to provide a defect relief technique for a semiconductor integrated circuit device in which a defect relief circuit block is embedded in place of a defective circuit block having a defect among a plurality of circuit blocks mounted on the main surface of a substrate. It is another object of the present invention to provide a technique capable of reducing defects that occur when the defect relief circuit block is buried and improving the yield in the manufacturing process of the semiconductor integrated circuit device.

Another object of the present invention is to provide an implementation device that achieves the above objects.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A plurality of circuit blocks are formed on a main surface of a substrate, defective circuit blocks of the plurality of circuit blocks are removed from the substrate, and defects are formed in a region of the substrate where the defective circuit blocks are removed. In a defect relief method for a semiconductor integrated circuit device in which a relief circuit block is embedded, a defect relief in which a magnetic layer or a magnetic particle mixed layer is formed on a circuit formation surface or a back surface thereof in a region of the substrate where the defective circuit block is removed Arranging the circuit block for
A step of determining an arrangement position of the defect relief circuit block with respect to an arrangement position of a plurality of circuit blocks or a part of the circuit blocks on the main surface of the substrate while applying a magnetic field to the defect relief circuit block; Fixing the defect relief circuit block to the substrate in a state where the arrangement position is determined.

(2) In the defect relief alignment device,
With respect to the arrangement positions of the plurality of circuit blocks or a part of the circuit blocks on the main surface of the substrate, a defective circuit block of the plurality of circuit blocks is changed to a region where the defective circuit block of the substrate is removed. A recognition device for recognizing the arrangement position of the arranged defect relief circuit block, and a magnetic field is applied to the magnetic layer or the magnetic particle mixed layer formed on the circuit formation surface of the defect relief circuit block or on the back surface thereof, and this defect relief is provided. A magnetic field applying device for moving the arrangement position of the circuit block for use, and a displacement amount between the arrangement position of the circuit block on the main surface of the substrate recognized by the recognition device and the arrangement position of the defect relief circuit block, And a magnetic field control device that drives the magnetic field application device and corrects the deviation amount.

[0014]

According to the above-mentioned means (1), when repairing a defect of the semiconductor integrated circuit device, a magnetic field is applied to the magnetic layer or the magnetic particle mixed layer formed in the defect repairing circuit block to move in the vertical direction and the lateral direction. Since the arrangement position of the defect relief circuit block can be moved in a non-contact state by moving,
It is possible to reduce damage given to the defect relief circuit block when aligning the arrangement positions of the defect relief circuit block.

According to the above-mentioned means (2), it is possible to provide an implementation device that obtains the above-mentioned effect (1).

The structure of the present invention will be described below with reference to an embodiment in which the present invention is applied to a wafer scale semiconductor integrated circuit device or a semiconductor integrated circuit device of a large pellet size cut out from a semiconductor wafer.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A defect relieving method for a wafer scale or large pellet size semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIGS. Explained.

First, as shown in FIG. 1, a plurality of circuit blocks 3A, 3B and 3C are mounted on a surface of a semiconductor substrate 1 formed of single crystal silicon with an insulator 2 interposed therebetween.

The semiconductor substrate 1 is either a semiconductor wafer or a so-called semiconductor pellet obtained by dicing a semiconductor wafer into a plurality of pieces. As the insulator 2, for example, a silicon oxide film is used. Each of the circuit blocks 3A, 3B, and 3C is configured by disposing a plurality of semiconductor elements on the surface (upper surface in FIG. 1) of a semiconductor layer made of single crystal silicon (or amorphous or polycrystalline silicon). Circuit block 3A, 3
The central processing unit (CPU), the shift register circuit, the ROM, the RAM, and the like of each of B and 3C are designed and developed as one functional unit at the design stage. Each of the circuit blocks 3A, 3B, and 3C may be a circuit block having the same circuit function or may be a circuit block having different circuit functions. This structure is not limited to, the structure of laminating a semiconductor layer by interposing an insulator 2 on the surface of the semiconductor substrate 1 is a so-called SOI (S ilicon O n I nsula
tor) structure.

An insulating substrate may be used as the semiconductor substrate 1 (in this case, the presence of the insulator 2 is not always necessary).

Next, as shown in FIG. 2, the circuit block 3
In the areas A, 3B, and 3C, the wirings 4A and 4A are provided.
B, 4C are formed respectively, and circuit blocks 3A, 3B, 3
Connection between the respective semiconductor elements of C or between circuits is performed (connection within a circuit block, connection within a functional circuit block, or connection within a macro cell). Each of the wirings 4A, 4B and 4C is usually arranged in a plurality of layers mainly for the purpose of shortening the wiring length and the wiring occupying area. The wirings 4 (between the upper and lower wirings) arranged in each of the plurality of layers are insulated from each other by an interlayer insulating film (generically denoted by reference numeral 5), and a connection hole formed in the interlayer insulating film 5 in a predetermined region. Electrical continuity is achieved through.

Next, as shown in FIG. 3, the circuit block 3
The test terminals A, 3B, and 3C are brought into contact with the probe 6 connected to the tester, respectively, and the circuit blocks 3A and 3C are connected.
The characteristic inspection of each of B and 3C is performed. This characteristic inspection is performed for the purpose of finding a defective circuit block having a defect among the plurality of circuit blocks 3A, 3B, 3C mounted on the surface of the semiconductor substrate 1.

As a result of this characteristic inspection, for example, when the presence of a defect is found in the circuit block 3B, a defect relief process of embedding a defect relief circuit block in place of the circuit block 3B is performed.

In this defect relief process, first, a plurality of circuit blocks 3A mounted on the surface of the semiconductor substrate 1,
Of the areas 3B and 3C, the area 11 in which the defective circuit block 3B in which the defect is present is arranged is removed from the area 10 in which the normal circuit blocks 3A and 3C in which the defect is not present are arranged. As shown in FIG. 4, the back surface of the semiconductor substrate 1 is diced, and the U-shaped groove 1A surrounding the region 11 is provided to the extent that the insulator 2 is not reached.
To form. Dicing is performed by a cutting technique using a diamond cutter, a laser cutting technique, or the like. Although not shown in FIG. 4 and FIGS. 5 and 6 described later, the dicing is
This is performed with a mask (silicon oxide film in this embodiment) previously formed on the back surface of the semiconductor substrate 1. This mask is
It is used as an etching mask in a later process.

Next, as shown in FIG. 5, using the mask not shown, the back surface of the semiconductor substrate 1 is etched in the U-shaped groove 1A until the insulator 2 is reached.
The groove 11B is formed to completely separate the region 11 and the region 11 of the semiconductor substrate 1. For the etching, for example, anisotropic etching using SF ₆ as an etching gas is used.

Next, as shown in FIG. 6, this time, on the surface of the semiconductor substrate 1, the interlayer insulating film 5 of the wiring layer in the region 11 is formed.
A groove 5A is formed in a region surrounding each of the insulators 2 to completely separate the region 11 from each of the interlayer insulating film 5 in the region 10 and the insulator 2. As a result, the defective circuit block 3B can be separated from the region 10 including the semiconductor substrate 1, the insulator 2, and the interlayer insulating film 5 and having the plurality of circuit blocks 3A and 3C.

Next, as shown in FIG. 7, the removal pin 7 is provided on the region 11 of the semiconductor substrate 1, that is, the back surface of a part of the semiconductor substrate 1 on which the defective circuit block 3B is mounted, with the adhesive layer 8 interposed. Are bonded together, and as shown in FIG. 8, a partial region 11 of the semiconductor substrate 1 is removed.

Next, a defect relief circuit block 3B 'is embedded in a part of the semiconductor substrate 1. First, as shown in FIG. 9, the circuit block 3B in which the semiconductor substrate 1 has a defect is present.
The defect relief circuit block 3B ′ is arranged in the region from which is removed. The defect relieving circuit block 3B ′ has substantially the same function (same structure) as the removed and removed circuit block 3B and has an insulator on the surface of the semiconductor substrate 1 corresponding to the removed size. 2 is interposed (the area denoted by reference numeral 12 in FIG. 9 and surrounded by a broken line).

A magnetic layer 13 is preliminarily formed on the back surface of the semiconductor substrate 1 on which the defect relief circuit block 3B 'is mounted. The magnetic layer 13 is formed of a tape coated with particles of a magnetic material such as ferrite metal, and the magnetic layer 13 is bonded to the back surface of the semiconductor substrate 1. The magnetic layer 13 is formed of a magnetic particle mixed layer in which magnetic particles are mixed in a resin such as a polyimide resin or an epoxy resin. In this case, the magnetic layer 13 is applied and then cured. Basically, the magnetic layer 13 is mainly configured to apply a magnetic field from the outside to move the semiconductor substrate 1 having the defect relief circuit block 3B ′ mounted thereon.

Next, the semiconductor substrate 1 having the circuit blocks 3A and 3C mounted thereon is aligned with the semiconductor substrate 1 having the defect relief circuit block 3B 'mounted thereon. This alignment is performed by the transparent glass substrate 20, the optical system 21, and the optical system 21, as shown in FIG.
The marker recognition device 22, the magnetic field control device 23, and the magnetic field application device 24 are mainly configured.

In the alignment, first, in the semiconductor substrate 1 mounted on the surface of the transparent glass substrate 1, the defect relief circuit block 3B 'is mounted in a region where the defective circuit block 3B is removed. Substrate 1 is soft landed. On the surface of the transparent glass substrate 1, the respective sides of the circuit blocks 3A and 3C and the defect relief circuit block 3B ′ are in contact. The semiconductor substrate 1 on which the defect relief circuit block 3B 'is mounted is transported to a predetermined position by a vacuum suction collet, a sandwiching collet or the like.

Next, an alignment mark (marker) preliminarily formed in one of the areas of the circuit blocks 3A and 3C mounted on the surface of the semiconductor substrate 1 and the area of the defect relief circuit block 3B '. The alignment marks formed in advance are read by the marker recognition device 22 through the transparent glass substrate 1 and the optical system 21, respectively. That is, the marker recognition device 22 can detect the amount of deviation between the positions where the two are arranged. The alignment marks are the circuit blocks 3A, 3C,
The same step as any of the steps of forming the respective semiconductor elements of the defect relief circuit block 3B ′ (for example, at least one of an isolation insulating film forming step, a gate material forming step, a diffusion layer forming step, and a connection hole forming step). ) Is formed.

When the marker recognition device 22 detects the displacement amount of the arrangement position, the magnetic field control device 23 drives the magnetic field applying device 24 according to the displacement amount, and the magnetic field applying device 24 causes the defect relief circuit block 3B. A magnetic field is generated in the magnetic layer 13 on the back surface of the semiconductor substrate 1 on which is mounted. In the case of the present embodiment, the magnetic field generates a repulsive force that presses the surface of the defect relief circuit block 3B ′ against the transparent glass substrate 20 in a non-contact manner and appropriately. As shown in FIG. 14, by applying this magnetic field, the semiconductor substrate 1 on which the defect relief circuit block 3B ′ is mounted can be moved in the vertical and horizontal directions in the non-contact state, and can be rotated. It is possible to perform the alignment from the arrangement position of the broken line to the arrangement position of the solid line.

Next, as shown in FIG. 10, the state in which the arrangement position of the semiconductor substrate 1 on which the defect relief circuit block 3B 'is mounted is determined is held, and the surface of this defect relief circuit block 3B' and A mask 14 is formed so as to cover the surrounding groove 5A, and a temporary fixing resin 15 is injected into the U-shaped groove 1B on the back surface of the semiconductor substrate 1. The mask 14 is formed mainly for the purpose of suppressing the outflow of the temporary fixing resin 15 to the surface side of the defect relief circuit block 3B ′, and uses, for example, a resin material such as a photosensitive resin or a polyimide resin. For the temporary fixing resin 15, a resin material such as an epoxy resin is used.

Next, the temporary fixing resin 15 is cured,
After that, as shown in FIG. 11, the mask 14 and the magnetic layer 13 are formed.
Remove each of the. The order of this removal may be basically any. The magnetic layer 13 is removed by peeling it from the back surface of the semiconductor substrate 1 in the case of the tape coated with the above-mentioned magnetic material, and is removed by etching or mechanical polishing in the case of the magnetic particle mixed layer. When this process is completed, the plurality of circuit blocks 3 mounted on the semiconductor substrate 1
Of the A, 3B, and 3C, the defective circuit block 3B having a defect is removed, and the defective circuit block 3B ′ is replaced with the defective circuit block 3B to complete the embedding.

Next, as shown in FIG. 12, on the surface of each of the circuit blocks 3A and 3C and the defect relief circuit block 3B 'mounted on the semiconductor substrate 1, mainly for filling the groove 5A and insulating separation. Then, the flattening insulating film 16 is formed.
The flattening insulating film 16 is formed of, for example, a single layer of a silicon oxide film deposited by a CVD method or a laminated layer mainly including the silicon oxide film.

Next, as shown in FIG. 13, on the flattening insulating film 16, wirings for connecting the circuit blocks 3A, 3C and the defect relief circuit block 3B 'to each other (connection between circuit blocks). ) 17 is formed. The wiring 17 is
The main purpose is to shorten the wiring length and the wiring occupation area.
It is arranged in a plurality of wiring layers.

The semiconductor integrated circuit device of this embodiment is completed by performing these series of defect relief processes.

In this way, a plurality of circuit blocks 3A, 3B, 3C are formed on the main surface of the semiconductor substrate 1, and the defective circuit block 3B among the plurality of circuit blocks 3A, 3B, 3C is the semiconductor substrate 1. In the defect relieving method for a semiconductor integrated circuit device (wafer scale or semiconductor pellet), the defect relieving circuit block 3B ′ is buried in a region of the semiconductor substrate 1 where the defective circuit block 3B is removed. Bad circuit block 3B
The defect relieving circuit block 3 in which the magnetic layer (or magnetic particle mixed layer) 13 is formed on the back surface in the region 11 where the
B ', and the defect relief circuit block 3
Arrangement of the defect relief circuit block 3B 'with respect to the arrangement position of the plurality of circuit blocks 3A, 3C or a part of the circuit blocks 3A or 3C on the main surface of the semiconductor substrate 1 while applying a magnetic field to B'. The method includes the steps of determining the position and the step of fixing the defect relief circuit block 3B ′ to the semiconductor substrate 1 with the arrangement position determined. With this configuration, when repairing defects in the semiconductor integrated circuit device,
Magnetic layer 13 formed in the defect relief circuit block 3B '
The defect relieving circuit block 3B ′ can be moved in a non-contact state by applying a magnetic field to the defect relieving circuit block 3B ′ such as vertical movement, horizontal movement, and rotational movement.
It is possible to reduce the damage given to the defect relief circuit block 3B ′ when aligning the arrangement position of B ′. That is,
In the defect relief process, the yield can be improved (high throughput can be achieved).

Further, in the defect relief positioning device,
A plurality of circuit blocks 3A, 3C on the main surface of the semiconductor substrate 1
Alternatively, the plurality of circuit blocks 3A, 3B, 3 may be arranged with respect to the arrangement positions of some of the circuit blocks 3A or 3C.
The semiconductor substrate 1 in place of the defective circuit block 3B of C
Of the defective relief circuit block 3B ′ arranged in the area 11 where the defective circuit block 3B of FIG.
A magnetic field is applied to the magnetic layer 13 formed on the back surface of B'to move the position of the defect relief circuit block 3B ', and the main surface of the semiconductor substrate 1 recognized by the recognition device 22. A magnetic field control device 23 that drives the magnetic field applying device 24 to correct the deviation amount according to the deviation amount between the arrangement position of the circuit block 3A or 3B and the arrangement position of the defect relief circuit block 3B ′. Equipped with. With this configuration, it is possible to provide an implementation device that achieves the above-described effects.

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

For example, according to the present invention, in the alignment of the above-described embodiment, the magnetic layer 13 is formed on the surface side of the defect relief circuit block 3B ', and a magnetic field is applied from the magnetic applying device 24 through the transparent glass substrate 20 ( In this case, either repulsive force or suction force) and alignment may be performed.

Further, the present invention is not limited to the defect relief technique of the circuit block mounted on the silicon substrate, but may be applied to the defect relief technique of the circuit block mounted on the compound semiconductor substrate.

[0045]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

In the defect relief technique of the semiconductor integrated circuit device in which the defect relief circuit block is buried in place of the defective circuit block having the defect among the plurality of circuit blocks mounted on the main surface of the substrate, the defect relief technique is used. It is possible to reduce defects that occur at the time of burying the circuit block and improve the yield in the manufacturing process of the semiconductor integrated circuit device.

It is possible to provide an implementation device that achieves the above effects.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts in a first step illustrating a defect relief process of a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 2 is a sectional view of a main part in a second step.

FIG. 3 is a sectional view of a main part in a third step.

FIG. 4 is a sectional view of a main part in a fourth step.

FIG. 5 is a sectional view of a main part in a fifth step.

FIG. 6 is a sectional view of an essential part in a sixth step.

FIG. 7 is a sectional view of an essential part in a seventh step.

FIG. 8 is a sectional view of an essential part in an eighth step.

FIG. 9 is a sectional view of an essential part in a ninth step.

FIG. 10 is a sectional view of an essential part in a tenth step.

FIG. 11 is a sectional view of a key portion in an eleventh step.

FIG. 12 is a sectional view of an essential part in a twelfth process.

FIG. 13 is a sectional view of a key portion in a thirteenth step.

FIG. 14 is a schematic block configuration diagram of an alignment device used in the defect relief.

[Explanation of symbols]

1 ... Semiconductor substrate, 1A, 1B, 5A ... Groove, 2 ... Insulator,
3A to 3C ... Circuit block, 3B '... Defect relief circuit block, 4, 17 ... Wiring, 10, 11 ... Region, 20 ... Transparent glass substrate, 21 ... Optical system, 22 ... Marker recognition device,
23 ... Magnetic field control device, 24 ... Magnetic field application device.

Claims (2)

[Claims] 1. A plurality of circuit blocks are formed on a main surface of a substrate, a defective circuit block of the plurality of circuit blocks is removed from the substrate, and a defect relief is performed in a region of the substrate where the defective circuit block is removed. In a method of relieving a defect of a semiconductor integrated circuit device in which a special circuit block is embedded, a magnetic layer or a magnetic particle mixed layer is formed on a circuit formation surface or a back surface thereof in a region of the substrate where the defective circuit block is removed. The step of arranging the circuit blocks and the defect relieving circuit block with respect to the arrangement position of the plurality of circuit blocks or a part of the circuit blocks on the main surface of the substrate while applying a magnetic field to the defect relieving circuit block. And a step of fixing the defect relief circuit block to the substrate in a state where the arrangement position is determined. And a defect relieving method for a semiconductor integrated circuit device. 2. A defective circuit block of a substrate is replaced by a defective circuit block of the plurality of circuit blocks with respect to the arrangement positions of the plural circuit blocks or a part of the circuit blocks on the main surface of the substrate. A recognition device for recognizing the arrangement position of the defect relief circuit block arranged in the removed region, and a magnetic field applied to the magnetic layer or the magnetic particle mixed layer formed on the circuit formation surface of the defect relief circuit block or on the back surface thereof. A magnetic field applying device that gives the position of the defect relief circuit block and moves the placement position of the defect relief circuit block, and a displacement between the placement position of the circuit block on the main surface of the substrate recognized by the recognizing device and the placement position of the defect relief circuit block. A defect relieving alignment device comprising: a magnetic field control device that drives the magnetic field applying device according to the amount of the magnetic field to correct the amount of deviation.