JPH05142788A - Formation of resist pattern - Google Patents

Abstract

(57) [Summary] [Object] To provide a method capable of forming a fine resist pattern while preventing side etching. [Structure] After forming a resist layer 2 on a substrate 1, a pattern is printed on the resist layer 2. Next, the resist layer 2
The resist layer is exposed to a silylating agent to effect silylation of the area 5 baked in. After silylation,
The resist layer is partially developed so that an undeveloped portion remains. The silylation of the exposed portion in the baked area is performed. Then, the undeveloped portion is removed to finally obtain a resist pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a resist pattern in the manufacture of integrated circuits, and more particularly to a method for forming a finer resist pattern by using silylation.

[0002]

2. Description of the Related Art Today, not only information / communication devices but also many industrial devices use an integrated circuit (IC) in which transistors, resistors and capacitors are built on one chip. This IC has made them intelligent and refined in all industrial equipment. The integration degree of the IC has been further increased, and the IC has been developed into an LSI, a VLSI, and a ULSI.

About this IC, thousands of transistors were integrated on a chip of several mm square around 1970, but nowadays, several millions of transistors are integrated on the chip. There is. Meanwhile, the width of the wiring formed in the IC has been narrowed from about 10 μm to 1 μm or less.

The miniaturization of devices built into ICs and their higher density integration yields many advantages. By reducing the size of the element, the IC can be made small and lightweight, and the manufacturing cost thereof can be reduced.

Further, by integrating a larger number of elements, more connections such as soldering can be omitted, so that the reliability of the IC is improved.

In addition, if the length of the wiring connecting the elements is shortened by increasing the degree of integration, the time required for the signal processing of the IC is rapidly shortened, and the power consumption is reduced accordingly. For example, in the case of a MOS integrated circuit,
Within the range where the scaling law holds, the element size should be 1
With / k, the delay time becomes 1 / k, and the power consumption is reduced to 1 / k ² per element.

Increasing the number of elements in one chip in order to increase the degree of integration of IC depends on a technique capable of forming a large number of fine structures on a wafer. In this technique, a process of applying a resist on a wafer and then processing the applied resist into a desired shape is a key for forming a fine structure.

This process requires ten or more times in many cases to complete a VLSI. For example, in forming a transistor on a silicon substrate, a source part and a drain part are formed using a resist through the steps shown in FIG.

Referring to FIG. 5, first, a silicon substrate 51 having an oxide film 58 formed on its surface is prepared (FIG. 5).
(A)). Next, the photoresist film 52 is formed on the oxide film 58.
Is applied (FIG. 5B). Then, a photomask 53 is provided above the photoresist film 52, and ultraviolet rays 54 are applied to the photoresist film through the photomask 53 (FIG. 5C). After development and baking,
A resist pattern 52 'having a predetermined shape is obtained (FIG. 5 (d)).

Next, etching is performed to remove only the portion of the oxide film which is not covered with the resist pattern 52 '(FIG. 5 (e)). After removing the resist pattern by plasma ashing, impurities are diffused in the exposed portion of the silicon substrate, and the source portion 59 and the drain portion 60 are formed (FIG. 5F).

Further, in order to form the wiring on the substrate, for example, the steps shown in FIG. 6 are taken. Referring to FIG. 6, first, aluminum layer 70 is deposited on substrate 61 (FIG. 6A). Next, as shown in FIG. 6B, after the resist film 62 is formed on the aluminum layer 70,
Ultraviolet rays 64 are transferred through the photomask 63 to the resist film 62.
It is irradiated on top (FIG. 6 (c)). Next, development and baking are performed to obtain a resist pattern 62 '(FIG. 6 (d)).

After removing only the aluminum layer exposed by etching, the resist pattern is removed by plasma ashing to obtain a wiring layer 70 'having a desired shape (FIG. 6 (e)).

In the above-mentioned process, it is apparent that the size of the element to be formed and the width of the wiring layer depend on the size of the resist pattern. In order to form a smaller element and a wiring layer having a narrower width, it is necessary to finely process the resist film. Therefore, the resist film processing technique plays an especially important role in improving the degree of integration of ICs.

As one of the techniques for forming a finer resist pattern, there is a method using silylation and dry development. One of the most prominent of this method was that of Coopmans and Roland in 1986.
DESIRE system announced by (Pr
oceding of SPIE 631, 34 (1
986). A basic process flow regarding this system will be described below with reference to FIG. 7.

First, as shown in FIG. 7A, a resist layer 72 is formed on a substrate 71. The resist layer can be formed by using a material marketed by UCB Electronics (Belgium) or Nippon Synthetic Rubber Co., Ltd. under the product name “PLASMASK”. PLAS
MASK contains a novolac resin and quinonediazide as main components. The novolak resin and quinonediazide are represented by the chemical formulas shown below.

[0016]

[Chemical 1]

After this material has been applied to the substrate, for example by a spinner, a prebake is carried out at a suitable temperature.

Next, as shown in FIG. 7B, the resist layer 72 covered with the mask 73 is irradiated with ultraviolet rays 74 having a wavelength of 248 nm to 436 nm.

After exposure, the substrate is placed in a vacuum chamber and heated at about 120-200 ° C. The exposed region 75 of the resist layer is stable to heating, while the unexposed region 77 undergoes a crosslinking reaction by heating.

After that, at an appropriate temperature, N 2 is put in the vacuum chamber.
Hexamethyldisilazane (HM ₂ as carrier gas
DS) gas is introduced and sprayed onto the substrate. HM
The DS is selectively incorporated only in the exposed portion of the resist layer. Among the exposed parts, for example, FIG.
A silylation reaction as shown in the following equation occurs in the blackened portion 76 shown in (c).

[0021]

[Chemical 2]

Next, dry development is performed on the resist layer by using reactive ion etching (RIE).
O ₂ plasma is used in RIE.

When the dry development is started, as shown in FIG. 7D, the silicon compound SiO ₂ is formed at the portion 76 where the selective silylation is performed in the resist layer. The portion where SiO ₂ is formed resists RIE, while the portion where HMDS is not incorporated is etched by RIE because it is composed of only a substance that can be volatilized by oxidation. The dry development is finally shown in FIG.
As shown in (e), only the exposed portion of the resist layer results in a residual resist pattern.

[0024]

The DESIRE system is applied to form a fine resist pattern. However, in this system, it was easy to form a resist pattern whose side portions were shaved by RIE.
That is, as shown in FIG. 8, the resist pattern 8 in which the body is narrowed due to side etching or undercut
0 was easy to be formed. When it is desired to form a finer resist pattern, the resist pattern having such a constricted shape may be inclined or tilted.

A method for preventing such side etching by RIE in a multilayer resist film system is disclosed in Japanese Patent Laid-Open No. 2-24661. This method will be described below with reference to the drawings.

Referring to FIG. 9, first, as shown in FIG. 9A, a first resist layer 92 is formed on a semiconductor substrate 91. Next, a second resist layer 93 containing silicon is deposited on the first resist layer 92 (FIG. 9).
(B)).

Then, after forming a third resist layer 94 on the second resist layer 93 (FIG. 9C), the third resist layer 94 is exposed through a mask having a predetermined pattern ( FIG. 9D). The third resist layer is developed to obtain a resist pattern 94 '(FIG. 9 (e)). Next, anisotropic etching is performed on the second resist layer 93 using the resist pattern 94 'as a mask (FIG. 9).
(F)).

Next, anisotropic etching is performed on the first resist layer using the resist pattern 93 'formed from the second resist layer as a mask. This anisotropic etching is temporarily stopped when the first resist layer 92 is removed by about half. At this time, the resist pattern 94 'for the third layer is removed (FIG. 9 (g)).

After that, as shown in FIG. 9H, silicon is introduced on the surface 95 of the first resist layer newly formed by etching to form a silylated layer 96. Then, the horizontal portion of the silylated layer 96 is removed by anisotropic etching (FIG. 9 (i)).

After that, anisotropic etching is performed again on the first resist layer 92 and is continued until the semiconductor substrate 91 is exposed. As a result, a patterned resist 92 'is obtained as shown in FIG. 9 (j).

This method protects the first resist layer by forming a silylated layer on the side portion of the first resist layer, so that a resist layer having a narrowed side portion is formed as in the above-mentioned DESIRE. Trying to prevent it. However, this method requires forming two more resist layers in patterning the first resist layer. This increases the number of steps for forming the resist pattern.

As described above, the process for forming the resist pattern is performed many times in the manufacture of the LSI, and therefore, if the number of steps required for one process is large, the time and the time required for the manufacture of the LSI are increased. The cost also increases.

Further, in the above method, it is necessary to deposit a layer considerably thinner than the first resist layer on the first resist layer to be patterned. Such thin layers are susceptible to dust. If the layer is affected by dust and a resist pattern with a desired shape cannot be obtained, LS
The yield in I manufacturing is reduced.

Further, as shown in FIGS. 9 (h) to 9 (i), in the step of removing the horizontal plane portion of the silylated layer by anisotropic etching, if the etching direction control is poor, it is formed on the side surface. The silylated layer may also be scraped. Therefore, this method leaves the possibility of side etching as described above.

[0035]

An object of the present invention is to provide a method capable of forming a fine resist pattern without side etching or undercut in a smaller number of steps.

A further object of the present invention is to provide a method capable of forming a fine resist pattern having a desired shape with good reproducibility by using a process which is not easily affected by dust.

According to the first aspect of the present invention, there is provided a method applicable particularly to the formation of a negative resist pattern. In this method, after the resist layer is formed, predetermined areas on the resist layer are exposed. The exposed areas of the resist layer are then silylated. Subsequently, the unexposed region of the resist layer is removed halfway to expose the exposed region, and then the exposed region of the exposed region is silylated. Finally, the remaining part of the unexposed area is removed, resulting in a finished resist pattern.

The resist layer can be preferably formed from a material containing novolac resin and quinonediazide as main components. The resist material can be applied to the substrate by various means such as a spinner. Pre-baking of the resist layer is carried out at a suitable temperature and time according to the thickness of the layer.

In this method, photolithography is generally applied to expose areas of the resist layer.
In photolithography, an ordinary exposure apparatus can be used to perform exposure with ultraviolet light through a mask.
The wavelength of the ultraviolet rays can be in the range of 248 to 436 nm, for example.

After the exposure step, the exposed areas of the resist layer are silylated. Silylation can be performed, for example, by exposing the resist layer to hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), or 1,2-dichlorotetramethylsiloxane.

These reagents are preferably supplied to the resist layer by a carrier gas (for example, N ₂ ).
For example, when using HMDS, N ₂ in HMDS solution
The gas released by injecting the gas may be supplied to the resist layer.

The treatment for silylation is, for example, 160
It can be carried out at a temperature of ° C for 3 to 6 minutes.
When the resist layer is formed from a material containing a novolac resin and a quinonediazide, the silylating reagent is incorporated only in the exposed portion of the resist layer and reacts with the novolac resin to react the organic compound as shown in the chemical formula above. A silicon compound is formed. Such selective silylation is based on the conversion of quinonediazide in the resist layer into carboxylic acid by exposure. In this way, a silylated layer is formed on the exposed portion.

In the case of the negative type, the unexposed areas of the resist layer can be preferably removed by reactive ion etching (RIE). On the other hand, the exposed areas are protected by the silylated layer and are not removed by RIE. O ₂ plasma can be applied to the RIE, for example.

The time for interrupting the etching in the first removal of the unexposed region can be, for example, when the resist layer is removed by about 1/3 to 1/2 of the total thickness, It is not particularly limited. This time depends on the thickness of the resist layer. By this step, only the exposed areas are partially exposed.

The exposed portions of the exposed areas are further silylated. The silylation can be performed according to the method described above. A silylated material is selectively taken into the exposed area, and a silylated layer is formed on the exposed portion.

Finally, when the rest of the unexposed area is removed, a resist pattern having a desired shape can be obtained. RIE can be preferably used in the removal step. For example, O ₂ plasma is applied as the etching gas.

In the final removal step, the silylated layer formed on the exposed portion of the exposed region plays a role of suppressing side etching. Since the exposed portion is entirely protected by the silylated layer, RIE
Not eroded by. Furthermore, since the portion not exposed to light is etched using the portion protected by the silylated layer as a mask, the portion further exposed by the etching has a desired shape.

Also according to the first aspect of the invention there is provided a method, in particular for strictly controlling patterning. In this method, the step of partially removing the unexposed region of the resist layer and then silylating the exposed portion is performed twice or more. The number of repetitions of this step may be determined as needed. For example, this number can be increased as the resist layer becomes thicker.

In this method, the resist layer is partially removed--
It is characterized by increasing protection against etching by increasing the number of silylation steps. This method is particularly effective when it is desired to form a thick resist pattern. Further, in this method, the same method as in the above-described first invention can be applied to the formation of the resist layer, the silylation, and the removal of the resist layer.

According to the second invention, there is provided a method particularly suitable for forming a positive resist pattern. In this method, after the resist layer is formed, predetermined areas on the resist layer are exposed. The unexposed areas of the resist layer are then silylated. Subsequently, the exposed region of the resist layer is removed halfway to expose the portion of the unexposed region, and then the exposed portion of the unexposed region is silylated. Finally, the remaining part of the exposed area is removed, resulting in a finished resist pattern.

In the second invention, the resist layer can be preferably formed from a material containing a novolac resin, an acid generator and a crosslinking agent as main components. The resist material can be applied to the substrate by various means such as a spinner. The prebaking in forming the resist layer can be performed at an appropriate temperature and time according to the thickness of the layer.

In this method, electron beam lithography is generally applicable to expose a region of the resist layer. When a material consisting essentially of a novolac resin, an acid generator and a cross-linking agent is used, the region irradiated with the electron beam causes the acid generator to generate an acid. The baking after the exposure causes a crosslinking reaction between the base resin and the crosslinking agent by using the generated acid as a catalyst. The crosslinked portion takes up little silylating agent supplied in the next step. In this way, the silylating agent hardly diffuses into the exposed areas, so that only the unexposed areas are selectively silylated.

For silylation, for example, hexamethyldisilazane (HMDS), tetramethyldisilazane (TM)
DS), 1,2-dichlorotetramethylsiloxane or the like can be used. These reagents are preferably supplied to the resist layer by a carrier gas (for example, N ₂ ).

When the resist material contains a novolac resin, the silylating reagent is incorporated only in the unexposed portion of the resist layer, and reacts with the novolac resin to form the organosilicon compound as shown in the above chemical formula. To form. In this way, a silylated layer is formed on the unexposed portion.

In the case of the positive type, the exposed region of the resist layer can be removed by RIE. On the other hand, the unexposed areas are protected by the silylated layer and are not removed by RIE. O ₂ plasma can be applied to the RIE, for example. This step only partially reveals the unexposed areas.

The exposed portions of the unexposed areas are further silylated. The silylation can be performed in the same manner as the above method. A silylating agent is selectively incorporated into the unexposed area, and a silylated layer is formed on the surface of the exposed portion.

Finally, when the rest of the exposed area is removed, a resist pattern having a desired shape can be obtained. RIE can be preferably used in the removal step. For example, O ₂ plasma is applied as the etching gas.

In the final removal step, the silylated layer formed on the exposed portions of the unexposed areas is
Suppress side etch. Further, since the exposed portion is etched using the portion protected by the silylated layer as a mask, the exposed portion has a desired shape.

According to a second invention, a method is provided, in particular for tightly controlling patterning. In this method, the step of partially removing the exposed region of the resist layer and then silylating the exposed portion is performed twice or more. The number of repetitions of this step may be determined as needed. For example, this number can be increased as the resist layer becomes thicker.

In this method, the resist layer is partially removed--
It is characterized by increasing protection against etching by increasing the number of silylation steps. This method is particularly effective when it is desired to form a thick resist pattern. Further, in this method, the same method as in the above-described second invention can be applied to the formation of the resist layer, the silylation, and the removal of the resist layer.

[0061]

As described above, when the silylation is carried out again after interrupting the etching, the side surface of the exposed portion is silylated. The silylated sides are not attacked by etching. In this way, etching is performed while protecting the exposed side surface until the final resist pattern is obtained, so side etching or undercut is prevented.

[0062]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

Referring to FIG. 1A, first, a resist layer 2 is formed on the semiconductor substrate 1. A material commercially available from UCB Electronics (Belgium) or Japan Synthetic Rubber Co., Ltd. under the product name “PLASMASK” is used for forming the resist layer. Although the detailed composition of PLASMASK is not clear, PLASMASK contains a novolac resin and a quinonediazide as main components.

This material is applied onto the semiconductor substrate 1 using a spinner. The pre-baking after coating is performed at 120 ° C. for 90 seconds. The thickness of the resulting resist layer 2 is
It is 1.2 to 1.5 μm.

Next, a photomask 3 is provided on the resist layer 2 and is irradiated with ultraviolet rays 4 (FIG. 1 (b)). As the ultraviolet rays, g-rays around 500 mW or i-rays around 200 mW are used. A predetermined pattern according to the photomask is printed on the resist layer by exposure. In the exposed region 5 in FIG. 1B, a diagonal line is drawn.

Then, the substrate is transferred to the apparatus shown in FIG. 2 for the silylation treatment. Referring to FIG. 2, substrate 20 having a resist layer formed thereon is placed on heating plate 24 provided in vacuum chamber 27. Vacuum chamber 2
The inside of 7 is exhausted. Above the substrate 20 is a gas nozzle 2
1 is provided. Gas produced by bubbling N ₂ gas through the solution 25 of the silylating agent heated by the heater 26 is sprayed onto the substrate 20 from the gas nozzle 21.
The silylating agent is HMDS.

A specific example of silylation is shown below. First,
The substrate 20 is heated by the heating plate 2 in the evacuated vacuum chamber 27.
4 hold at 160 ° C. for 3 minutes. Next, the heater 2
N ₂ is bubbled through the silylating agent 25 held at 50 ° C. by 6 to introduce the silylating agent from the nozzle 21 into the vacuum chamber 27. The substrate is then exposed to HMDS vapor for 4 minutes at 160 ° C. As a result, the surface portion is silylated in the exposed region as shown in FIG. In the figure, the silylated portion 6 is filled in black.

Next, the substrate is transferred to an apparatus for dry development. A parallel plate type reactive ion etching apparatus is applied as an apparatus for dry development. Dry development is performed by RIE.

Due to etching, the flow rate of oxygen is 70 scc.
Supplied in m. The gas pressure is adjusted to 4 mmTorr. The voltage applied to the band magnetron etcher for RIE is 79V. Dry development is carried out for about 1 minute and then interrupted. Figure 1 after etching
As shown in (d), the undeveloped portion 7 is formed on the substrate 1.
Is left, the exposed area 5 is exposed.

After interrupting the dry development, the substrate is placed in the silylation apparatus again. Silylation is performed by the same procedure and conditions as described above. As a result, as shown in FIG. 1E, the side surface 6 ′ of the portion exposed by the development is newly silylated. In the figure, the newly silylated portion 6'is filled in black.

After silylation, the substrate is again transferred to the RIE apparatus and etched with O ₂ plasma. The conditions (flow rate, pressure and voltage) for etching are the same as above. The etching is continued until the semiconductor substrate is exposed. The final resist pattern is obtained by etching for about 2 minutes.

In this final development step, since the silylated layer is formed on the side surface of the exposed portion, the side surface is prevented from being scraped by RIE. For this reason, the constricted resist pattern that is a problem in the conventional DESIRE system is not formed. The side surface of the obtained resist pattern is not cut as shown in the figure.

Further, while the conventional technique using the multi-layer system requires about 10 steps to form the resist pattern, the embodiment of the present invention described above requires only about 6 steps. As described above, according to the present invention, the resist pattern can be formed without side etching or undercut in a smaller number of steps. Further, the above embodiment does not require the step of removing an unnecessary portion of the silylated layer, which is performed in the conventional technique. Therefore,
The present invention also avoids the potential side etches of conventional methods. The present invention can form a fine resist pattern having a desired shape with higher reproducibility than ever before.

A second embodiment according to the present invention will be described below with reference to the drawings. As shown in FIGS. 3 (a) to 3 (e), after the resist layer 2 is formed on the semiconductor substrate 1, the same steps as those in the first embodiment are performed, and the resist layer 2 is exposed by development. The side surface of the exposed portion is silylated.

After silylation, the substrate is again transferred to the RIE apparatus and etched with O ₂ plasma. The conditions (flow rate, pressure and voltage) for etching are the same as those in the first embodiment. However, the etching is stopped before the semiconductor substrate is exposed (FIG. 3).
(F)).

After interrupting the etching, the substrate is placed in the silylation apparatus again. Silylation is performed by the same procedure and conditions as described above. As a result, FIG. 3 (g)
As shown in, a silylated layer 26 is further formed on the side surface of the region exposed by the development. As shown above, in the second embodiment, the silylation step is performed three times.

After silylation, the substrate is again transferred to the RIE apparatus and etched with O ₂ plasma. The etching is continued until the semiconductor substrate is exposed. In this way, a final resist pattern is obtained (FIG. 3 (h)).

In the second embodiment, the etching-silylation step was performed twice, but this step can be repeated. The number of repetitions can be arbitrarily determined according to conditions such as the thickness of the resist layer.

A third embodiment according to the present invention will be described below with reference to the drawings. The third embodiment is a specific example for forming a positive resist pattern.

Referring to FIG. 4A, first, resist layer 12 is formed on semiconductor substrate 11. For the formation of the resist layer, the product name “SAL601-ER
The material commercially available as "7" is used. This material contains a novolac resin, an acid generator and a crosslinking agent as main components. Next, as shown in FIG. 4B, electron beam lithography is performed on the resist layer 12. In the region 12 ′ irradiated with the electron beam, acid is generated from the acid generator. In the region 12 ', the post-exposure baking causes a cross-linking reaction between the base resin and the cross-linking material using the generated acid as a catalyst.

Then, silylation is carried out in the same manner as in the first embodiment. The portion cross-linked by the irradiation of the electron beam hardly takes in the silylating agent, and therefore, as shown in FIG.
As shown in (c), only unexposed areas are selectively silylated. In the figure, the silylated portion 16 is filled with black.

Next, the substrate is transferred to an apparatus for dry development. Dry development is performed using RIE as in the first embodiment. The dry development is performed in the exposed area 12 '.
Will be stopped when about half is removed. As a result, as shown in FIG. 4D, the part of the unexposed region is exposed.

After interrupting the RIE, the substrate is placed in the silylation apparatus again. Silylation is carried out by the same procedure and conditions as in the first embodiment. In this way, a silylated layer 16 'is newly formed on the side surface of the portion exposed by etching (FIG. 4 (e)).

Next, the substrate is transferred to the RIE device again, and O
₂ Etched with plasma. Etching
This is continued until the semiconductor substrate is exposed. as a result,
As shown in FIG. 4F, the exposed portion is removed and a resist pattern having a desired shape is formed. Also in the third embodiment, the side etch is blocked by the silylated layer. Therefore, even if a positive resist is used, a fine resist pattern can be formed with good reproducibility as in the case of a negative resist.

In addition, although the etching-silylation step was performed only once in the third embodiment, this step can be repeated multiple times. That is, similarly to the second embodiment, after the silylation step, the development can be performed again and the development can be stopped, and the silylation can be performed again. The number of repetitions can be arbitrarily determined according to conditions such as the thickness of the resist layer.

[0086]

As described above, the present invention is
Provided is a method for preventing side etching and forming a fine resist pattern in a single-layer system for forming a single resist layer. The present invention does not require the steps of stacking multiple resist layers and the step of removing unwanted portions of the silylated layers that are required in conventional multilayer systems.

This not only enables the formation of a fine resist pattern in a smaller number of steps than in the conventional method, but also avoids side etching which is possible in the conventional method.

From the above, the present invention is particularly applicable to 1.0 μ
It can be applied to form a resist pattern having a line & space of m or less.

[Brief description of drawings]

FIG. 1 is a schematic view showing a state of a resist layer formed in each step in a first embodiment according to the present invention.

FIG. 2 is a schematic view showing one specific example of an apparatus used for silylating a resist layer according to the present invention.

FIG. 3 is a schematic diagram showing a state of a resist layer formed in each step in the second embodiment according to the present invention.

FIG. 4 is a schematic diagram showing a state of a resist layer formed in each step in the third embodiment according to the present invention.

FIG. 5 is a schematic view showing a step of forming a source part and a drain part of a transistor by using a resist pattern.

FIG. 6 is a schematic diagram showing a process for forming a wiring layer on a substrate using a resist pattern.

FIG. 7 is a schematic view showing each step of a conventional DESIRE method.

FIG. 8 is a schematic view showing a state where side etching occurs in the DESIRE method.

FIG. 9 is a schematic diagram for explaining each step of a conventional method improved to prevent side etching.

[Explanation of symbols]

 1, 11 Semiconductor substrate 2, 12 Resist layer 6, 6 ′ Silylated portion 16 ′, 26 Silylation layer

Claims (4)

[Claims] 1. A step of forming a resist layer, a step of exposing an area on the resist layer, a step of silylating an exposed area of the resist layer, and a step of exposing an unexposed area of the resist layer. Removing halfway to expose a portion of the exposed region, silylating the exposed portion of the exposed region, and removing the remaining portion of the unexposed region Forming a resist pattern. 2. A step of partially removing an unexposed region of the resist layer to expose a portion of the exposed region, and then silylating the exposed portion of the exposed region. The method for forming a resist pattern according to claim 1, wherein the method is repeated twice or more. 3. Forming a resist layer, exposing a region on the resist layer, silylating an unexposed region of the resist layer, and exposing the exposed region of the resist layer. Remove it halfway,
Exposing a portion of the unexposed region, silylating the exposed portion of the unexposed region, and removing the remaining portion of the exposed region to obtain a resist pattern And a step of forming a resist pattern. 4. A step of partially removing an exposed region of the resist layer to expose a portion of an unexposed region, and then silylating the exposed portion of the unexposed region. The method for forming a resist pattern according to claim 3, wherein the step is repeated twice or more.