JPH05159587A - Nonvolatile memory and writing system - Google Patents

Abstract

(57) [Summary] (Modified) [Objective] To provide a non-volatile memory device and a writing method capable of rewriting in a block unit and increasing the substantial number of times of rewriting. [Structure] For the source lines CS0 to n of the non-volatile memory elements M1 to 8 shared by each block, the ground potential of the circuit is applied to the block selected at the time of writing, and the non-selected block is supplied. In contrast, the potential difference between the floating gate and the source / drain is reduced. Alternatively, in one memory block, word lines W0 to m and source lines CS such that a high voltage is not supplied to the word lines W0 to m in a non-selected memory block at the time of writing.
The configuration is 0 to n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor non-volatile memory device and a writing method, for example, a batch erasing type EEPROM (Electrical Erasable & Programmable Read Only.
Memory) is related to effective technology.

[0002]

2. Description of the Related Art Nonvolatile memory devices include an EPROM (erasable & programmable read only memory) capable of erasing stored information by ultraviolet rays, and an electrically erasable EEPROM described above. EPROM
Is suitable for large storage capacity due to its small memory cell area, but requires a package with a window to erase stored information by UV irradiation and removes it from the system at the time of rewriting because the programmer writes. There are problems such as the necessity.

The EEPROM is electrically rewritable in the system, but the size of the memory cell is EPROM.
Since it is about 2.5 to 5 times larger, it is not suitable for increasing the storage capacity. Therefore, recently, as an intermediate non-volatile memory device between the two, an electrically collective erasing type EEPROM is used.
Is being developed. Electrically erasable type E
The EPROM is a non-volatile memory device having a function of electrically erasing a chip or a group of memory cells collectively. The size of the memory cell can be made as small as the EPROM. Regarding the batch erase type EEPROM, the page of 1980 International Solid State Conference (ISSCC)
152 and 1987 International Solid State Conference (ISSCC) page 7
6, as well as the IEE Journal of Solid State Circuits, Vol. 23, No. 5, pp. 1157 to 1163 (IEEE, J. Solid-S).
tate Cicuits, vol.23 (1988) pp.1157-1163).

FIG. 14 shows a memory cell of an electrically erasable EEPROM which was announced at the 1987 International Electron Device Meeting. The memory cell shown in FIG.
It has a two-layer gate structure much like a PROM. The write operation is performed by injecting hot carriers generated in the vicinity of the junction of the drain 3 into the floating gate 4, similarly to the memory cell of EPROM. The write operation raises the threshold voltage seen from the control gate 6 of the memory cell. On the other hand, in the erase operation, the control gate 6 is grounded, a high voltage is applied to the source 5 to generate a high electric field between the floating gate 4 and the source 5, and the tunnel phenomenon through the thin oxide film 7 is used. Then, the electrons accumulated in the floating gate 4 are extracted to the source 5. The erase operation lowers the threshold voltage seen from the control gate 6. For reading, a low voltage of about 1 V is applied to the drain 3 so that weak writing is unlikely to occur, and about 5 V is applied to the control gate 6 so that the magnitude of the flowing channel current corresponds to "0" and "1" of information. In the figure, 8 is a P-type silicon substrate, 9 is an N-type diffusion layer, 10 is a low concentration N-type diffusion layer, and 11 is a P-type diffusion layer.

[0005]

Prior to the present invention, the inventors of the present application can divide one memory array (or memory mat) into a plurality of blocks and erase each block as shown in FIG. Considered a non-volatile memory device. In the figure, the memory cell shown as an example is constituted by the nonvolatile memory element as shown in FIG.

In the figure, when writing (1 → 0) to the memory cell M1 of the memory block MB0, the word line W0 is set to a high level such as 12 V, and the data line D0 is set.
0 is set to 6V by the activated write amplifier WA.
High level is supplied. The source of the memory cell is an erase circuit ERS provided corresponding to each of the memory blocks MB0 to MBn except the erase operation.
The ground potential 0V of the circuit is applied through 0 to ERSn. As a result, hot electrons as described above are generated in the memory cells of the memory block MB0,
By injecting it into the floating gate, the threshold voltage is changed to a high value as described above.

At this time, in the memory cell MB5 in the erased state (1 state) of the memory block MBn in which writing is not performed, which is shown as an example, the word line W0
Is raised to about 7V, the floating gate is raised to about 7V.
As a result, a relatively high electric field acts between the floating gate and the source, a weak tunnel current is generated through the thin tunnel oxide film, and electrons are injected into the floating gate. In the case of erasing for each memory block as described above, in the worst case, other memory blocks MB0 other than the memory block MBn
When erasing and writing are repeatedly performed in a memory block MBn, etc., the weak write operation due to the tunnel current is repeated for the memory cells in the erased state in the memory block MBn each time. As shown, it has been found that there is a problem that the erase level of the memory cell, which should be maintained near 1 V, changes significantly. Therefore, if one memory array is divided into a plurality of memory blocks and a selective erasing operation (rewriting) is performed for each memory block, the number of rewritable times is significantly reduced,
Usability becomes extremely poor. The characteristic diagram of FIG. 15 has been obtained by the inventors of the present application using computer simulation.

An object of the present invention is to provide a non-volatile memory device and a writing system which can rewrite in block units and can substantially increase the number of times of rewriting. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of non-volatile memory elements, each having a plurality of non-volatile memory elements in which a control gate is coupled to the same word line, are arranged in a matrix in which non-volatile memory elements that erase accumulated charges in a floating gate by a tunnel current through a tunnel insulating film are arranged in a matrix. In a non-volatile memory device having a memory array that is divided into blocks and enabled to erase in each block, the source line of the non-volatile memory element shared in each block is selected at the time of writing. The ground potential of the circuit is given to the block, the predetermined bias voltage that reduces the potential difference between the floating gate and the source and drain is given to the non-selected block, and the source that gives the predetermined high voltage at the time of erasing. Provide a switch circuit. Alternatively,
In one memory block, a word line and a source line are configured so that a high voltage is not supplied to the word line in a non-selected memory block during writing.

[0010]

According to the above-described means, a predetermined bias voltage for reducing the potential difference between the floating gate and the source / drain is applied to the non-selected block at the time of writing, or the word line is provided for each block. Since the source line is divided into two, the generation of an undesired tunnel current due to the write operation in the non-selected memory block can be prevented or reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of an electrically batch erase type EEPROM (hereinafter also referred to as a flash memory) to which the present invention is applied. Although not particularly limited, each circuit block shown in the figure is formed on one semiconductor substrate by a well-known semiconductor integrated circuit technique. Further, in the figure, the mark "○" indicates an external terminal provided in the flash memory.

In FIG. 1, a plurality of word lines, a plurality of data lines arranged so as to intersect these word lines, and a non-volatile memory element provided at each intersection of the word lines and the data lines ( Hereinafter, a memory array (or memory mat) in which memory cells are arranged in a matrix.
Are divided into memory blocks MB0 to MBn. In the memory array, word lines are arranged so as to extend in the horizontal direction, and the control gates of the memory cells are coupled to the word lines. Further, a data line (or sometimes referred to as a bit line or a digit line) and a source line are arranged to extend in the vertical direction, and the drain and the source of the memory cell correspond to these data line and source line, respectively. And are commonly connected.

ADB is an address buffer, which receives the external address signals A0 to Ai supplied through the external terminals and responds to the internal address signal ax corresponding to the X system address signal and the Y system address signal. Internal address signal a
form y. XDC is an X-system decoder that receives the internal address signal ax formed by the address buffer ADB and decodes the internal address signal ax. Although not particularly limited, in the present embodiment, the address buffer ADB and the X-system decoder XDC are common to the memory blocks MB0 to MBn of the memory array. That is, the X system decoder XDC
Decodes the internal address signal ax to generate the memory array (memory blocks MB0 to MB).
A word line selection signal for selecting one word line designated by the internal address signal ax is formed from the plurality of word lines in each of n). As a result, one word line common to the memory blocks MB0 to MBn is selected.

In the figure, YDC is a Y-system decoder, which decodes the internal address signal ay formed by the address buffer ADB to generate the internal address signal a.
A data line selection signal according to y is formed. Of the plurality of data lines provided in each memory block MB0 to MBn of the memory array, one data line designated by the internal address signal ay is a common data line (not shown) commonly provided in each memory block. To bind to Y
A gate YG is provided. The Y gate YG receives the data line selection signal formed by the Y-system decoder and connects the one data line to the corresponding common data line.

In this way, the memory blocks MB0 to MB0
In the memory array composed of MBn, one word line and one data line according to the X-system internal address signal ax and the Y-system internal address signal ay corresponding to the address signals A0 to Ai supplied from the outside. Is selected, and the memory cell provided at the intersection of the selected word line and data line is selected. That is, the memory cell coupled to the selected word line and data line is selected from the plurality of memory cells in the memory array.

When a plurality of memory cells are selected by one memory access, in other words,
When writing / reading a plurality of bits of data, a plurality of memory arrays as described above are provided. Although not particularly limited, in this embodiment, data writing / reading is performed in units of 8 bits. At this time, if the memory array as above is 8
Individually provided.

In this embodiment, the write operation or the read operation is performed almost simultaneously on the memory cells selected from each of the eight memory arrays as described above. That is, information writing or reading operation is performed in 8-bit units. Therefore, the flash memory of the present embodiment is provided with eight external input / output terminals D0 to D7, and between the memory array of eight and the corresponding external input / output terminals D0 to D7, An input / output circuit IOB including a data input buffer and a data output buffer, a sense amplifier SA as a read circuit, and a write amplifier WA as a write circuit are provided. Eight of these sense amplifiers SA and write amplifiers are prepared according to the memory array of eight as described above, and each of them is an external input / output terminal D.
It corresponds to 0 to D7.

In the figure, CLG is a control circuit having a control function of automatic erasing, and is composed of an external signal or voltage supplied to the external terminals CEB, OEB and WEB and the high voltage VPP, and a signal from the internal circuit. In response, a timing signal required for a series of erase operations is formed. Terminal CEB
Is a control input terminal to which a chip enable signal is input, OEB is a control input terminal to which an output enable signal is input, and WEB is a control input terminal to which a write enable signal is input. Also, VCC
Is an external terminal for supplying a power supply voltage VCC of about 5V to each circuit, and GND is an external terminal for supplying a circuit ground potential 0V to each circuit block. VP
P is a high voltage terminal to which a high voltage such as 12 V is input during writing and erasing.

In this embodiment, in order to enable erasing in blocks, the source switch circuits SS0 to SSn are connected to the common source line in which the sources of the memory cells provided in the memory blocks MB0 to MBn are shared. It is provided. The source switch circuits SS0 to SSn have a ternary output function, and generate a bias voltage according to the operation mode by the write control signal PROG formed by the control circuit CLG, the erase control signal ERASE, and the block selection signals S0 to Sn. One of the bias voltage VS formed by the circuit BVG, the high voltage VPP, and the ground potential 0V of the circuit is selectively output.

The control circuit CLG designates each memory block MB0-MBn from among the Y-system address signals ay in order to generate the selection signals S0-Sn for a plurality of memory blocks as described above. A signal is input. The control circuit CLG sends a control signal to the input / output circuit IOB through the signal line IOC for controlling write and read operations, but is not particularly limited.
It receives a command input from the terminals D0 to D7 in a specific input mode and forms a mode signal for various internal sequence operations. Further, the control signal CLG supplies the control signal PROG to the write amplifier WA.

The EEPROM is in a non-selected state when the terminal CEB is at a high level and a high voltage is not supplied to the terminal VPP. If the terminal CEB is at the low level, the terminal OEB is at the low level, and the terminal WEB is at the high level, the read mode is set. When a high voltage is supplied to the terminal VPP and the terminal CEB is at the low level and the terminal WEB is at the low level, the command input mode is set, and various program modes are executed according to the input bit pattern input from the terminals D0 to D7. .. This program mode includes, for example, a write mode, all block batch erase, and selective erase mode for each block. The number of control terminals may be increased so that the internal operation mode is instructed only by the combination of control terminals without using the above command.

FIG. 2 shows an EEPR to which the present invention is applied.
A circuit diagram of a memory array portion and main peripheral circuits, which is an embodiment of the OM, is shown. Although not particularly limited, each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. In the figure, the P-channel MOSFET has an N-channel M-channel by adding an arrow to its channel (back gate) part.
It is distinguished from OSFET. This also applies to other drawings.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. The N-channel MOSFET is composed of a source region, a drain region formed on the surface of the semiconductor substrate and polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region via a thin gate insulating film. Composed of various gate electrodes. P-channel MOSFET is
It is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate constitutes a common substrate gate of the plurality of N-channel MOSFETs formed on the semiconductor substrate, and the ground potential of the circuit is supplied. The N-type well region has a P-channel MOSFET formed thereon.
The substrate gate of. The substrate gate or N-type well region of the P-channel MOSFET is coupled to the power supply voltage Vcc. However, in the case of a high-voltage circuit, the N-type well region in which the corresponding P-channel MOSFET is formed is connected to the externally applied high voltage VPP, internally generated high voltage, or the like. Alternatively, the integrated circuit is a single crystal N
It may be formed on a semiconductor substrate made of type silicon. In this case, the N-channel MOSFET and the non-volatile memory element are formed in the P-type well region and the P-channel MOSFE is formed.
T is formed on the N-type substrate. In the present invention, MOSFET is used to mean an insulated gate field effect transistor (IGFET).

As the memory array, two memory blocks MB0 and MBn are shown as a representative. This memory array includes stacked memory cells (nonvolatile memory elements ... MOSFETs M1 to M8) having control gates and floating gates and word lines W0 to Wm.
And data lines D0, D1 to Dj, and Dj + 1. Although not particularly limited, the memory cells M1 to M8 have the same structure as that of FIG. That is, these memory cells M1 to M8 are the same as the conventional EP as described above.
Although it has a structure similar to that of the memory cell of the ROM, the erase operation is electrically performed by utilizing the tunnel phenomenon between the floating gate and the source coupled to the source line as will be described later. This is different from the EPROM erasing method used.

For the memory blocks MB0 and MBn shown by way of example above, the memory cells M1 arranged in the same row.
And M2 and M5 and M6 (M3 and M4 and M7 and M8) have their control gates respectively corresponding to the word line W0.
(Wm). The word lines W0 and Wm are level conversion circuits LVC0 and LVC that form a word driver.
driven by m. When the output of the decoder circuit DEC is set to the low level, the low level is transmitted through the cutting MOSFET Q10 and the N-channel type MOSF.
ETQ8 turned off, P-channel MOSFETQ
Turn 7 on. As a result, the high voltage VPP is transmitted to the word line W0. When the output signal of the decoder circuit DEC is at high level, the cutting MOSFET Q
The N-channel MOSFET Q8 is turned on through 10 to lower the word line W0 to a low level such as the ground potential of the circuit. This low level turns on the feedback P-channel MOSFET Q9 to raise the input signal to the high voltage VPP. As a result, the P-channel MOSFET Q7 can be turned off. With such an increase in the input signal, the cutting MOSF
Since the ETQ 10 is turned off, it is possible to prevent a direct current from flowing from the high voltage VPP to the decoder circuit DEC that operates at the power supply voltage VCC to form a high level output signal. During the read operation, VPP
Are switched to VCC.

Memory cells M1 and M3 arranged in the same column
And M2 and M4 drains correspond to the corresponding data lines D
0 and D1 connected to memory cells M5, M7, M6 and M
8 drains correspond to the corresponding data lines Dj and Dj +, respectively.
It is connected to 1. The sources of the memory cells M1 to M4 of the memory block MB0 are connected to the corresponding common source line CS0, and the sources of the memory cells M5 to M8 of the memory block MBn are the corresponding common source line C.
Connected to Sn.

Although not particularly limited, since writing / reading is performed in a unit of a plurality of bits such as 8 bits (or 16 bits), the memory array has a total of 8 bits.
A plurality of sets such as a set (or 16 sets) are provided. In the same figure, a circuit for one bit is shown.

Each of the data lines D0 to Dj + 1 forming one memory array is a column selection switch MOSFET Q20, Q for receiving the selection signals Y0, Y1 to Yj, Yj + 1 generated by the Y system decoder YDC.
It is connected to the common data line CD via 21 to Q24 and Q25. The common data line CD is the write amplifier WA0.
Connected to the output terminal of. This write amplifier WA0
Among the external terminals D0 to D7, from the MOSFET Q15 receiving the output signal Di of the write data input buffer for receiving the write signal input from the corresponding D0 terminal, the MOSFET Q16 receiving the bias voltage VP, and the MOSFET Q17 receiving the control signal PROG. And transmits the voltage of the high voltage terminal VPP to the common data line CD. MOSFET Q16 is a MOSFET
This is to prevent a high voltage such as a high voltage VPP from being directly applied between the drain and gate of Q17 or Q15, and MOSF in which an intermediate high voltage VP is supplied to the gate.
By inserting the ETQ16, these voltages are divided to reduce the voltage applied to the individual MOSFETs Q17 and Q15.

On the other hand, the common data line CD is connected to a sense amplifier SA via a switch MOSFET Q11.
0 input stage circuit coupled to the input terminal. MOSFETs Q12 to Q14 for amplifying the input stage, control inverter circuits N2 and N3, and CMOS inverter circuit N
A circuit constituted by 4 and 4 will be called a sense amplifier SA0. The operating voltage VCC ′ of the sense amplifier SA0 is not particularly limited, but a power supply voltage VCC such as 5V is supplied during normal read, and is switched to a predetermined voltage lower than 5V during erase verify as described later. The MOSFET Q11 has a control signal PRO.
It is controlled by the output signal of the inverter circuit N1 which receives G, and is turned off in the write operation. As a result, the relatively high potential of the common data line CD at the time of writing is not supplied to the input of the sense amplifier SA0.

The storage level of the memory cell read to the common data line CD is MO which is turned on at the time of reading.
Through the SFET Q11, the source is connected to the source of the N-channel type amplification MOSFET Q12 to which the source is connected. A P-channel type load MOSFET Q13 whose gate and source are connected is provided between the drain of the amplification MOSFET Q12 and the power supply voltage terminal VCC '. The load MOSFET Q13 operates so as to flow a precharge current to the common data line CD for the read operation.

In order to increase the sensitivity of the amplification MOSFET Q12, the voltage of the common data line CD via the switch MOSFET Q11 is supplied to the inputs of the inverter circuits N2 and N3 which function as an inverting amplification circuit. The output signal of the inverter circuit N3 serving as the inverting amplifier circuit is supplied to the gate of the amplifier MOSFET Q12. Further, a MOSFET acting as a limiter is provided for the source input.
Charge-up is performed from the power supply terminal VCC 'via Q14. The output signal of the inverter circuit N2 as an inverting amplifier circuit is supplied to the gate of the MOSFET Q14.

At the time of reading the memory cell, the memory cell has a high threshold voltage or a low threshold voltage with respect to the selection level of the word line according to the information charges accumulated in the floating gate. If the memory cells selected by the X-system and Y-system decoders XDC and YDC are turned off even though the word line is at the selection level, the common data line CD
Is brought to a relatively high level by the current supply from MOSFETs Q12 and Q14. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level.

In this case, as for the high level of the common data line CD, the output voltage of the relatively low level formed by the inverting amplifier circuit receiving this high level potential is MOSFET.
It is limited to a relatively low potential by being supplied to the gate of Q14. On the other hand, as for the low level of the common data line CD, the voltage of a relatively high level formed by the inverting amplifier circuit receiving this low level potential is MOSFET Q1.
It is limited to a relatively high potential by being supplied to the gate of 4. Due to the level limiting action of the common data line CD, the signal change speed when the stored information continuously read from the memory cell changes from 1 level to 0 level, or when it changes from 0 level to 1 level. Can be substantially faster.

The amplifying MOSFET Q12 carries out an amplifying operation of the grounded source input of the gate and transmits the output signal to the input of the CMOS inverter circuit N4. CMOS
The inverter circuit N4 waveform-shapes the drain output signal of the amplification MOSFET Q12 and transmits it to the input of the corresponding data output buffer DOB. Data output buffer DOB
Amplifies the signal from the sense amplifier SA0 and sends it out from the corresponding external terminal D0. Although not shown in the figure, the write signal supplied from the external terminal D0 is input to the data input buffer, and its output signal Di is supplied to the gate of the MOSFET Q15 of the write amplifier WA0.

In this embodiment, each memory block MB0
To enable a selective erase operation for each MBn to MBn, common source lines CS0 to C of each memory block MB0 to MBn
Source switch circuits SS0 to SSn as erase control circuits are provided corresponding to Sn. In the figure, a concrete circuit of the source switch circuit SS0 is shown as a representative.

The source switch circuit SS0 includes a P-channel MOSFET Q6 which supplies a high voltage VPP to the source line CS0 at the time of erasing, and a common source line CS0 at the time of writing.
N-channel MOSFET that supplies 0V to ground potential
A P-channel MOSFET Q4 for supplying an intermediate bias voltage VS formed by Q5 and a bias voltage generation circuit BVG which will be described later is provided. This MOSF
ETQ4 and Q5 are complementarily switch-controlled at the time of writing.

The gate of the P-channel MOSFET Q6 has a block selection signal S0 and an erase control signal ERASE.
The output signal of the NAND gate circuit G1 for receiving the signal is supplied. The gate of the P-channel MOSFET Q4 is supplied with the output signal of the inverter circuit N receiving the block selection signal S0 and the output signal of the NAND gate circuit G2 receiving the write control signal PROG. The output signal of the OR gate circuit G5 is supplied to the gate of the N-channel MOSFET Q5. This OR gate circuit G
The input signal 5 is supplied with the output signal of the NOR gate circuit G3 receiving the erase control signal ERASE and the write control signal PROG, and the output signal of the AND gate circuit G4 receiving the write control signal PROG and the block selection signal S0.

In read operations other than programming / erasing, the control signals ERASE and PROG are both set to low level "0". Therefore, the output signal of the NOR gate circuit G3 becomes high level "1" and the output signal of the OR gate circuit G5 becomes high level.
The OSFET Q5 is turned on. At this time, the output signals of the NAND gate circuits G1 and G2 are the same as the above-mentioned signal ERAS.
In response to the low level "0" of E and PROG, the high level is set, and the P-channel MOSFETs Q4 and Q6 are both turned off. As a result, the ground potential of the circuit is supplied to the common source line CS0 by the MOSFET Q5 which is turned on.

In the write operation, the erase control signal ERASE is at the low level and the write control signal PRO is
G is set to high level. In the memory block MB0 in which writing is performed, the output signal of the AND gate circuit G4 becomes high level due to the high level of the write control signal PROG and the high level of the block selection signal S0, and the output signal of the OR gate circuit G5 becomes high in the same manner as above. To level. As a result, the MOSFET Q5 is turned on and the ground potential of the circuit is supplied to the common source line CS0. At this time, due to the low level of the erase control signal ERASE, the output signal of the NAND gate circuit G1 goes high, turning off the MOSFET Q6. Further, since the output signal of the inverter circuit N is set to low level by the high level of the block selection signal S0, the output signal of the NAND gate circuit G2 is set to high level. As a result,
The MOSFET Q4 is also turned off.

In the write operation in which the erase control signal ERASE is at the low level and the write control signal PROG is at the high level, when writing is not performed in the memory block MB0 by writing in another memory block, The output signal of the NAND gate circuit G2 becomes low level due to the high level of the output signal of the inverter circuit N receiving the low level of the block selection signal S0 and the high level of the write control signal PROG. As a result, the P-channel MOSFET Q4 is turned on, and the bias voltage VS formed by the bias voltage generation circuit BVG is applied to the common source line CS0. At this time, due to the low level of the erase control signal ERASE, the output signal of the NAND gate circuit G1 goes high, turning off the MOSFET Q6. Further, the output signal of the AND gate circuit G4 is low level due to the low level of the block selection signal S0, and the output signal of the NOR gate circuit G3 is low level due to the high level of the write control signal PROG.
The output signal of 5 also becomes low level and the MOSFET Q5 is turned off.

In the erase operation, the erase control signal E
RASE is at high level and the write control signal PROG is at low level. Memory block M to be erased
In B0, the output signal of the NAND gate circuit G1 becomes low level due to the high level of the erase control signal ERASE and the high level of the block selection signal S0, and the P-channel MOSFET Q6 is turned on. As a result, the high voltage VPP is supplied to the common source line CS0. At this time, the low level of the write control signal PROG causes the output signal of the NAND gate circuit G2 to go high, turning off the MOSFET Q4. Further, since the output signals of the NOR gate circuit G3 and the AND gate circuit G4 are both set to the low level according to the low level of the write control signal PROG, the output signal of the OR gate circuit G5 is also set to the low level and the MOSFET Q5 is also turned off.

In the erase operation, the erase control signal E
RASE is at high level and the write control signal PROG is at low level. When the memory block MB0 is not erased in response to the erasing of another memory block, the common source line CS0 is placed in the high impedance state. That is, since the output signal of the NAND gate circuit G2 becomes high level by the low level of the write control signal PROG, the MOSFET Q4 is in the off state, and the output signal of the NOR gate circuit G3 is at the low level according to the high level of the erase control signal ERASE. Since the output signal of the AND gate circuit G4 is at low level according to the low level of the control signal PROG,
The FET Q5 is in the off state, and the output signal of the NAND gate circuit G1 is at the high level in response to the low level of the block selection signal S0, so that the MOSFET Q6 is in the off state. Instead of this configuration, in the erase operation, the common source line CS0 of the memory block that is not erased may be set to the ground potential of the circuit. That is, the erase control signal ERASE and the block selection signal inverted by the inverter circuit may be supplied to the AND gate circuit, and the output signal thereof may be supplied to the input of the OR gate circuit G5. Other source switch circuits SS1 to SS1 whose specific circuits are not shown
The configuration and operation of SSn are similar to those of the circuit described above, and therefore description thereof is omitted.

The bias voltage generating circuit BVG is composed of the following circuits. The Zener diode ZD and the current limiting MOSFET Q2 are connected in series. The high voltage VPP is supplied to this series circuit through a P-channel MOSFET Q1 which is switch-controlled by the output signal of the inverter circuit which receives the write control signal PROG. Although it is not particularly limited, the MOSFET can be applied to the Zener voltage.
The voltage is divided by the series resistors R1 and R2 by adding a threshold voltage between the gate and the source of Q2. This divided voltage is transmitted to the gate of the source follower output MOSFET Q3. The drain of the MOSFET Q3 is connected to the power supply voltage VCC, and the source outputs the bias voltage VS.

In this embodiment, MOSFETs Q2 and Q3
Assuming that the threshold voltages of the two are substantially equal, the Zener constant voltage by the Zener diode ZD is divided by the resistors R1 and R2, so that a constant voltage that does not depend on the power supply voltage VCC or the high voltage VPP can be formed. it can. By supplying such a constant voltage VS to the common source line of the memory block in which the writing is not performed in the write operation, the voltage difference between the floating gate and the source of the memory cell in the erased state in the write-unselected memory block. Is made small so that the tunnel injection current flowing therethrough is substantially prevented.

FIG. 3 shows a circuit diagram of an embodiment of the block selection signal generating circuit. In the figure, selection signals S0 and S corresponding to one memory block MB0 and MBn are shown.
The circuit forming n is exemplarily shown as a representative.
This circuit is not particularly limited, but the control circuit CL of FIG.
Included in G. A Y-system address signal ay corresponding to a plurality of blocks into which the memory array is divided is supplied to NAND gate circuits NAND1 and NAND2 as a decoding circuit.

For example, when the memory array is divided into eight memory blocks, the address signal of the upper 3 bits of the Y-system address signal composed of a plurality of bits is used, and the combination of the eight decoded signals is used. Is formed. The write control signal PROG and the erase control signal ERASE are input to the NOR gate circuit NOR3.
The output signal of the NOR gate circuit NOR3 is used as a gate control signal of the NOR gate circuits NOR1 and NOR2 which outputs the output signals of the NAND gate circuits NAND1 and NAND2. That is, the above decoded signal is
Write control signal PROG or erase control signal ERASE
Only when the writing operation or the erasing operation is instructed by, any one of the selection signals corresponding to the Y-system address signal ay is output. When the batch erase function is added, a logic gate for invalidating the decode output by the batch erase control signal and setting all the signals S0 to Sn to the high selection level may be added.

FIG. 4 shows a circuit diagram of another embodiment of the bias voltage generating circuit. In the figure, for simplification of the drawing, the circuit symbols attached to the circuit elements partially overlap with those of the other elements, but it should be understood that each has a separate circuit function. This also applies to the other drawings below. In this embodiment, FIG.
The resistors R1 and R2 of the bias voltage generating circuit BVG shown in FIG.
Instead, MOSFETs Q4 and Q5 are used. That is, the gates and drains of the N-channel MOSFETs Q4 and Q5 are commonly connected and used as a resistance element. In this embodiment, the voltage division ratio is set by the conductance ratio corresponding to the channel width ratio of the MOSFETs Q4 and Q5.

FIG. 5 shows a circuit diagram of another embodiment of the bias voltage generating circuit. In this embodiment, FIG.
Instead of forming a constant voltage by the Zener diode ZD shown in FIG. 1 and dividing it to obtain a bias voltage, the high voltage VPP is divided by the conductance ratio of the P-channel type MOSFET Q4 and the N-channel type MOSFET Q5. To obtain the voltage of. To increase the voltage division ratio, MOSFETs Q4 and Q5
Are formed in a relatively large size. Therefore, by inserting the current limiting MOSFET Q1 in series, the MOSFET Q1
This is to limit the direct current flowing through 4 and Q5. Further, the N-channel MOSFET Q5 is controlled by the write control signal PROG so that the bias voltage is output only during the write operation, and the P-channel MOSFET is controlled by the signal inverted by the inverter circuit N1.
Q4 is controlled. With this configuration, a special manufacturing process for forming the Zener diode on the semiconductor substrate can be omitted.

FIG. 6 shows a circuit diagram of still another embodiment of the bias voltage generating circuit. In this example,
N-channel type MOSFE of FIG. 5 as a current limiting element
Instead of TQ1, a depletion type MOSFET Q6 is used. In this way depletion type MOS
When the FET Q6 is used, a current limiting operation is performed by a constant current by connecting the gate and the source thereof, and the high voltage VPP is divided by the MOSFETs Q4 and Q5. Therefore, as shown in FIG. This can be done without being affected by voltage variations.

FIG. 9 is a characteristic diagram showing the relationship between the number of rewrites and the threshold voltage in the erased state of the flash memory according to the present invention. In the flash memory of FIG. 2, similarly to the above, for example, the memory cell M1 of the memory block MB0
When writing (1 → 0) to the word line, the word line W0 is set to 1
A high level such as 2V is set, and a high level such as 6V is supplied to the data line D0 by the activated write amplifier WA. Hot electrons as described above are generated in the memory cells of the memory block MB0 and injected into the floating gate to change the threshold voltage to a high value as described above. At this time, a predetermined bias voltage VS is applied to the other memory blocks MB1 to MBn where writing is not performed through the source switch circuits SS1 to SSn. As a result, the potential difference between the floating gate and the source is reduced in the memory cells M5, M6, etc. by being coupled to the word line W0 of the memory blocks MB1 to MBn in which writing is not performed and being placed in the erased state "1". The tunnel current through the tunnel oxide film can be prevented or significantly limited.

In the figure, the bias voltage VS is 0V, 1
The computer simulation results are shown for V, 2V and 3V. That is, when the bias voltage VS is set to 0V as in the conventional case, the threshold voltage increases after rewriting about 1000 times, and the write error state is substantially caused. On the other hand, when the bias voltage VS is increased to 1V, 2V, and 3V, the increase of the threshold voltage is decreased with the increase of the voltage, and the change of the threshold voltage is not observed at 3V.

FIG. 10 is a characteristic diagram showing the relationship between the number of rewrites and the threshold voltage in the write state of the flash memory according to the present invention. In the same figure, the characteristics of the write level in the non-selected word line of the memory block in which writing is not performed are obtained. That is, the effect of increasing the bias voltage VS as 3 V, 4 V, 5 V and 6 V was investigated. When the potential of the common source line in the non-selected memory block in which the above writing is not performed is increased, the electric field in the opposite direction acts on the memory cell coupled to the non-selected word line. That is, the potential of the non-selected word line is 0 V, and when the potential of the source is raised to 3 V or higher as described above, an electric field acts in the opposite direction between the floating gate and the source, and the write state "0 The threshold voltage of the memory cell placed in "is reduced. In other words, the erase operation will be substantially performed.

From the above, it is understood that, in the flash memory which performs the block erase operation, there is an upper limit to the bias voltage applied to the common source line of the non-selected memory block during the write operation. From this, the bias voltage VS is constant in consideration of the film pressure and film quality of the tunnel insulating film of the memory cell, the capacitance ratio of the parasitic capacitance between the control gate and the floating gate and the parasitic capacitance between the floating gate and the source, and the like. It is set to a voltage with an upper limit.

When the bias voltage VS is a constant voltage using a Zener diode or the like, the power supply voltage V
It is a constant voltage that is not affected by CC. As described above, if the source potential becomes too high, it adversely affects the memory cell in the written state, and if the source potential becomes low, the retention characteristic of the memory cell in the erased state is weakened. Therefore, it is desirable to use a constant voltage to guarantee the number of rewrites.

FIG. 7 shows a circuit diagram of essential parts of another embodiment of the flash memory according to the present invention. In this embodiment, the memory array is divided into two, that is, two memory blocks MB0 and MB1. The word line is divided at the center and separated into right and left, and level conversion circuits LVC0L and LVC0R as word drivers are provided in each. As described above, the source switch circuits SS0 and S0 are provided according to the memory blocks MB0 and MB1 divided into two.
S1 is provided.

In this configuration, for example, the memory block MB
When writing to 0, all the word lines of the non-selected memory block MB1 can be set to the non-selected low level. Therefore, in the unselected memory block MB1, no tunnel current flows in the memory cells in the erased state. As a result, in the non-selected memory block MB1, the potential of the source line may be set to the ground potential of the circuit in the write operation as well as in the read operation, without applying the intermediate bias voltage VS as described above. .. From this, the source switch circuit SS
0 can be greatly simplified. That is, the potential of the source line may be the ground potential of the circuit except in the erase operation, so that the P-channel MOSFET transmitting the high voltage VPP.
The output signal of the NAND gate circuit G1 that receives the block selection signal S0 and the erase control signal ERASE is supplied to the gate of Q6, and the P-channel type M that transmits the ground potential of the circuit is supplied.
The erase control signal ERASE is applied to the gate of the OSFET Q5.
The output signal of the inverter circuit N0 which receives the signal is supplied.

FIG. 8 shows a circuit diagram of a main part of still another embodiment of the flash memory according to the present invention. In this embodiment, the memory array is divided into a plurality of blocks for each word line. That is, one memory block is composed of a plurality of word lines as a unit. The sources of the memory cells in this memory block are shared and connected to the source line. Therefore, although not particularly limited, it is convenient in layout that the source line is extended in parallel with the word line instead of being extended in parallel with the data line as in the above embodiment. In this configuration, the X-system address signal is used as the block selection signal instead of the Y-system address signal corresponding to the data line as described above. Although not shown,
When the word lines of the memory array are divided into eight to form eight memory blocks, eight block selection signals are used as the block selection signal by using the upper 3 bits of the X-system address signal. It is formed.

With this configuration, since only one word line is selected in the memory array at any one time, when writing to the memory block MB0, for example, word lines of other memory blocks MBn to be unselected are selected. Are set to non-selected low level. Therefore, in other unselected memory blocks Bn or the like, no tunnel current flows in the erased memory cells. As a result, in the unselected memory blocks MBn and the like, the potential of the source line is set to the ground potential of the circuit in the write operation as in the read operation without applying the intermediate bias voltage VS as shown in FIG. Good. From this, the source switch circuit SS0 can be greatly simplified as in the embodiment of FIG. In other words, the potential of the source line may be the ground potential of the circuit except in the erase operation, so that the high voltage VPP
Is supplied with the output signal of the NAND gate circuit G1 which receives the block selection signal S0 and the erase control signal ERASE, and transmits the ground potential of the circuit.
An output signal of the inverter circuit N0 receiving the erase control signal ERASE is supplied to the gate of the.

In the above structure, during the erase operation, the source line is set to the high impedance state for the memory block which is not erased as described above. If it is desired to set the potential of the source line of the memory block that is not erased in the erase operation to the ground potential of the circuit, for example, the erase control signal ERASE
An AND gate circuit for receiving the inverted signal of the block selection and the output signal of the inverter circuit N0 may be supplied to the gate of the MOSFET Q5 through the OR gate circuit.

FIG. 11 is a flow chart showing an example of the algorithm of the erase mode in the flash memory of this embodiment. In the figure, a series of pre-write operations as indicated by the dotted line in the figure are executed prior to the actual erase operation. That is, the stored information of the memory cell in the memory block before erasing, in other words, the threshold voltage of the storage element varies in height depending on the presence or absence of writing as described above. The above-mentioned pre-write operation is performed by writing to all storage elements prior to the electrical erasing operation, so that the internal automatic erasing according to this embodiment is performed on the unwritten memory cells, that is, the erased memory cells. It is intended to prevent generation of a memory cell having a negative threshold voltage due to the operation.

Generally, in electrical erasing, the threshold voltage when erasing is continued for a long time can be a negative value, unlike the threshold voltage in the thermal equilibrium state. In contrast to the EPROM, when erasing is performed with ultraviolet rays, the threshold value at the time of manufacturing the memory device can be settled down and can be controlled by the manufacturing method. In the above memory cell, when the threshold value becomes negative, the reading is adversely affected. In this pre-write operation, in step (1), address setting is performed in which an address signal for selecting an individual memory cell is generated by the address counter circuit.

In step (2), writing (pre-writing) is performed by generating a writing pulse. After this writing, in step (3), the address counter circuit is incremented (+1),
Perform address increment. Then, in step (4), it is determined whether or not the address is the final address, and the above prewrite is not performed up to the final address (N
In the case of O), the process returns to the writing step (2) and writing is performed. This is repeated until the final address of one memory block. Since the final address is determined after the address increment (3) as described above, the address actually determined is the final address + 1.

When the above-mentioned prewriting is completed, the following erasing operation is executed. In step (5), the address for the erase operation is initialized.
In this embodiment, since erasing is performed in block units, it is absolutely necessary to initialize this address. This address setting is also necessary for the erase verify that will be performed later.

In step (6), an erase pulse for block erase is generated. After that, the verify operation is performed in step (7) according to the address setting. In this verify operation, the operation voltage is switched to a voltage lower than the low voltage VCC, for example, a low voltage such as 3.5 V, and the above-described read operation is performed. In this read operation, the read signal is "0".
If so, it is recognized that the threshold voltage is in the erased state of 3.5 V or less, and therefore the address increment is performed in step (8).

Similar to the above-mentioned pre-write operation, it is judged whether or not it is the final address, and if it is not the final address (N
In (O), the procedure returns to step (7), and the verify operation similar to the above is performed. By repeating this process up to the final address, the erase operation is completed. In this erase operation, since the memory blocks are collectively erased as described above, the number of erases is determined by the memory cell having the highest threshold voltage by the write operation among the memory cells in the block. That is, the memory cell having the highest threshold voltage can be read at the above 3.5V,
That is, the erase pulse in step (6) is performed based on the verify result in step (7) until the threshold voltage is low. By such a controlled erase operation, the threshold voltage of the memory cell can be accurately set to a predetermined voltage without making it negative.

FIG. 12 is a block diagram showing an embodiment of a microcomputer system using the flash memory according to the present invention. In the microcomputer system of this embodiment, a microprocessor (CPU) is mainly used to store a program (ROM, read ROM, etc.).
R used as a main memory device)
AM (random access memory), I / O port I
/ OPORT, the batch erase type EEPR according to the present invention
Liquid crystal display device or CRT (cathode ray tube) as a monitor connected via OM and control circuit CONTROLLER
Address bus ADDRESS, data bus DATA
And a control bus exemplarily shown and transmitting the control signal CONTROL.

In this embodiment, the display device LCD or C is used.
12V power supply RGU required for RT operation is
It is also used as the high voltage VPP of the ROM. Therefore, in this embodiment, the power supply RGU is a microprocessor CPU
Control signal from the terminal V during the read operation.
A function to switch PP to 5V such as VCC is added. Further, in FIG. 13, a microprocessor CPU and E
The connection relationship of each signal focusing on the EPROM is shown.

At the terminal CEB of the flash memory, an address signal indicating the address space assigned to the EEPROM of the system address is supplied to the decoder circuit DEC to generate the chip enable signal CEB. Further, the timing control circuit TC is a microprocessor C
It receives an R / W (read / write) signal, a DSB (data strobe) signal and a WAIT (wait) signal from PU and generates an output enable signal OEB and a write enable signal WEB.

In the microcomputer system of this embodiment, since the flash memory has the automatic erasing function as described above, the microprocessor CPU is
The flash memory is addressed to generate a signal CEB, and a command is generated through signals OEB, WEB and signal CEB and a data bus DATA for designating a mode of the combination of the signals R / W, DSB and WAIT. After this, the flash memory internally enters the automatic erase mode as described above. When the flash memory enters the erase mode, the address terminals, data terminals and all control terminals become free as described above, and are separated from the microprocessor CPU.

Therefore, the microprocessor CPU
Simply indicates the erase mode to the flash memory, and then uses the system bus to perform data processing involving the exchange of information with other memory devices ROM or RAM, or input / output ports. You can This allows you to do this without sacrificing system throughput.
It becomes possible to erase the flash memory in the state where it is placed in the system like the full-function (byte rewritable) EEPROM. Microprocessor C
After instructing the erase mode as described above, the PU designates the data polling mode to the EEPROM at appropriate time intervals, and, for example, the level of the terminal D7 of the data bus becomes low level / high level. A determination is made to determine whether or not the erase operation has ended, and if the erase is completed and there is data to be written to the flash memory, then writing is instructed.

The operational effects obtained from the above embodiment are as follows. That is, (1) Non-volatile memory elements are arranged in a matrix in which non-volatile memory elements that erase accumulated charges in the floating gate by a tunnel current through the tunnel insulating film are arranged in a matrix. In a nonvolatile memory device having a memory array in which a memory element is divided into a plurality of blocks and the above erasure can be performed for each block, writing is performed to a source line of the nonvolatile memory element that is shared for each block. The ground potential of the circuit is given to the selected block from time to time, and the floating gate and source are applied to the non-selected block.
A source switch circuit that provides a predetermined bias voltage that reduces the potential difference between the drains and a predetermined high voltage during erasing is provided. In this configuration, a predetermined bias voltage that reduces the potential difference between the floating gate and the source / drain is applied to the non-selected block during writing, or the word line and the source line are divided for each block. As a result, it is possible to prevent or reduce the generation of an undesired tunnel current due to the write operation in the non-selected memory block.

(2) In one divided memory block, the word line and the source line are configured so that a high voltage is not supplied to the word line in the non-selected memory block at the time of writing. It is possible to obtain an effect that it is possible to prevent the generation of an undesired tunnel current due to the write operation in the block. (3) Flash E for block erasing is performed by setting the upper limit of the bias voltage such that tunnel emission current does not substantially occur in the nonvolatile memory element of the non-selected memory block at the time of writing.
It is possible to obtain the effect that the information holding characteristics of the erased state and the written state in the EPROM can be improved.

(4) The bias voltage is a constant voltage which is substantially independent of the power supply voltage and the write voltage, so that an undesired tunnel current is prevented with high accuracy. The effect of being able to do is obtained. (5) In the memory block to be erased, by performing the write operation to all the non-volatile memory elements in the memory block prior to the erase, the unwritten memory cells become negative by executing the erase operation. It is possible to obtain the effect that it can be prevented from having a threshold voltage of.

(6) A non-volatile memory element for erasing the accumulated charges in the floating gate by a tunnel current through the tunnel insulating film is arranged in a matrix.
For a memory array in which a plurality of non-volatile memory elements each having a control gate coupled to the same word line is divided into a plurality of blocks and the above-mentioned erasing is possible for each block, the non-volatile memory of the one memory block At the time of writing operation of the element, writing is performed by applying a constant bias voltage to the source or drain to which the nonvolatile memory element in the non-selected memory block is coupled so as to reduce the potential difference between the floating gate and the source or drain. By adopting the method described above, a predetermined bias voltage that reduces the potential difference between the floating gate and the source / drain is applied to the non-selected block at the time of writing, or the word line and the source line are provided for each block. Is divided into non-selected memory blocks. There effect that the occurrence of undesired tunneling current due to the write operation can be prevented or reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
The storage element may be a stacked gate structure MOS transistor used in EPROM, or may be a FLOTOX type non-volatile storage element that uses a tunnel phenomenon for the writing operation. The high voltage VPP for writing / erasing is not limited to the one using the high voltage supplied from the outside. That is, if the current flowing during writing / erasing is small, the low voltage VC
It is also possible to use a voltage boosted from C by a known charge pump circuit or the like. Further, the internal boosted power supply and the external high voltage VPP may be used together.

In the flash memory, the configuration of the circuit portion that controls normal writing / reading and the like and the circuit portion that controls the erasing algorithm may be any circuit as long as the above operation sequence is performed. It doesn't matter. The erasing algorithm as described above may be performed by an instruction of an external microprocessor or the like.
In addition to the random logic circuit, the circuit for controlling the erasing algorithm is a programmable logic array (PLA), a microcomputer and software are incorporated, or an asynchronous circuit as in the above embodiment, but a synchronous circuit. I don't care. in this way,
The circuit that realizes the above operation sequence can adopt various embodiments. Flash EEPR
Various embodiments can be adopted as a concrete circuit configuration of the memory array and its peripheral circuits which constitute the OM. Further, the EEPROM or the like may be incorporated in a digital semiconductor integrated circuit device such as a microcomputer or the like.

The present invention can be widely used for a nonvolatile memory device and a writing method in which a selective erasing operation is performed for each block by a tunnel current.

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of non-volatile memory elements, each having a plurality of non-volatile memory elements in which a control gate is coupled to the same word line, are arranged in a matrix in which non-volatile memory elements that erase accumulated charges in a floating gate by a tunnel current through a tunnel insulating film are arranged in a matrix. In a non-volatile memory device having a memory array that is divided into blocks and enabled to erase in each block, the source line of the non-volatile memory element shared in each block is selected at the time of writing. The ground potential of the circuit is applied to the selected block, a predetermined bias voltage that reduces the potential difference between the floating gate and the source and drain is applied to the non-selected block, and a predetermined high voltage is applied during erase. When providing a source switch circuit or writing to one memory block In the non-selected memory block, the word line and the source line are configured so that high voltage is not supplied to the word line, so that the potential difference between the floating gate and the source / drain is small in the non-selected block during writing. Since a predetermined bias voltage is applied or the word line and the source line are divided for each block, it is possible to prevent or reduce the generation of an undesired tunnel current due to a write operation in a non-selected memory block. You can

[Brief description of drawings]

FIG. 1 is an electrical erasing type EEP to which the present invention is applied.
It is a block diagram which shows one Example of ROM.

FIG. 2 is a circuit diagram of a memory array section and main peripheral circuits showing an embodiment of a flash memory to which the present invention is applied.

FIG. 3 is a circuit diagram showing an embodiment of a block selection signal generation circuit.

FIG. 4 is a circuit diagram showing another embodiment of the bias voltage generating circuit.

FIG. 5 is a circuit diagram showing another embodiment of the bias voltage generating circuit.

FIG. 6 is a circuit diagram showing still another embodiment of the bias voltage generating circuit.

FIG. 7 is a circuit diagram of a memory array section and main peripheral circuits showing another embodiment of a flash memory to which the present invention is applied.

FIG. 8 is a circuit diagram of a memory array section and main peripheral circuits showing still another embodiment of a flash memory to which the present invention is applied.

FIG. 9 is a characteristic diagram showing the relationship between the number of rewrites and the threshold voltage in the erased state of the flash memory according to the present invention.

FIG. 10 is a characteristic diagram showing the relationship between the number of times of rewriting and the threshold voltage in a written state of the flash memory according to the present invention.

FIG. 11 is a flowchart showing an example of an erase mode algorithm in the flash memory according to the present invention.

FIG. 12 is a block diagram showing an embodiment of a microcomputer system using a flash memory according to the present invention.

FIG. 13 is a block diagram showing a connection relationship between a microprocessor CPU and a flash memory.

FIG. 14 is a structural cross-sectional view for explaining an example of a conventional memory cell.

FIG. 15 is a characteristic diagram showing the relationship between the number of rewrites and the threshold voltage in the erased state when erasing is performed in block units.

FIG. 16 is a circuit diagram of a main part showing an example of a flash memory designed to perform block-by-block erasure conceived prior to the present invention.

[Explanation of symbols]

ADB ... Address buffer, XDC ... X system decoder, Y
DC ... Y system decoder, MB0-MBn ... Memory block, YG ... Y gate, SA ... Sense amplifier, WA ... Write amplifier, IOB ... Input / output circuit, SS0-SSn ... Source switch circuit, BVG ... Bias voltage generation circuit, C
LG ... Control circuit, LVC0, LVCm ... Level conversion circuit, CPU ... Microprocessor, ROM ... Read only memory, RAM ... Random access memory, I / OPORT ... I / O port, EEPROM (F
LASH) ... Flash non-volatile memory device, RGU ... 1
2V power supply device, LCD ... Liquid crystal display device, CRT ... Cathode ray tube, ADDRESS ... Address bus, DATA ... Data bus, DEC ... Decoder circuit, TC ... Timing control circuit, 3 ... Drain, 4 ... Floating gate, 5 ...
Source, 6 ... Control gate, 7 ... Thin oxide film (tunnel oxide film), 8 ... P-type silicon substrate, 9 ... N-type diffusion layer, 10 ... Low-concentration N-type diffusion layer, 11 ... P-type diffusion layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/792 H01L 29/78 371 (72) Inventor Kazuhiro Komori 5th Street, Kamimizumoto-cho, Kodaira-shi, Tokyo No. 20-1 Incorporated company Hitachi Ltd. Musashi Factory (72) Inventor Hitoshi Kume 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi Ltd.

Claims (9)

[Claims] 1. A non-volatile memory device comprising a plurality of non-volatile memory devices arranged in a matrix for erasing accumulated charges of a floating gate by a tunnel current through a tunnel insulating film, and having a plurality of control gates coupled to the same word line. Is provided in the memory array which is divided into a plurality of blocks to enable the erasing in each block and the source line of the non-volatile memory element shared in each of the blocks, and which is selected at the time of writing. Is applied to the ground potential of the circuit, a non-selected block is applied with a predetermined bias voltage that reduces the potential difference between the floating gate and the source, and the source switch is applied with a predetermined high voltage during erase. A nonvolatile memory device comprising a circuit. 2. The bias voltage is set with a potential such that a tunnel emission current does not substantially occur in a nonvolatile memory element of a non-selected memory block at the time of writing, as an upper limit. Claim 1
Non-volatile storage device. 3. The bias voltage is set to a constant voltage that is substantially independent of the power supply voltage and the write voltage. 2. Non-volatile storage device. 4. A non-volatile memory element, which is arranged in a matrix and has a non-volatile memory element for erasing accumulated charges of a floating gate by a tunnel current through a tunnel insulating film, corresponding to one or a plurality of word lines to which a control gate is coupled. A memory array divided into a plurality of memory blocks each having a source line to which a source of a storage element is commonly connected, and a source line provided for each memory block are provided, and a ground potential of a circuit is given at the time of writing,
A non-volatile memory device comprising: a source switch circuit that applies a predetermined high voltage only to a selected memory block at the time of erasing. 5. The word line is divided into left and right, word line selection circuits are provided corresponding to the left and right, and a data line to which a drain of a nonvolatile memory element is connected and a source line to which a source is connected are defined. The nonvolatile memory device according to claim 4, wherein the nonvolatile memory device is arranged so as to be orthogonal to the word line. 6. The source line is arranged in parallel with the word line in the same direction.
Non-volatile storage device. 7. The memory block that is selectively erased comprises:
The non-volatile memory device according to any one of claims 1, 2, 3, and 4, wherein a write operation is performed on all the non-volatile memory elements in the memory block prior to erasing. .. 8. A non-volatile memory device comprising a plurality of non-volatile memory devices arranged in a matrix for erasing accumulated charges of a floating gate by a tunnel current through a tunnel insulating film, and having a plurality of control gates coupled to the same word line. A memory array that is divided into a plurality of blocks to enable the erasing in each block, and a nonvolatile memory element in a non-selected memory block during a write operation of the nonvolatile memory element of the one memory block. A writing method for a non-volatile memory device, characterized in that a constant bias voltage is applied to the source or drain to which is coupled so as to reduce the potential difference between the floating gate and the source or drain. 9. In the erase operation of the nonvolatile memory element, a write operation is performed on all the nonvolatile memory elements to be erased prior to the erase operation, and a read operation is performed after at least one erase operation. 9. The read level determines whether to continue the erase operation again or stop the erase operation again.
Non-volatile storage device writing method.