JPH05151297A - Logical inspection device - Google Patents

Abstract

PURPOSE:To efficiently and surely execute inspection for preventing the generation of misdetction of an design error in a logical circuit by executing the combination of signal values for controlling the operation of a circuit part at the time of executing logical circuit simulation and checking circuit operation of executing logical is not executed yet based upon a combination which is not set up at the time of the simulation. CONSTITUTION:An overall control signal extracting part 1 analyzes logical description 4 and forms an overall control signal combination list 5 consisting of combinations of signal values controlling the operation of a circuit part. On the other hand, a test pattern 6 is set up in the logical description 4 and simulation is executed to obtain control system signal status value information 7 to be the combinations of status values to which control system signals are to be set up. An uninspected operation detecting part 3 excludes a combination coincident with the information 7 from the list 5, treats operation to be executed by the residual combinations as uninspected operation and outputs an uninspected operation indicating list 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device for a logic simulation model.

[0002]

2. Description of the Related Art A conventional logic verification apparatus performs a simulation on a designed logic circuit and changes the state value of each signal after the simulation from 0 value to 1 value or from 1 value to 0 value. Focusing on changes in state values, such as changes, and determining from the changes in state values whether or not a certain circuit part has been verified, and identifying unverified circuit parts (unverified parts and their logical descriptions). In order to prevent the logic circuit design error from being overlooked, the verification was performed.

[0003]

In the above-described conventional logic verification device, in detecting the unverified portion of the logic circuit, the verification is performed by paying attention only to the change in the state value of each signal after the simulation. Actually, even if all the operations set for a certain circuit portion have not been verified, the state value of a certain signal in that circuit portion is simply 0 or 1
When it is recognized that both values are taken, it is considered that the verification for the circuit part is completed, and the unverified part on the logic circuit is overlooked, so that the design error of the logic circuit cannot be detected. Was invited.

[0004]

SUMMARY OF THE INVENTION The present invention is based on a logic description expressing a logic simulation model created at the time of logic design of a circuit, and a value that all control system signals that control the circuit operation assumed on the logic description can take. And all control system signal value extraction means for creating a list of all control system signal value combinations, and simulation means for simulating the operation of the logic circuit based on the logic description and the test pattern expressing the logic simulation model. , A combination of values taken by each control system signal is excluded based on the total control system signal value combination list created by the total control system signal extraction means and the control system signal state value information created by the simulation means. By doing so, the combination of the values of the control system signals when selecting the circuit operation that has not been verified during simulation has not been verified. And a non-verification operation detection means for outputting as a work posting list.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, all control system signal extraction means 1
Recognizes all control system signals involved in switching all the operations set for a certain circuit portion based on the logic description 4 expressing the logic simulation model created at the time of logic design of the circuit, A combination of all control system signal values when selecting an operation is created as a total control system signal value combination list 5.

The simulation means 2 sets a test pattern 6 for a logic description 4 expressing a logic simulation model and performs simulation, and a state in which all control system signals involved in switching the operation of the circuit portion are taken. A value is created as the control system signal state value information 7.

Then, the unverified operation detecting means 3 collates the control system signal value combination list 5 with the control system signal state value information 7 and sets from all combinations of the values that all control system signals can take. From the combination of the values that each control system signal can take as a result of the simulation in the test pattern, select the one that matches the combination of the values that each control system signal takes as the result of the simulation in the set test pattern. As an unverified operation bulletin list 8 that excludes and finally leaves the combination of the values of the control system signals that is posted as the combination of the values of the control system signals when selecting the operation of the circuit portion that has not been verified during the simulation. Output.

Next, the operation of this embodiment will be described.

FIG. 2 is a flow chart showing the flow of processing in this embodiment. In FIG. 2, reference numeral 4 is a logic description representing a logic simulation model created at the time of logic design of the circuit. In this logic description 4, “IN: A, B,
D, E "are four input signals to the circuit: A, B, D, E
“C = D ANDE” indicates that the value of the signal C is the result of the AND operation of the signal D and the signal E, and “P = (A, B, C / 1,1,
X: 1) ”, the value that the signal P takes is controlled by three signals, that is, the signal A, the signal B, and the signal C.
It indicates that the operation of taking the state value 1 is selected when the value, the signal B takes a single value, and the signal C takes an arbitrary value. Hereinafter, it will be shown that this operation is sequentially followed.

First, the all control system signal extraction unit uses the logic description 4
By analyzing all the control system signals involved in the switching of all the operations set for the circuit, all the control system signals showing the combinations of the values of all the control system signals when selecting each operation are analyzed. A control system signal value combination list 5 is created.

That is, "P = (A,
B, C / 1, 1, X: 1) ", the control signals for the signal P are signal A, signal B, and signal C, each of which is 1
In the case of taking a value, 1 value, or an arbitrary value, it is analyzed that the signal P takes the state value 1, and “(A, B, C) = (1 , 1, X) ”is created.

Similarly, "(A, B,
C / 1,0, X: 0) "," (A, B, C / 0,1,
X: 0) "," (A, B, C / 0,0,0: 1) ",
From “(A, B, C / 0, 0, 1: 1)”, “(1, 0,
X) ”,“ (0,1, X) ”,“ (0,0,0) ”,
Create "(0,0,1)".

Further, the simulation section 2 sets a test pattern 6 for the logic description 4 expressing the logic simulation model, performs simulation, and as a result of the simulation, is involved in switching the operation of the circuit part. The state values of all control system signals are created as control system signal state value information 7.

That is, the input signals of the circuit represented by the logical description 4 are the signal A, the signal B, the signal D, and the signal E, the signal A has one value, the signal B has one value, and the signal D has one value.
“IN: A, B, D, E = (1, 1, 1,
1) ”, the test pattern 6 is set for the logic description 4 and a simulation is performed. Among control signals involved in switching the operation of the circuit part, a signal whose value is determined only after the simulation is performed. The value of C is obtained, that is, "C = D AND E" in the logical description 4.
By setting 1 value in D and 1 value in E and performing an AND operation to obtain 1 value as the value of the signal C, it is possible to participate in the switching of the operation of the circuit part shown in the logic description 4. The control signals A, B, and C that are set may have a value of 1 for the signal A, a value of 1 for the signal B, and a value of 1 for the signal C when a simulation is performed by setting the first test pattern. Understand, "(A, B, in the control system signal state value information 7
C) = (1,1,1) ″ is obtained.

In the same manner, all test patterns are sequentially set and a simulation is performed, and "(1,0,1)", "(0,1,1)", "(in the control system signal state value information 7 are set. 0,
0,0) "and" (0,0,0) "are obtained.

The unverified operation detecting section 3 determines the state value of each control system signal in the control system signal state value information 7 from the combination of the values of all the control system signals in the total control system signal value combination list 5. Those that match the combinations are excluded, and the finally remaining combinations of the values of all control system signals are output as the unverified operation bulletin list 8.

It can be seen that the operation of the circuit portion selected by the combination of all the control system signal values included in the unverified operation list 8 has not been verified. That is, “(A, B, C) =” in the control system signal state value information 7
Since (1,1,1) ”is included in“ (A, B, C) = (1,1, X) ”in the total control system signal value combination list 5, the signal A is displayed on the logic circuit. Is 1 and signal B is 1
It can be seen that the operation of the circuit portion selected when the value and the signal C take one value has been verified.

Further, "(1,0,1)" and "(0,1,1)" in the control system signal state value information 7 are "(1,0,1)" in the total control system signal value combination list 5, respectively. 0,
“(X,),” (0,1, X) ”, and“ (0,0,0) ”in the control system signal state value 7 is“ (0,0,0) ”in the total control system control value combination list 5. 0,0) ”, the control system signal state value information 7 indicates the state value of each control signal among the combinations of the values of all control system signals in the control system signal value combination list 5. A combination that does not match the combination is detected to be "(0,0,1)".

Therefore, the unverified operation detector 3 does not verify the operation of the circuit portion selected by the signal A having a 0 value, the signal B having a 0 value, and the signal C having a 1 value. Therefore, “(A, B, C) = (0, 0, 1)” representing the combination of the control system signals A, B, C is output as the unverified operation list 8.

[0021]

As described above, according to the present invention, when the verification of the logic circuit is performed, the judgment is made only from the change of the state value on the logic circuit. Since the unverified portion can be surely grasped, there is an effect that the verification for preventing the omission of the detection of the design error of the logic circuit can be performed efficiently and surely.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of processing in this embodiment.

[Explanation of symbols]

 1 All control system signal extraction unit 2 Simulation unit 3 Unverified operation detection unit 4 Logic description 5 All control system signal value combination list 6 Test pattern 7 Control system signal state value information 8 Unverified operation bulletin list

Claims (1)

[Claims] 1. All controls representing all combinations of possible values of all control system signals for controlling circuit operations assumed on the basis of a logic description expressing a logic simulation model created at the time of logic design of a circuit. All control system signal extraction means for creating a system signal value combination list, simulation means for simulating the operation of a logic circuit based on a logic description and a test pattern expressing the logic simulation model, and all control system signal extraction means It is verified at the time of simulation by excluding a combination of values taken by each control system signal based on the control system signal value combination list created by the above and the control system signal state value information created by the simulation means. Outputs the combination of control system signal values when selecting a circuit operation that has not been performed as an unverified operation bulletin list. And a non-verified operation detecting means.