JPH05175430A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize a semiconductor integrated circuit having a chip identifying circuit, which can identify a semiconductor chip simply and accurately. CONSTITUTION:A TEG chip 1a as a semiconductor integrated circuit is constituted of 9 subchips 2. The subchip 2 includes a P-N junction diode line 4, whose connecting number is set in response to the kinds A, B and C of the chips, respectively. One end of each P-N junction diode line is connected to a recognizing pad 5, which is connected to a package pin in assembly. The other end is connected to the highest or lowest potential based on the type of the P-N junction. The number of the diodes is set with an Al wiring 12. In this way, the semiconductor chip can be identified simply and accurately by making a constant current flow through the P-N junction diode and measuring the voltage in the forward direction at this time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a semiconductor integrated circuit having a chip identification circuit for identifying the type of a semiconductor chip, and in particular, a plurality of types of semiconductors having various elements, circuits, etc. formed on the same wafer. The present invention relates to a semiconductor integrated circuit capable of forming chips, assembling these semiconductor chips into a package of the same type, and then identifying and selecting them.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as ICs)
In the development and design of the product, prior to product design, the electrical characteristics of transistors and resistors formed on the IC and the characteristics of standard circuits are measured. We sometimes design and prototype test chips on a large scale, and these chips are usually used for TEG (Te
It is called a st Element Group chip.

This TEG chip is often divided into a plurality of types of sub chips, one sub chip is a single element, and the other sub chip is a circuit. The positions of the bonding pads are often the same. In such a configuration, when assembling these TEG chips into a package, it is possible to select and assemble only desired sub chips, but once all the sub chips are assembled as the same chip, some method is used. It is easier to sort with.

Therefore, conventionally, a resistance element is connected between a pad at the same position of each sub chip and a pad connected to the substrate of the sub chip, and the resistance value of this resistance element is set for each sub chip. In other words, after assembly, a method of identifying and selecting the type of subchip by measuring this resistance value from the outside is performed.

For example, when a TEG chip 1 having a 3 × 3 nine-sided sub-chip structure as shown in FIG. 6 is designed, a recognition pad 5 is provided at substantially the same position, and the recognition pad 5 has a sub-chip (A ~I) connect one end of the resistive element (R _a ~R _I) 16 of 1KΩ~9KΩ every 2, element 1
The other terminal of 6 is connected to the substrate potential pad 17.

The TEG chip 1 having such a structure is
It is divided into sub chips 2 and assembled into the same type of package. In this case, sorting by sub-chip 2,
It is not necessary to assemble, and all the chips are the same chip.

After the assembly is completed, as shown in FIGS. 7A and 7B, a resistance meter 21 is connected between the recognition pin 19 and the substrate potential pin 20 of the package 18 to measure the resistance value between the pins. Thus, the type of the sub chip 2 can be estimated. For example, in FIG. 7A, the resistance value of the ohmmeter 21 becomes 5 KΩ, which is the internal sub-chip E.
In (b), since it is 7 KΩ, it can be seen that it is a sub chip G.

Therefore, if this method is performed by a screening tester or the like, sub chips can be sorted at high speed. It is also possible to branch the conditions of various test items to be performed next from the result of the recognition resistance measurement, and it is possible to select TEG chips in which various element constants change with almost the same circuit configuration. Is.

[0009]

However, in the above-mentioned conventional method of recognizing the semiconductor chip in the semiconductor integrated circuit, the absolute value of the resistance is measured, so that the resistance value can be set in advance in consideration of the variation in the resistance value. is necessary. That is, for example, in order to reduce the element area of this recognition resistor,
Assuming that the minimum resistance value is 100Ω and the resistance value is increased in 100Ω steps, the resistance value is 100Ω, 20
0Ω ...

Assuming that there are 10 types of sub chips, the maximum and previous recognition resistance values are 90.
It becomes 0Ω and 1KΩ. However, if the variation in absolute accuracy of the resistance is ± 20%, these resistance values are 7
20Ω to 900Ω to 1080Ω and 800Ω to 100
It will be 0Ω to 1200Ω, and the dispersion range of these two resistances will overlap, resulting in 950Ω in a certain lot.
When the resistance value of is measured, the two sub chips cannot be distinguished.

As described above, in consideration of the variation in absolute accuracy of resistance, the basic minimum resistance value and step value must be increased as the number of types of sub-chips increases, and the area of the recognition resistance element increases, resulting in manufacturing. There was a drawback that it became difficult.

[0012] In essence, in this method, it is necessary to set the program for determining the resistance value to be measured so that the variation range of the absolute value can be determined.
Depending on the type of recognition resistor and the type of sub chip,
There was a drawback that the screening program had to be changed.

It is an object of the present invention to provide a semiconductor integrated circuit having a chip identification circuit which can easily identify a sub chip without increasing the chip area by eliminating the above-mentioned drawbacks.

[0014]

According to the present invention, in a semiconductor integrated circuit having a chip identification circuit for identifying the type of a semiconductor chip, the chip identification circuit has a PN junction in which a plurality of PN junction diodes are connected in series. One of the PN junction diode arrays is connected to a predetermined power supply terminal, and the other terminal is connected to a bonding pad connected to a package side pin.

[0015]

In the PN junction diode array, the number of diodes is set for each sub-chip by electrically short-circuiting unnecessary diodes, and a constant current for measurement is passed through the PN junction diode array to measure the voltage. The magnitude of the voltage measured at this time is given by the number of times the forward voltage of the PN junction diode, and each sub-chip can be identified.

By the way, the forward current-voltage characteristic of the PN junction diode depends only on the process and the junction, and although it has a temperature characteristic, the variation is very small, and it is possible to accurately identify it by the number.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a layout diagram showing a main part of a first embodiment of the present invention, showing a case of a TEG chip.

The TEG chip 1a of the first embodiment is 3 ×
3 sub-chips 2 and 3 types A,
It is classified into B and C. And each sub chip 2
As a chip identifying circuit, which is a feature of the present invention, one end is connected to the substrate potential, and the other end set by the number of each diode is connected to a package side pin by an Al (aluminum) wiring 12. PN connected to the recognition pad 5 as a bonding pad
It includes a junction diode array 4. In FIG. 1, 3 is a pad, and the pad arrangement including the recognition pad 5 is
It is the same in each sub chip 2.

Next, how the TEG chip 1a shown in FIG. 1 is obtained will be described in detail.

FIG. 2 shows the TEG chip 1a of FIG.
FIG. 9 is a layout diagram showing a state before setting a PN junction diode array.

The TEG chip 1a of the first embodiment is manufactured by a CMOS process using a P-type substrate and is 3 × 3.
9 sub chips (A to I) 2 each having the same elements such as transistors and resistors formed on each sub chip 2, and the pads 3 are arranged at the same positions. Then, in the lower right corner of each sub chip 2, a PN junction diode array 4, which is a feature of the present invention, is formed.

The structure of the PN junction diode array 4 is shown in FIG.
As shown in (a) (plan view) and (b) (AA ′ cross-sectional view) and FIG. 4 (equivalent circuit), islands in the region of the isolated N well 7 are provided on the P-type substrate 6. Therefore, the high-concentration N-type layer 8 and the high-concentration P-type layer 9 exist in the region of the N well 7, and the PN junction diode 10 is formed. In the first embodiment, eight PN junction diode rows are connected in series by the Al wiring 12 on the oxide film 13 via the contact 11 to form the electrodes 14-1 to 14-8.

Further, one end of the PN junction diode array 4 is P
The high-concentration P-type layer 9 provided on the mold substrate 6 connects to the substrate potential.

Using such a TEG chip 1a, 3
When configuring a type of circuit (for example, circuits A, B, and C), as illustrated in FIG. 1, the recognition pad 5 of the sub chip 2 that configures the circuit A includes the electrode 14-1 (in the PN junction diode array 4). (See FIG. 4) is connected using an Al wiring 12. Similarly, the circuit B is connected to the electrode 14-4, and the circuit C is connected to the electrode 14-8.

The TEG chips 1 having such a structure are assembled in the same shape package as all the same chips. At this time, the position of the pin connected to the recognition pad 5 and the position of the pin connected to the substrate potential are exactly the same.

Next, in order to select the assembled ICs,
A constant current source is connected between the connected pin of the recognition pad 5 and the pin connected to the substrate potential, for example, 100 μA
A forward current of about a certain value is applied, and the pin-to-pin voltage at that time is measured.

This measured voltage is about 0.7 V when the sub chip 2 is the circuit A, 2.8 V when the circuit B is the circuit B, and 5.6 V when the circuit C is the circuit C.
The identification of B and C is simple and accurate.

FIG. 5 is a chip plan view showing a PN junction diode array of a second embodiment of the present invention.

The PN junction diode array of the second embodiment is
As shown in FIG. 5, each electrode 14- of the PN junction diode 10
Wafer check pads 15-1 to 1 on 1 to 14-8
5-7 are provided.

This PN junction diode array is formed on a part of the IC, and the electrode 14-8 is connected to a certain bonding pad defined as a recognition pad.

In such a structure, when the characteristics, performance, etc. of the IC in the wafer state are evaluated, the chips are classified into several ranks, and the above-mentioned wafer check pad 15-1 is divided accordingly. A relatively large current is applied in a pulse form to a substrate potential from a part of 15-15, and the junction of the PN junction diode through which the current passes is destroyed,
The PN junction is short-circuited. This electrically reduces the number of PN junction diode strings connected in series. As a result, there are various numbers of PN junction diode rows connected between the recognition pad and the substrate potential pad in the same wafer, but after the assembly is completed, the potential difference between the recognition pad and the substrate potential pad is By measuring, ICs can be sorted according to the rank of the ICs sorted by the wafer check.

Although the case of the P type substrate has been described in the above embodiments, the present invention can be similarly applied to the case of the N type substrate. However, in this case, one end of the PN junction diode array is connected to the power supply potential (highest potential) instead of the substrate potential (lowest potential).

[0034]

As described above, according to the present invention, since the element connected to the recognition pad is a PN junction diode having a stable characteristic with little variation according to the type of chip, the semiconductor chip can be easily and accurately mounted. It has a distinguishing effect.

Further, since the PN junction diode can be formed in a very small area, the effect that the identification circuit area can be made small can be obtained. Furthermore, as described in the second embodiment, the PN junction diode can be obtained.
Since it is possible to selectively destroy the junction diode on the wafer after the diffusion is completed, it is possible to obtain the effect that the junction diode can be used for ranking the ICs in the wafer after the chip characteristic evaluation.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a layout diagram showing a state before setting the PN junction diode array in FIG.

FIG. 3 is a plan view showing the PN junction diode array and a sectional view taken along the line AA ′.

FIG. 4 is an equivalent circuit diagram of the PN junction diode array.

FIG. 5 is a plan view showing a PN junction diode array according to a second embodiment of the present invention.

FIG. 6 is a layout diagram showing a main part of a conventional example.

FIG. 7 is an explanatory diagram showing a procedure for identifying the semiconductor chip.

[Explanation of symbols]

 1, 1a TEG chip 2 subchip 3 pad 4 PN junction diode row 5 recognition pad 6 P-type substrate 7 N well 8 high-concentration N-type layer 9 high-concentration P-type layer 10 PN junction diode 11 contact 12 Al wiring 13 oxide film 14- 1-14-8 Electrodes 15-1 to 15-7 Wafer Check Pad 16 Resistance Element 17 Substrate Potential Pad 18 Package 19 Recognition Pin 20 Substrate Potential Pin 21 Resistance Meter

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a chip identification circuit for identifying the type of a semiconductor chip, wherein the chip identification circuit includes a PN junction diode row in which a plurality of PN junction diodes are connected in series, A semiconductor integrated circuit, wherein one end of the diode array is connected to a predetermined power supply terminal, and the other terminal is connected to a bonding pad connected to a package side pin.