JPH05176349A - Video transmission system - Google Patents

Abstract

(57) [Abstract] [Purpose] Prevents deterioration of image quality due to addition or deletion of frame images that occur due to the asynchronization of the clock on the transmitting side and the clock on the receiving side in a method of digitizing and transmitting a television signal on a high-speed data transmission line. To do. [Structure] Image data is transmitted from the transmitting side through the data channel and frame pulses are transmitted through the control channel, and the phase difference between the received frame pulse and the frame pulse of the receiving side synchronizing signal generator is monitored in the window and always pulled back within the window. By using the frequency tracking circuit that works in this way as the reception side clock, the transmission side A / D conversion clock and the reception side read clock are synchronized on average, and addition or deletion of frames is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a reading circuit on the receiving side when transmitting a composite color video signal through a high speed data transmission line such as an optical fiber.

[0002]

2. Description of the Related Art In a large-capacity data transmission system (for example, a LAN system) using an optical fiber or the like, not only digital data used by a computer but also video signals and audio signals are digitized, and further control signals are time-division multiplexed. By transmitting, it is possible to transmit video signals of a plurality of channels in almost real time. FIG. 3 shows an example of the most basic LAN system for video signal transmission, and shows a case where the transmitting side and the receiving side each have one system. This system transmits all composite color video signals including video signals, composite sync signals, and color burst signals. Although the data transmission capacity is greater than when sending only video signals without sync signals, D After the A / A conversion, almost no post-processing is required to directly obtain a composite color video signal, and since a color burst signal is added, faithful color reproduction is possible.

This outline will be described with reference to FIG. The high-speed data transmission line 1 is connected to a transmission terminal 2, a reception terminal 3, and a monitoring controller 4 for monitoring the transmission line 1 and controlling the synchronization. As an example, an NTSC television color camera 5 is connected to the transmitting terminal 2, and a color monitor 6 is connected to the receiving terminal 3. NTS output from color camera 5
Although not shown in the figure, the C television signal a is added to the transmission terminal 2, and image data, audio data, and control data are time-division multiplexed and output to the transmission line 1. On the other hand, the receiving terminal 3 takes in only a desired video signal from a series of data which has been time-division multiplexed, stores it in a built-in buffer memory, restores it to an NTSC television signal, and outputs it to the color monitor 6. The supervisory controller 4 has a role of not only monitoring the failure of the transmission line 1 but also preventing data collision during transmission / reception, and generally outputs the network synchronization control signal b to the transmission line 1 at a constant cycle. It controls the use of the transmission path of the terminal.

Next, details of the transmitting terminal 2 and the receiving terminal 3 will be described with reference to FIGS. FIG. 4 shows an example of the transmission terminal 2. The NTSC television signal a input to the terminal 201 is added to the A / D converter 202 and the write clock generator 203. Write clock generator 20
In the case of No. 3, 14. Synchronized with the NTSC television signal a.
A clock of 3 MHz (4 fsc ∴ fsc: color subcarrier frequency) is generated, and the A / D converter 202 and the data buffer 2 are generated.
Supply to 04. The A / D converter 202 samples the NTSC television signal a at 14.3 MHz, and
The data buffer 204 encodes each sampled value into 8 bits.
Supply to. The purpose of the data buffer 204 is to convert the speed of the NTSC signal clock and the master clock of the transmission line 1. As the configuration of the data buffer 204, for example, a buffer memory of two systems is used, and the A / D converter 20 is used.
It suffices to have a function of continuously writing the output data of No. 2 alternately and reading from the buffer memory in which writing has been completed at high speed (time shorter than writing) according to the clock of the transmission line 1. The control of reading is performed by the controller 205. The output of the data buffer 204 is supplied to the transmission line 1 via the interface circuit 206.

FIG. 5 shows an example of the receiving terminal 3.
The desired composite data transmitted through the transmission line 1 is fetched and supplied to the controller 302 and the frame memory 303 via the interface circuit 301, and the desired image data position of the desired image data is detected by the controller 302. , Is written in the frame memory 303. The image data is read from the frame memory 303 based on the sync signal generator 304, and this image data is returned to the composite color video signal by the D / A converter 306 via the chroma inversion circuit 305 and output terminal 307. Is output from.

Here, the reason why the chroma inverting circuit 305 is necessary will be described. Generally, in a large-capacity data transmission system, the clock of the transmission side terminal (clock frequency for A / D conversion in video signal transmission) and the clock of reception side terminal (clock frequency for memory reading or D / A conversion) are asynchronous. Many. In such a case, since the average writing speed written in the frame memory 303 and the average reading speed at the time of reading are different, the following problem of overtaking and overtaking of an image occurs. For example, when the writing speed is slower than the reading speed, the reading side overtakes the writing side, and therefore the image once read must be read again (adding one frame) in order to prevent the overtaking. Conversely, when the writing speed is faster than the reading speed,
Since the reading side is overtaken by the writing side, 1
The frame must be skipped (one frame deleted) and read. In either case, discontinuous movement occurs on the screen, and the image quality is significantly impaired. Furthermore, since the phase of the color subcarrier is inverted one frame before and after one frame due to the nature of the signal in the NTSC television signal, the same frame is divided into two.
When reading out twice or deleting one frame, the continuity of the color subcarrier is lost and a color inversion phenomenon occurs on the color monitor, which causes deterioration of image quality. To prevent this, a chroma inversion circuit is provided. ing.

Generally, in order to solve these problems,
It is sufficient to distribute the synchronization signal from the transmitting terminal in a separate system and use the PLL loop in the receiving terminal to synchronize the clock with the transmitting side, but consider that a plurality of terminals connected to the transmission path communicate with each other. Becomes complicated. In particular, when a periodic reference pulse is transmitted together with image data by sharing a transmission line and the PLL is to be operated on the receiving side, data for several channels is multiplexed on the transmission line, and a certain transmission Even if an attempt is made to instantly transmit the reference pulse from the terminal to the receiving terminal, data transmission cannot be performed unless the right to use the transmission path comes around. Furthermore, when the master clock of the transmission line and the video signal are asynchronous, data transmission is performed with a time-axis fluctuation (the cycle changes in length within a certain range). Therefore, the receiving terminal cannot directly use the transmitted reference pulse for the PLL.

In addition, the method of distributing only the synchronizing signal separately from the transmission line has a problem in terms of cost, and also results in a reversal of multiplexing, which affects the reliability of the system. As another method, the master clock of the transmission line is set to NTSC.
It is also possible to select a multiple of the color subcarrier of the signal, divide the master clock at the transmitting terminal and the receiving terminal, and use it as the clock for the A / D and D / A converters. Considering that (for example, PAL signal) is transmitted and the transmission line is also used for general data communication, it is not common to select the master clock of the transmission line as an integer multiple of the color subcarrier of the NTSC signal.

Further, if the deletion / addition of frames is performed in color frame units (4 field units), discontinuity of color subcarriers can be prevented, but discontinuous movement on the screen becomes more noticeable. Further, when the chroma inverting circuit 305 as described above is provided to maintain the continuity of the color subcarrier signal, complete luminance / chromaticity separation is impossible, which causes deterioration of image quality. In addition, when an image is deleted / added, a slight timing discomfort occurs between the audio and the video. The above is one-to-one between the sending terminal and the receiving terminal
Although the case has been described, it goes without saying that a more complicated problem occurs in a system that selects and uses video signals of a plurality of transmission terminals.

[0010]

In the above-mentioned prior art,
Not only is it complicated to synchronize the clocks of the sender and the receiver, but it is also possible to delete / remove images if synchronization is ignored.
Problems such as unnatural movement and timing problems with audio signals accompanying addition, and the need for a chroma inversion circuit to maintain the continuity of the color subcarriers cause problems in terms of image quality and circuit scale. is there. The present invention eliminates these drawbacks, and in a video signal transmission system using a high-speed data transmission line, by controlling the clock generator on the receiving side and synchronizing with the transmitting side with a relatively easy circuit configuration. The purpose is to reduce additional circuits such as a chroma inversion circuit.

[0011]

In order to achieve the above object, the present invention transmits image data from a transmitting side to a data channel and a frame pulse of a video signal via a control channel, and receives the frame pulse and the receiving side. The phase difference of the frame pulse of the synchronization signal generator is monitored in a window of a predetermined width, and the output of the detector that determines to which side the received frame pulse deviates from both ends of the window controls the oscillation frequency of the receiving clock, A configuration in which the transmitting side A / D conversion clock and the receiving side read clock are averagely synchronized by reading the image data from the field or frame memory using the clock obtained by the frequency tracking circuit that works so as to pull back into the window. It is what When the read clock is modulated in this manner, the cycle of the video signal slightly changes in a strict sense. However, since the sync monitor range of a color monitor is wide enough, the influence on the display screen can be ignored by selecting a large time constant for changing the cycle of the video signal.

[0012]

As a result, since the average read speed from the frame memory matches that on the write side, it is possible to eliminate the factors that cause unnatural movement, eliminate the need for complicated circuits such as the chroma inversion circuit, and add video and audio. It is possible to provide a system that can minimize the influence on

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. A waveform timing chart of the main part is shown in FIG. It should be noted that the same blocks in the same blocks as those described above and having the same basic operation are denoted by the same reference numerals and the description thereof will be omitted. A portion surrounded by a broken line in FIG. 4 shows a portion where the frame pulse of the video signal is multiplexed with the control channel of the transmission signal of the transmission line 1 in the transmission terminal. The NTSC television signal a input to the terminal 201 is applied to the frame pulse separation circuit 207 and the frame pulse is separated. The separated frame pulse c is applied to the controller 205. The controller 205 receives the network synchronization control signal b periodically output from the supervisory controller 4 described with reference to FIG. 3, and the separated frame pulse c receives the network synchronization control signal b.
And the phase relationship between them is measured, and the phase information is sent to the transmission line 1 as follows.

In addition to the network synchronization control signal b, the transmission line 1 has a packet as a unit for sending some data together. Usually, several tens to several hundreds of packets are collected after the network synchronization control signal b. Have been transmitted. Therefore, the phase relationship between the frame pulse c and the network synchronization control signal b is, for example, the nth frame pulse c is the 10th packet of the ith network synchronization control signal b and the n + 1th frame pulse c is the jth packet. When the phase matches with the 105th packet of the network synchronization control signal b, ..., The information of what number of this frame pulse c matches with which packet of the number of the network synchronization control signal b. , Output to the corresponding control channel of the packet transmitting the image data. Of course, the image data and the control channel data are finally time-division-multiplexed and output to the transmission path 1. Therefore, strictly speaking, the sending side does not send them at a fixed cycle, and a maximum of 1 packet (several microseconds) A time-axis fluctuation error of occurs.

Next, an embodiment of the receiving side terminal will be described with reference to FIG. The main circuit of the reception side terminal is a VCO (voltage controlled oscillator) 316, which changes the control voltage to 0V and a positive potential with a large time constant according to the phase difference between the reception frame pulse c and the read frame pulse g, and performs A / D conversion. It is a method to follow the clock cycle of. The control voltage is set to be slightly higher than 4 fsc when it is 0 V, and the oscillation frequency is designed to decrease when a positive voltage is applied.

The aforementioned composite data sent through the transmission line 1 is added to the frame memory 303 and the controller 302 via the interface circuit 301. The controller 302 analyzes the above-mentioned control channel data (phase information) and detects a desired image data position and frame pulse c. A writing control signal d indicating a target image data period and a writing high speed clock e are applied to the memory control circuit 308 to control the frame memory 303.
Further, the detected frame pulse c is delayed by the 4-line delay circuit 309, and the narrow pulse f as shown in FIG.
Shaped into two input NAND gates 310, 311 and 3
It is added to one of twelve.

On the other hand, the read frame pulse g generated by the synchronizing signal generator 304 is used in addition to the memory control circuit 308.
The reset inhibit pulse generation circuit 313, the leading edge matching determination pulse generating circuit 314, and the trailing edge matching determination pulse generating circuit 315 are added to the reset inhibit pulse h, the leading edge matching determination pulse j, and the trailing edge matching, respectively, as shown in FIG. Generate a pulse k. And
The phase relationship with the pulse f is determined. Now, suppose that the connection immediately after connecting to a new transmission terminal channel is considered, the read frame pulse g generated by the synchronization signal generator 304
And the phase of the transmitted frame pulse c is different. For example, if the 4H delay pulse f of this frame pulse c has the phase shown by the broken line of f in FIG. 2, it is in the high level period of the reset inhibit pulse h. The frame reset pulse 1 is output to the output of the 2-input NAND gate 310 as shown by the broken line, and the synchronization signal generator 304
Is reset, and the relationship between the pulse f and the reset inhibit pulse h is forcibly changed to the phase relationship shown by the solid line in FIG. 2 from the next frame.

When the pulse f and the read frame pulse g have substantially the same phase as shown by the solid line in FIG. 2, the reset pulse 1 is not generated and the phase is stabilized by the disturbance of one frame after channel switching. However, as it is, VC
Since the oscillation frequency of O316 is not synchronized with the clock at the time of A / D conversion, for example, when the oscillation frequency of the VCO 316 is lower than the clock at the time of A / D conversion, the cycle becomes longer. , The reset inhibit pulse h moves to the right, and finally, the high level portion of the front edge coincidence determination pulse j coincides, and the reset pulse m resets the RS FF (reset set flip flop) 317. Added to the terminal. As a result, the output of the RS FF 317 becomes approximately 0V, and the oscillation frequency of the VCO 316 is increased as initially set by being added to the VCO 316 through the resistor R and the capacitor C for the time constant. The diodes D1 and D2 inserted at both ends of the capacitor C serve as a limiter for the control voltage.

On the other hand, as the oscillation frequency becomes higher, the reset inhibit pulse h moves to the left this time, and finally the trailing edge coincidence determination pulse k.
Corresponding to the high level part of the
(Reset Set Flip-Flop) 314 applied to the set terminal. As a result, the output of the RS FF 317 becomes logical high and the oscillation frequency of the VCO 316 becomes low. By repeating the above operation, the clock on the reading side follows the clock at the time of A / D conversion on average.
The clock output p of the VCO 316 is the synchronization signal generator 304, the memory control circuit 308, the frame memory 30.
3, connected to the D / A converter 306.

In this way, the read frame pulse g
2 reciprocates in the range indicated by X in FIG. 2, and the frame pulse cycle of the incoming video signal is averaged, and the phenomenon of overtaking and overtaking of the read video signal can be prevented. To widen the range of X, the width of the reset inhibit pulse h is widened, and the relationship between the leading edge coincidence determination pulse j and the trailing edge coincidence pulse k is changed to the rising and falling edges of the reset inhibit pulse h as shown in FIG. It can be easily realized by combining them.

[0021]

According to the present invention, a pulse having a frame rate synchronized with an input video signal is used, and the receiving side is controlled so that the average reading speed of the frame memory is matched with the transmitting speed of the transmitting side. It is possible to avoid the occurrence of deletion / insertion, eliminate the need for a complicated chroma inversion circuit, and also minimize the phase shift between video and audio, making it a high-quality video transmission system. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a timing chart of the main part of the present invention.

FIG. 3 is a block diagram showing an example of a basic video signal transmission system.

FIG. 4 is a block diagram showing an example of a transmission terminal.

FIG. 5 is a block diagram showing an example of a receiving terminal.

[Explanation of symbols]

1: high-speed data transmission path, 2: transmitting terminal, 3: receiving terminal,
4: Monitoring controller, 202: A / D converter, 203: Write clock generator, 205: Controller, 206: Interface circuit, 207: Frame pulse separation circuit, 301: Interface circuit, 302: Controller, 303: Frame memory , 304: synchronization signal generator, 308: memory control circuit, 309: 4-line delay circuit, 313: inhibit pulse generation circuit, 314: front edge coincidence determination pulse generation circuit, 315: rear edge coincidence determination pulse generation circuit, 316: VCO (voltage controlled oscillator), 317: RS FF (reset set flip-flop).

Claims (2)

[Claims] 1. A transmission system in which a composite video signal is digitized and time-divisionally transmitted, and a receiving side uses a field or frame memory to restore the composite video signal.
The image data is transmitted from the transmitting side to the data channel and the frame pulse is transmitted via the control channel, and the phase difference between the received frame pulse and the frame pulse of the receiving side synchronizing signal generator is monitored in a window of a predetermined width, and the received frame pulse is received. A clock obtained by a frequency tracking circuit that controls the transmission frequency of the receiving clock with the output of the detector that determines to which side from both ends of the window, and pulls the received frame pulse back into the window. A video transmission method characterized in that the A / D conversion clock on the transmission side and the read clock on the reception side are averaged in synchronization by reading the image data from the field or the frame memory using. 2. When the transmission-side frame pulse is out of the window, the reset-side pulse generated from the transmission-side frame pulse is used to force the reception-side synchronization signal generator to be phase-synchronized with the transmission-side vertical synchronization signal. The video transmission system according to claim 1, characterized in that