JPH05172896A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH05172896A JPH05172896A JP3003000A JP300091A JPH05172896A JP H05172896 A JPH05172896 A JP H05172896A JP 3003000 A JP3003000 A JP 3003000A JP 300091 A JP300091 A JP 300091A JP H05172896 A JPH05172896 A JP H05172896A
- Authority
- JP
- Japan
- Prior art keywords
- characteristic
- pad
- monitor transistor
- pads
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000005259 measurement Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特に外部端子からその特性を測定可能な特性チェック用
モニタトランジスタを有する半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit having a characteristic checking monitor transistor whose characteristic can be measured from an external terminal.
【0002】[0002]
【従来の技術】従来、半導体集積回路(IC)チップに
内蔵される特性チェック用モニタトランジスタは、IC
チップ内部の内部回路とは別に設けられて測定用パッド
に接続され、その特性を測定するには、測定用パッドに
ICテスタの探針をあて測定している。2. Description of the Related Art Conventionally, a characteristic check monitor transistor built in a semiconductor integrated circuit (IC) chip is an IC.
It is provided separately from the internal circuit inside the chip and is connected to a measurement pad. To measure the characteristics, a probe of an IC tester is applied to the measurement pad for measurement.
【0003】[0003]
【発明が解決しようとする課題】この従来のIC特性チ
ェック用モニタトランジスタでは、ウェーハまたはチッ
プとしての半導体単体での測定は可能であるが、完成品
のICとなってからはあらかじめ外部端子として特性チ
ェックトランジスタ専用のチェック用端子を用意してお
かないと測定が不可能であるという問題点があった。This conventional monitor transistor for checking the IC characteristics can measure the semiconductor alone as a wafer or a chip, but it cannot be measured as an external terminal in advance after it becomes a finished IC. There is a problem that measurement is impossible unless a check terminal dedicated to the check transistor is prepared.
【0004】本発明の目的は専用のチェック用端子なし
で外部端子からモニタトランジスタの測定ができる半導
体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit capable of measuring a monitor transistor from an external terminal without a dedicated check terminal.
【0005】[0005]
【課題を解決するための手段】本発明の半導体集積回路
は、複数の電源用および外部端用のパッドと、特性チェ
ック用のモニタトランジスタと、前記複数のパッドに接
続されている内部回路を有する半導体集積回路におい
て、前記電源用及び外部端用パッドと前記内部回路との
間にそれぞれドレイン・ソースが挿入されたスイッチ用
トランジスタを有し、前記モニタトランジスタのゲート
は前記電源用のパッドに接続されソース・ドレイン間は
前記外部端用のパッド間に挿入されて、前スイッチ用ト
ランジスタのゲートに前記電源用パッドから制御信号を
入力して前記モニタトランジスタを前記内部回路から切
離して構成されている。A semiconductor integrated circuit of the present invention has a plurality of power supply and external end pads, a characteristic checking monitor transistor, and an internal circuit connected to the plurality of pads. The semiconductor integrated circuit has switching transistors each having a drain / source inserted between the power supply / external end pad and the internal circuit, and a gate of the monitor transistor is connected to the power supply pad. The source / drain is inserted between the pads for the external end, and the monitor transistor is separated from the internal circuit by inputting a control signal from the power supply pad to the gate of the front switching transistor.
【0006】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の回路図である。ICは電
源用パッド1および外部端子パッド3a〜3bと内部回
路と間にそれぞれスイッチ用のPチャンネルトランジス
タ6a〜6cのドレイン・ソースを接続し、GND供給
端パッド2と内部回路との間にそれぞれスイッチ用のn
チャンネルトランジスタ7a〜7cのドレイン・ソース
を接続し、外部パッド3a,3b間にPチャンネル特性
チェック用モニタトランジスタ5の、またパッド3c,
3d間にnチャンネル特性チェック用モニタトランジス
タ4のドレイン・ソースをそれぞれ接続している。The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. The IC connects the drain and source of P-channel transistors 6a to 6c for switching between the power supply pad 1 and the external terminal pads 3a to 3b and the internal circuit, respectively, and connects the GND and the GND supply terminal pad 2 to the internal circuit, respectively. N for switch
The drains and sources of the channel transistors 7a to 7c are connected, and the P-channel characteristic check monitor transistor 5 and the pads 3c,
The drain and source of the n-channel characteristic checking monitor transistor 4 are connected between 3d.
【0007】通常の内部回路動作時はVDD供給端パッド
1とGND供給端パッド2から内部回路に電源電圧を供
給する。この時モニタトランジスタ6a〜6c及びモニ
タトランジスタ7a〜7cはスイッチ・オン状態とな
り、トランジスタ5とトランジスタ4はスイッチ・オフ
状態となり、外部端パッド3aと3b及び3cと3d
は、内部回路から独立状態となって通常の内部回路動作
が行われる。During normal operation of the internal circuit, the power supply voltage is supplied to the internal circuit from the V DD supply end pad 1 and the GND supply end pad 2. At this time, the monitor transistors 6a to 6c and the monitor transistors 7a to 7c are switched on, the transistors 5 and 4 are switched off, and the external end pads 3a and 3b and 3c and 3d.
Becomes an independent state from the internal circuit and normal internal circuit operation is performed.
【0008】特性チェック用モニタトランジスタ4又は
5の測定時は、VDD供給端パッド1にGNDレベルを、
GND供給端子パッド2にVDDレベルを供給することに
よって、Pチャンネルトランジスタ6a〜6c及びnチ
ャンネルトランジスタ7a〜7cはスイッチ・オフ状態
となり、内部配線8a〜8fを切断してVDD供給端パッ
ド1とGND供給端パッド2及び外部端パッド3a〜3
dを、内部回路から独立させる。When the characteristic check monitor transistor 4 or 5 is measured, the GND level is applied to the V DD supply end pad 1.
By supplying the V DD level to the GND supply terminal pad 2, the P-channel transistors 6a to 6c and the n-channel transistors 7a to 7c are switched off, and the internal wirings 8a to 8f are cut to disconnect the V DD supply end pad 1 And GND supply end pad 2 and external end pads 3a-3
d is independent of the internal circuit.
【0009】例えばPチャンネル特性チェック用モニタ
トランジスタ5の測定は上記の状態で外部端子3aと3
bを用いて行い、nチャンネル特性チェック用モニタト
ランジスタ4の測定は外部端子3cと3dを用いて内部
回路と独立に行う。For example, the P-channel characteristic checking monitor transistor 5 is measured in the above-described state with the external terminals 3a and 3a.
b, and the measurement of the n-channel characteristic checking monitor transistor 4 is performed independently of the internal circuit using the external terminals 3c and 3d.
【0010】[0010]
【発明の効果】以上説明したように本発明は半導体IC
の通常の電源供給用端子とGND端子及び外部端子を用
いて特性チェックトランジスタの特性測定を行えるよう
にしたので、半導体装置完成後も通常の端子を用いて外
部から特性チェック用モニタトランジスタの測定が行え
るという効果を有する。又内部回路の外部端子を測定に
用いるため、内部回路の試験時等に特性チェック用モニ
タトランジスタの特性測定を容易に自動測定できるとい
う効果も有する。As described above, the present invention is a semiconductor IC
Since the characteristic check transistor characteristics can be measured using the normal power supply terminal, the GND terminal, and the external terminal, the characteristic check monitor transistor can be externally measured using the normal terminal even after the semiconductor device is completed. It has the effect that it can be done. Further, since the external terminal of the internal circuit is used for the measurement, there is also an effect that the characteristic of the characteristic checking monitor transistor can be easily measured automatically when the internal circuit is tested.
【図1】本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.
1 VDD供給端パッド 2 GND供給端パッド 3a〜3d 外部端パッド 4 nチャンネル特性チェック用モニタトランジスタ 5 Pチャンネル特性チェック用モニタトランジスタ 6a〜6c Pチャンネルトランジスタ 7a〜7c nチャンネルトランジスタ 8a〜8f 内部配線1 V DD Supply End Pad 2 GND Supply End Pad 3a-3d External End Pad 4 n-Channel Characteristic Check Monitor Transistor 5 P-Channel Characteristic Check Monitor Transistor 6a-6c P-Channel Transistor 7a-7c n-Channel Transistor 8a-8f Internal Wiring
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成4年11月26日[Submission date] November 26, 1992
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】発明の名称[Name of item to be amended] Title of invention
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【発明の名称】 半導体集積回路Title: Semiconductor integrated circuit
Claims (1)
と、特性チェック用のモニタトランジスタと、前記複数
のパッドに接続されている内部回路を有する半導体集積
回路において、前記電源用及び外部端用パッドと前記内
部回路との間にそれぞれドレイン・ソースが挿入された
スイッチ用トランジスタを有し、前記モニタトランジス
タのゲートは前記電源用のパッドに接続されソース・ド
レイン間は前記外部端用のパッド間に挿入されて、前ス
イッチ用トランジスタのゲートに前記電源用パッドから
制御信号を入力して前記モニタトランジスタを前記内部
回路から切離すことを特徴とする半導体集積回路。1. A semiconductor integrated circuit having a plurality of power supply pads and external end pads, a characteristic checking monitor transistor, and an internal circuit connected to the plurality of pads, wherein the power supply end and the external end end are provided. A switch transistor having a drain and a source respectively inserted between the pad and the internal circuit; a gate of the monitor transistor is connected to the power supply pad; and a source and a drain between the pad for the external end. And a control signal is input to the gate of the front switching transistor from the power supply pad to disconnect the monitor transistor from the internal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3003000A JP2665054B2 (en) | 1991-01-16 | 1991-01-16 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3003000A JP2665054B2 (en) | 1991-01-16 | 1991-01-16 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05172896A true JPH05172896A (en) | 1993-07-13 |
| JP2665054B2 JP2665054B2 (en) | 1997-10-22 |
Family
ID=11545106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3003000A Expired - Fee Related JP2665054B2 (en) | 1991-01-16 | 1991-01-16 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2665054B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362641B2 (en) | 1998-08-25 | 2002-03-26 | Nec Corporation | Integrated circuit device and semiconductor wafer having test circuit therein |
| KR100408943B1 (en) * | 2000-06-16 | 2003-12-11 | 인피니언 테크놀로지스 아게 | Integrated circuit with test mode and test device for testing the same |
-
1991
- 1991-01-16 JP JP3003000A patent/JP2665054B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362641B2 (en) | 1998-08-25 | 2002-03-26 | Nec Corporation | Integrated circuit device and semiconductor wafer having test circuit therein |
| KR100408943B1 (en) * | 2000-06-16 | 2003-12-11 | 인피니언 테크놀로지스 아게 | Integrated circuit with test mode and test device for testing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2665054B2 (en) | 1997-10-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970603 |
|
| LAPS | Cancellation because of no payment of annual fees |